#ifndef morpheo_behavioural_Constants_h #define morpheo_behavioural_Constants_h namespace morpheo { namespace behavioural { //=========================================================[ Type ]===== #define TYPE_MEMORY 0x1 // 00001 //====================================================[ Operation ]===== //-------------------------------------------------------[ Memory ]----- #define OPERATION_MEMORY_LOAD_8_Z 0x0 // 000_0000 #define OPERATION_MEMORY_LOAD_16_Z 0x20 // 010_0000 #define OPERATION_MEMORY_LOAD_32_Z 0x40 // 100_0000 #define OPERATION_MEMORY_LOAD_64_Z 0x60 // 110_0000 #define OPERATION_MEMORY_LOAD_8_S 0x10 // 001_0000 #define OPERATION_MEMORY_LOAD_16_S 0x30 // 011_0000 #define OPERATION_MEMORY_LOAD_32_S 0x50 // 101_0000 #define OPERATION_MEMORY_LOAD_64_S 0x70 // 111_0000 #define OPERATION_MEMORY_STORE_8 0x8 // 000_1000 #define OPERATION_MEMORY_STORE_16 0x9 // 000_1001 #define OPERATION_MEMORY_STORE_32 0xa // 000_1010 #define OPERATION_MEMORY_STORE_64 0xb // 000_1011 #define OPERATION_MEMORY_STORE_HEAD_OK 0xc // 000_1100 #define OPERATION_MEMORY_STORE_HEAD_KO 0xd // 000_1101 #define OPERATION_MEMORY_LOCK 0x1 // 000_0001 #define OPERATION_MEMORY_INVALIDATE 0x2 // 000_0010 #define OPERATION_MEMORY_PREFETCH 0x3 // 000_0011 #define OPERATION_MEMORY_FLUSH 0x6 // 000_0110 #define OPERATION_MEMORY_SYNCHRONIZATION 0x7 // 000_0111 #define is_operation_memory_load(x) \ ((x == OPERATION_MEMORY_LOAD_8_Z ) or \ (x == OPERATION_MEMORY_LOAD_16_Z) or \ (x == OPERATION_MEMORY_LOAD_32_Z) or \ (x == OPERATION_MEMORY_LOAD_64_Z) or \ (x == OPERATION_MEMORY_LOAD_8_S ) or \ (x == OPERATION_MEMORY_LOAD_16_S) or \ (x == OPERATION_MEMORY_LOAD_32_S) or \ (x == OPERATION_MEMORY_LOAD_64_S) ) #define is_operation_memory_store(x) \ ((x == OPERATION_MEMORY_STORE_8 ) or \ (x == OPERATION_MEMORY_STORE_16 ) or \ (x == OPERATION_MEMORY_STORE_32 ) or \ (x == OPERATION_MEMORY_STORE_64 ) or \ (x == OPERATION_MEMORY_STORE_HEAD_OK) or \ (x == OPERATION_MEMORY_STORE_HEAD_KO)) #define is_operation_memory_store_head(x) \ ((x == OPERATION_MEMORY_STORE_HEAD_OK) or \ (x == OPERATION_MEMORY_STORE_HEAD_KO)) #define MEMORY_ACCESS_8 0x0 #define MEMORY_ACCESS_16 0x1 #define MEMORY_ACCESS_32 0x2 #define MEMORY_ACCESS_64 0x3 #define MASK_MEMORY_ACCESS_8 0x0 #define MASK_MEMORY_ACCESS_16 0x1 #define MASK_MEMORY_ACCESS_32 0x3 #define MASK_MEMORY_ACCESS_64 0x7 #define memory_access(x) \ (((x==OPERATION_MEMORY_LOAD_16_Z)or \ (x==OPERATION_MEMORY_LOAD_16_S)or \ (x==OPERATION_MEMORY_STORE_16 ))?MEMORY_ACCESS_16: \ (((x==OPERATION_MEMORY_LOAD_32_Z)or \ (x==OPERATION_MEMORY_LOAD_32_S)or \ (x==OPERATION_MEMORY_STORE_32 ))?MEMORY_ACCESS_32: \ (((x==OPERATION_MEMORY_LOAD_64_Z)or \ (x==OPERATION_MEMORY_LOAD_64_S)or \ (x==OPERATION_MEMORY_STORE_64 ))?MEMORY_ACCESS_64:MEMORY_ACCESS_8))) #define mask_memory_access(x) \ (((x==OPERATION_MEMORY_LOAD_16_Z)or \ (x==OPERATION_MEMORY_LOAD_16_S)or \ (x==OPERATION_MEMORY_STORE_16 ))?MASK_MEMORY_ACCESS_16: \ (((x==OPERATION_MEMORY_LOAD_32_Z)or \ (x==OPERATION_MEMORY_LOAD_32_S)or \ (x==OPERATION_MEMORY_STORE_32 ))?MASK_MEMORY_ACCESS_32: \ (((x==OPERATION_MEMORY_LOAD_64_Z)or \ (x==OPERATION_MEMORY_LOAD_64_S)or \ (x==OPERATION_MEMORY_STORE_64 ))?MASK_MEMORY_ACCESS_64:MASK_MEMORY_ACCESS_8))) //====================================================[ Exception ]===== // Exception - OpenRISC #define EXCEPTION_NONE 0x00 // none exception #define EXCEPTION_RESET 0x01 // software or hardware reset #define EXCEPTION_BUS_ERROR 0x02 // Access at a invalid physical adress #define EXCEPTION_DATA_PAGE 0x03 // No matching or page violation protection in pages tables #define EXCEPTION_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables #define EXCEPTION_TICK_TIMER 0x05 // Tick timer interruption #define EXCEPTION_ALIGNMENT 0x06 // Load/Store access is not aligned #define EXCEPTION_ILLEGAL_INSTRUCTION 0x07 // Instruction is illegal (no implemented) #define EXCEPTION_INTERRUPT 0x08 // External interruption #define EXCEPTION_DATA_TLB 0x09 // DTLB miss #define EXCEPTION_INSTRUCTION_TLB 0x0a // ITLB miss #define EXCEPTION_RANGE 0x0b // Overflow or access at a unimplemented register or context #define EXCEPTION_SYSCALL 0x0c // System Call #define EXCEPTION_FLOATING_POINT 0x0d // Caused by a floating instruction #define EXCEPTION_TRAP 0x0e // L.trap or debug unit #define EXCEPTION_RESERVED_0 0x0f // Reserved for a futur usage #define EXCEPTION_RESERVED_1 0x10 // Reserved for a futur usage #define EXCEPTION_RESERVED_2 0x11 // Reserved for a futur usage #define EXCEPTION_RESERVED_3 0x12 // Reserved for a futur usage #define EXCEPTION_RESERVED_4 0x13 // Reserved for a futur usage #define EXCEPTION_RESERVED_5 0x14 // Reserved for a futur usage #define EXCEPTION_RESERVED_6 0x15 // Reserved for implemented specific exceptions #define EXCEPTION_RESERVED_7 0x16 // Reserved for implemented specific exceptions #define EXCEPTION_RESERVED_8 0x17 // Reserved for implemented specific exceptions #define EXCEPTION_RESERVED_9 0x18 // Reserved for implemented specific exceptions #define EXCEPTION_CUSTOM_0 0x19 // Reserved for custom exceptions #define EXCEPTION_CUSTOM_1 0x1a // Reserved for custom exceptions #define EXCEPTION_CUSTOM_2 0x1b // Reserved for custom exceptions #define EXCEPTION_CUSTOM_3 0x1c // Reserved for custom exceptions #define EXCEPTION_CUSTOM_4 0x1d // Reserved for custom exceptions #define EXCEPTION_CUSTOM_5 0x1e // Reserved for custom exceptions #define EXCEPTION_CUSTOM_6 0x1f // Reserved for custom exceptions // Exception Execution #define EXCEPTION_MEMORY_NONE 0x0 // Load/Store access is not aligned #define EXCEPTION_MEMORY_ALIGNMENT 0x1 // Load/Store access is not aligned #define EXCEPTION_MEMORY_DATA_TLB 0x2 // DTLB miss #define EXCEPTION_MEMORY_DATA_PAGE 0x3 // No matching or page violation protection in pages tables #define EXCEPTION_MEMORY_BUS_ERROR 0x4 // Access at a invalid physical address #define EXCEPTION_MEMORY_MISS_SPECULATION 0x5 // Load miss speculation /* #define _size_instruction 32 #define _size_instruction_log2 5 //----------------------------------------------------[ Operation ]----- // #define _nb_operation 32 // #define _size_operation 5 #define _operation_none 0x0 #define _operation_l_adds 0x1 #define _operation_l_addu 0x2 #define _operation_l_subs 0x3 #define _operation_l_and 0x4 #define _operation_l_or 0x5 #define _operation_l_xor 0x6 #define _operation_l_cmove 0x7 #define _operation_l_read_imm 0x8 #define _operation_l_movhi 0x9 #define _operation_l_muls 0xa #define _operation_l_mulu 0xb #define _operation_l_divs 0xc #define _operation_l_divu 0xd #define _operation_l_exts 0xe #define _operation_l_extz 0xf #define _operation_l_ff1 0x10 #define _operation_l_fl1 0x11 #define _operation_l_sll 0x12 #define _operation_l_sla 0x13 #define _operation_l_srl 0x14 #define _operation_l_ror 0x15 #define _operation_l_cmp_eq 0x16 #define _operation_l_cmp_ne 0x17 #define _operation_l_cmp_ges 0x18 #define _operation_l_cmp_geu 0x19 #define _operation_l_cmp_gts 0x1a #define _operation_l_cmp_gtu 0x1b #define _operation_l_cmp_les 0x1c #define _operation_l_cmp_leu 0x1d #define _operation_l_cmp_lts 0x1e #define _operation_l_cmp_ltu 0x1f //--------------------------------------------------[ destination ]----- #define _size_destination1 4 #define cst_DESTINATION1_NONE 0x0 #define mask_DESTINATION1_GPR 0x1 #define mask_DESTINATION1_MEMORY 0x2 #define mask_DESTINATION1_SPR 0x4 #define mask_DESTINATION1_MAC_UNIT 0x8 #define _size_destination2 3 #define cst_DESTINATION2_NONE 0x0 #define mask_DESTINATION2_COMMIT 0x1 #define mask_DESTINATION2_MEMORY 0x2 #define mask_DESTINATION2_SPR 0x4 //----------------------------------------------------[ exec_flag ]----- #define _size_exec_flag 2 #define mask_EXEC_FLAG_NONE 0x1 #define mask_EXEC_FLAG_CARRY 0x1 #define mask_EXEC_FLAG_FLAG 0x1 #define mask_EXEC_FLAG_OVERFLOW 0x2 //---------------------------------------------------[ exec_excep ]----- #define _size_exec_excep 1 #define mask_EXEC_EXCEP_NONE 0x0 #define mask_EXEC_EXCEP_RANGE 0x1 //----------------------------------------------------[ Condition ]----- #define _size_condition 3 #define cst_CONDITION_UNCONDITIONAL 0x0 // None condition (jump) #define mask_CONDITION_CONDITIONAL 0x2 #define mask_CONDITION_CONDITIONAL_NF 0x0 // Branch if Flag is clear #define mask_CONDITION_CONDITIONAL_F 0x1 // Branch if Flag is set #define mask_CONDITION_REG 0x4 // Branch if a register is read #define mask_CONDITION_STACK 0x8 // Branch with pop in stack pointer //-------------------------------------------------[ branch_state ]----- #define cst_BRANCH_STATE_NONE 0x0 // 0 0 #define cst_BRANCH_STATE_NSPEC_TAKE 0x1 // 0 1 -> incondionnal #define cst_BRANCH_STATE_SPEC_NTAKE 0x2 // 1 0 #define cst_BRANCH_STATE_SPEC_TAKE 0x3 // 1 1 */ /* #define M_CPU_SIZE_INST 32 //---------------------------------------------------- // Exception type //---------------------------------------------------- #define M_CPU_LOG2_NB_EXCP 5 #define M_CPU_NB_EXCP 32 #define EXCP_NO 0x00 // none exception #define EXCP_RESET 0x01 // software or hardware reset #define EXCP_BERR 0x02 // Access at a invalid physical adress #define EXCP_D_PAGE 0x03 // No matching or page violation protection in pages tables #define EXCP_I_PAGE 0x04 // No matching or page violation protection in pages tables #define EXCP_TICK_TIMER 0x05 // Tick timer interruption #define EXCP_ALIGNMENT 0x06 // Load/Store access is not aligned #define EXCP_ILL_INST 0x07 // Instruction is illegal (no implemented) #define EXCP_IRQ 0x08 // External interruption #define EXCP_D_TLB 0x09 // DTLB miss #define EXCP_I_TLB 0x0a // ITLB miss #define EXCP_RANGE 0x0b // Overflow or access at a unimplemented register or context #define EXCP_SYSCALL 0x0c // System Call #define EXCP_FP 0x0d // Caused by a floating instruction #define EXCP_TRAP 0x0e // L.trap or debug unit #define EXCP_RES0 0x0f // Reserved for a futur usage #define EXCP_RES1 0x10 // Reserved for a futur usage #define EXCP_RES2 0x11 // Reserved for a futur usage #define EXCP_RES3 0x12 // Reserved for a futur usage #define EXCP_RES4 0x13 // Reserved for a futur usage #define EXCP_RES5 0x14 // Reserved for a futur usage #define EXCP_RES6 0x15 // Reserved for implemented specific exceptions #define EXCP_RES7 0x16 // Reserved for implemented specific exceptions #define EXCP_RES8 0x17 // Reserved for implemented specific exceptions #define EXCP_RES9 0x18 // Reserved for implemented specific exceptions #define EXCP_CUST0 0x19 // Reserved for custom exceptions #define EXCP_CUST1 0x1a // Reserved for custom exceptions #define EXCP_CUST2 0x1b // Reserved for custom exceptions #define EXCP_CUST3 0x1c // Reserved for custom exceptions #define EXCP_CUST4 0x1d // Reserved for custom exceptions #define EXCP_CUST5 0x1e // Reserved for custom exceptions #define EXCP_CUST6 0x1f // Reserved for custom exceptions //---------------------------------------------------- // Flags //---------------------------------------------------- #define M_CPU_NB_FLAG 3 // Integer flags #define FLAG_F 0x1 // Conditionnal branch flag #define FLAG_CY 0x2 // Carry was produced by last arithmétic operation #define FLAG_OV 0x4 // Overflow occured during last arithmetic operation // Floating flags #define FLAG_OVF 0x004 // Overflow occured during last arithmetic operation #define FLAG_UNF 0x008 // Underflow flags #define FLAG_SNF 0x010 // Result SNAN #define FLAG_QNF 0x020 // Result QNAN #define FLAG_ZF 0x040 // Result is nul #define FLAG_IXF 0x080 // Result is inexact #define FLAG_IVF 0x100 // Result is invalid #define FLAG_INF 0x200 // Result is infinite #define FLAG_DZF 0x400 // Division by zero // Position of flag in "rename register SR" (NOT IN "SR") #define FLAG_POS_F 0x0 // Conditionnal branch flag #define FLAG_POS_CY 0x1 // Carry was produced by last arithmétic operation #define FLAG_POS_OV 0x0 // Overflow occured during last arithmetic operation //---------------------------------------------------- // Instruction type //---------------------------------------------------- #define M_CPU_LOG2_NB_TYPE 4 #define TYPE_NOP 0x0 #define TYPE_ALU_F 0x1 // Instruction ALU with flag using (ADD, SUB, ADDC ...) #define TYPE_ALU_NF 0x2 // Instruction ALU without flag using (AND, OR ...) #define TYPE_MAC 0x3 // Instruction ALU with utilisation of register HI/LO #define TYPE_J 0x4 // Branch instruction #define TYPE_SPR_READ 0x5 // Instruction special : l.mfspr #define TYPE_SPR_WRITE 0x6 // Instruction special : l.mtspr #define TYPE_SPECIAL 0x7 // Instruction execute in decode stage #define TYPE_CUSTOM 0x8 // Instruction Custom #define TYPE_LOAD_Z 0x9 // Load access (extended by zero) #define TYPE_LOAD_S 0xa // Load access (sign extended) #define TYPE_STORE 0xc // Store access //---------------------------------------------------- // Condition to branch //---------------------------------------------------- #define M_CPU_LOG2_NB_COND 4 #define COND_NONE 0x0 // None condition (jump) #define COND_F 0x2 // Branch if Flag is set #define COND_NF 0x3 // Branch if Flag is clear #define COND_REG 0x4 // Branch if a register is read #define COND_STACK 0x8 // Branch with pop in stack pointer //---------------------------------------------------- // Event : State and Type //---------------------------------------------------- #define EVENT_STATE_NO_EVENT 0 // no event : current case #define EVENT_STATE_EVENT 1 // Have a event : make necessary to manage the event #define EVENT_STATE_WAITEND 2 // Wait end of manage event (restaure a good context) #define EVENT_STATE_END 3 // CPU can continue #define EVENT_TYPE_MISS 0 // miss of speculation #define EVENT_TYPE_EXCP 1 // exception or interruption occure // SPEC? TAKE? #define BRANCH_STATE_NONE 0 // 0 0 #define BRANCH_STATE_NSPEC_TAKE 1 // 0 1 -> incondionnal #define BRANCH_STATE_SPEC_NTAKE 2 // 1 0 #define BRANCH_STATE_SPEC_TAKE 3 // 1 1 //---------------------------------------------------- // Name to particular register //---------------------------------------------------- //~~~~~~~~~~~~~~~~~~~~~~~~~~ // GENERAL PURPOSE REGISTER //~~~~~~~~~~~~~~~~~~~~~~~~~~ #define M_CPU_LOG2_NB_GPR_LOG 5 #define M_CPU_NB_GPR_LOG (1< INST_L_NO_IMPLEMENTED //#define NB_INST_L (INST_L_NO_IMPLEMENTED+1) */ }; // end namespace behavioural }; // end namespace morpheo #endif