1 | #ifndef morpheo_behavioural_Constants_h |
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2 | #define morpheo_behavioural_Constants_h |
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3 | |
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4 | namespace morpheo { |
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5 | namespace behavioural { |
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6 | |
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7 | //=========================================================[ Type ]===== |
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8 | #define TYPE_MEMORY 0x1 // 00001 |
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9 | |
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10 | //====================================================[ Operation ]===== |
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11 | |
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12 | //-------------------------------------------------------[ Memory ]----- |
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13 | #define OPERATION_MEMORY_LOAD_8_Z 0x0 // 000_0000 |
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14 | #define OPERATION_MEMORY_LOAD_16_Z 0x20 // 010_0000 |
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15 | #define OPERATION_MEMORY_LOAD_32_Z 0x40 // 100_0000 |
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16 | #define OPERATION_MEMORY_LOAD_64_Z 0x60 // 110_0000 |
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17 | #define OPERATION_MEMORY_LOAD_8_S 0x10 // 001_0000 |
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18 | #define OPERATION_MEMORY_LOAD_16_S 0x30 // 011_0000 |
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19 | #define OPERATION_MEMORY_LOAD_32_S 0x50 // 101_0000 |
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20 | #define OPERATION_MEMORY_LOAD_64_S 0x70 // 111_0000 |
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21 | |
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22 | #define OPERATION_MEMORY_STORE_8 0x8 // 000_1000 |
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23 | #define OPERATION_MEMORY_STORE_16 0x9 // 000_1001 |
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24 | #define OPERATION_MEMORY_STORE_32 0xa // 000_1010 |
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25 | #define OPERATION_MEMORY_STORE_64 0xb // 000_1011 |
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26 | #define OPERATION_MEMORY_STORE_HEAD_OK 0xc // 000_1100 |
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27 | #define OPERATION_MEMORY_STORE_HEAD_KO 0xd // 000_1101 |
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28 | |
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29 | #define OPERATION_MEMORY_LOCK 0x1 // 000_0001 |
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30 | #define OPERATION_MEMORY_INVALIDATE 0x2 // 000_0010 |
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31 | #define OPERATION_MEMORY_PREFETCH 0x3 // 000_0011 |
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32 | #define OPERATION_MEMORY_FLUSH 0x6 // 000_0110 |
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33 | #define OPERATION_MEMORY_SYNCHRONIZATION 0x7 // 000_0111 |
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34 | |
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35 | #define is_operation_memory_load(x) \ |
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36 | ((x == OPERATION_MEMORY_LOAD_8_Z ) or \ |
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37 | (x == OPERATION_MEMORY_LOAD_16_Z) or \ |
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38 | (x == OPERATION_MEMORY_LOAD_32_Z) or \ |
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39 | (x == OPERATION_MEMORY_LOAD_64_Z) or \ |
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40 | (x == OPERATION_MEMORY_LOAD_8_S ) or \ |
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41 | (x == OPERATION_MEMORY_LOAD_16_S) or \ |
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42 | (x == OPERATION_MEMORY_LOAD_32_S) or \ |
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43 | (x == OPERATION_MEMORY_LOAD_64_S) ) |
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44 | |
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45 | #define is_operation_memory_store(x) \ |
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46 | ((x == OPERATION_MEMORY_STORE_8 ) or \ |
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47 | (x == OPERATION_MEMORY_STORE_16 ) or \ |
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48 | (x == OPERATION_MEMORY_STORE_32 ) or \ |
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49 | (x == OPERATION_MEMORY_STORE_64 ) or \ |
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50 | (x == OPERATION_MEMORY_STORE_HEAD_OK) or \ |
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51 | (x == OPERATION_MEMORY_STORE_HEAD_KO)) |
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52 | |
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53 | #define is_operation_memory_store_head(x) \ |
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54 | ((x == OPERATION_MEMORY_STORE_HEAD_OK) or \ |
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55 | (x == OPERATION_MEMORY_STORE_HEAD_KO)) |
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56 | |
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57 | #define MEMORY_ACCESS_8 0x0 |
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58 | #define MEMORY_ACCESS_16 0x1 |
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59 | #define MEMORY_ACCESS_32 0x2 |
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60 | #define MEMORY_ACCESS_64 0x3 |
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61 | |
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62 | #define MASK_MEMORY_ACCESS_8 0x0 |
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63 | #define MASK_MEMORY_ACCESS_16 0x1 |
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64 | #define MASK_MEMORY_ACCESS_32 0x3 |
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65 | #define MASK_MEMORY_ACCESS_64 0x7 |
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66 | |
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67 | #define memory_access(x) \ |
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68 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
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69 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
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70 | (x==OPERATION_MEMORY_STORE_16 ))?MEMORY_ACCESS_16: \ |
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71 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
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72 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
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73 | (x==OPERATION_MEMORY_STORE_32 ))?MEMORY_ACCESS_32: \ |
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74 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
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75 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
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76 | (x==OPERATION_MEMORY_STORE_64 ))?MEMORY_ACCESS_64:MEMORY_ACCESS_8))) |
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77 | |
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78 | #define mask_memory_access(x) \ |
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79 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
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80 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
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81 | (x==OPERATION_MEMORY_STORE_16 ))?MASK_MEMORY_ACCESS_16: \ |
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82 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
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83 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
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84 | (x==OPERATION_MEMORY_STORE_32 ))?MASK_MEMORY_ACCESS_32: \ |
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85 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
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86 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
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87 | (x==OPERATION_MEMORY_STORE_64 ))?MASK_MEMORY_ACCESS_64:MASK_MEMORY_ACCESS_8))) |
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88 | |
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89 | |
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90 | //====================================================[ Exception ]===== |
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91 | // Exception - OpenRISC |
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92 | |
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93 | #define EXCEPTION_NONE 0x00 // none exception |
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94 | #define EXCEPTION_RESET 0x01 // software or hardware reset |
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95 | #define EXCEPTION_BUS_ERROR 0x02 // Access at a invalid physical adress |
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96 | #define EXCEPTION_DATA_PAGE 0x03 // No matching or page violation protection in pages tables |
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97 | #define EXCEPTION_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables |
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98 | #define EXCEPTION_TICK_TIMER 0x05 // Tick timer interruption |
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99 | #define EXCEPTION_ALIGNMENT 0x06 // Load/Store access is not aligned |
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100 | #define EXCEPTION_ILLEGAL_INSTRUCTION 0x07 // Instruction is illegal (no implemented) |
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101 | #define EXCEPTION_INTERRUPT 0x08 // External interruption |
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102 | #define EXCEPTION_DATA_TLB 0x09 // DTLB miss |
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103 | #define EXCEPTION_INSTRUCTION_TLB 0x0a // ITLB miss |
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104 | #define EXCEPTION_RANGE 0x0b // Overflow or access at a unimplemented register or context |
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105 | #define EXCEPTION_SYSCALL 0x0c // System Call |
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106 | #define EXCEPTION_FLOATING_POINT 0x0d // Caused by a floating instruction |
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107 | #define EXCEPTION_TRAP 0x0e // L.trap or debug unit |
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108 | #define EXCEPTION_RESERVED_0 0x0f // Reserved for a futur usage |
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109 | #define EXCEPTION_RESERVED_1 0x10 // Reserved for a futur usage |
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110 | #define EXCEPTION_RESERVED_2 0x11 // Reserved for a futur usage |
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111 | #define EXCEPTION_RESERVED_3 0x12 // Reserved for a futur usage |
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112 | #define EXCEPTION_RESERVED_4 0x13 // Reserved for a futur usage |
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113 | #define EXCEPTION_RESERVED_5 0x14 // Reserved for a futur usage |
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114 | #define EXCEPTION_RESERVED_6 0x15 // Reserved for implemented specific exceptions |
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115 | #define EXCEPTION_RESERVED_7 0x16 // Reserved for implemented specific exceptions |
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116 | #define EXCEPTION_RESERVED_8 0x17 // Reserved for implemented specific exceptions |
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117 | #define EXCEPTION_RESERVED_9 0x18 // Reserved for implemented specific exceptions |
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118 | #define EXCEPTION_CUSTOM_0 0x19 // Reserved for custom exceptions |
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119 | #define EXCEPTION_CUSTOM_1 0x1a // Reserved for custom exceptions |
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120 | #define EXCEPTION_CUSTOM_2 0x1b // Reserved for custom exceptions |
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121 | #define EXCEPTION_CUSTOM_3 0x1c // Reserved for custom exceptions |
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122 | #define EXCEPTION_CUSTOM_4 0x1d // Reserved for custom exceptions |
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123 | #define EXCEPTION_CUSTOM_5 0x1e // Reserved for custom exceptions |
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124 | #define EXCEPTION_CUSTOM_6 0x1f // Reserved for custom exceptions |
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125 | |
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126 | // Exception Execution |
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127 | #define EXCEPTION_MEMORY_NONE 0x0 // Load/Store access is not aligned |
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128 | #define EXCEPTION_MEMORY_ALIGNMENT 0x1 // Load/Store access is not aligned |
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129 | #define EXCEPTION_MEMORY_DATA_TLB 0x2 // DTLB miss |
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130 | #define EXCEPTION_MEMORY_DATA_PAGE 0x3 // No matching or page violation protection in pages tables |
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131 | #define EXCEPTION_MEMORY_BUS_ERROR 0x4 // Access at a invalid physical address |
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132 | #define EXCEPTION_MEMORY_MISS_SPECULATION 0x5 // Load miss speculation |
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133 | |
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134 | /* |
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135 | #define _size_instruction 32 |
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136 | #define _size_instruction_log2 5 |
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137 | |
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138 | //----------------------------------------------------[ Operation ]----- |
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139 | // #define _nb_operation 32 |
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140 | // #define _size_operation 5 |
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141 | |
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142 | #define _operation_none 0x0 |
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143 | #define _operation_l_adds 0x1 |
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144 | #define _operation_l_addu 0x2 |
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145 | #define _operation_l_subs 0x3 |
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146 | #define _operation_l_and 0x4 |
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147 | #define _operation_l_or 0x5 |
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148 | #define _operation_l_xor 0x6 |
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149 | #define _operation_l_cmove 0x7 |
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150 | #define _operation_l_read_imm 0x8 |
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151 | #define _operation_l_movhi 0x9 |
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152 | #define _operation_l_muls 0xa |
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153 | #define _operation_l_mulu 0xb |
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154 | #define _operation_l_divs 0xc |
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155 | #define _operation_l_divu 0xd |
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156 | #define _operation_l_exts 0xe |
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157 | #define _operation_l_extz 0xf |
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158 | #define _operation_l_ff1 0x10 |
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159 | #define _operation_l_fl1 0x11 |
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160 | #define _operation_l_sll 0x12 |
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161 | #define _operation_l_sla 0x13 |
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162 | #define _operation_l_srl 0x14 |
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163 | #define _operation_l_ror 0x15 |
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164 | #define _operation_l_cmp_eq 0x16 |
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165 | #define _operation_l_cmp_ne 0x17 |
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166 | #define _operation_l_cmp_ges 0x18 |
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167 | #define _operation_l_cmp_geu 0x19 |
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168 | #define _operation_l_cmp_gts 0x1a |
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169 | #define _operation_l_cmp_gtu 0x1b |
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170 | #define _operation_l_cmp_les 0x1c |
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171 | #define _operation_l_cmp_leu 0x1d |
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172 | #define _operation_l_cmp_lts 0x1e |
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173 | #define _operation_l_cmp_ltu 0x1f |
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174 | |
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175 | //--------------------------------------------------[ destination ]----- |
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176 | #define _size_destination1 4 |
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177 | |
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178 | #define cst_DESTINATION1_NONE 0x0 |
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179 | #define mask_DESTINATION1_GPR 0x1 |
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180 | #define mask_DESTINATION1_MEMORY 0x2 |
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181 | #define mask_DESTINATION1_SPR 0x4 |
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182 | #define mask_DESTINATION1_MAC_UNIT 0x8 |
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183 | |
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184 | #define _size_destination2 3 |
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185 | |
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186 | #define cst_DESTINATION2_NONE 0x0 |
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187 | #define mask_DESTINATION2_COMMIT 0x1 |
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188 | #define mask_DESTINATION2_MEMORY 0x2 |
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189 | #define mask_DESTINATION2_SPR 0x4 |
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190 | |
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191 | //----------------------------------------------------[ exec_flag ]----- |
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192 | #define _size_exec_flag 2 |
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193 | |
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194 | #define mask_EXEC_FLAG_NONE 0x1 |
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195 | #define mask_EXEC_FLAG_CARRY 0x1 |
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196 | #define mask_EXEC_FLAG_FLAG 0x1 |
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197 | #define mask_EXEC_FLAG_OVERFLOW 0x2 |
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198 | |
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199 | //---------------------------------------------------[ exec_excep ]----- |
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200 | #define _size_exec_excep 1 |
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201 | |
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202 | #define mask_EXEC_EXCEP_NONE 0x0 |
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203 | #define mask_EXEC_EXCEP_RANGE 0x1 |
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204 | |
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205 | //----------------------------------------------------[ Condition ]----- |
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206 | #define _size_condition 3 |
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207 | |
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208 | #define cst_CONDITION_UNCONDITIONAL 0x0 // None condition (jump) |
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209 | #define mask_CONDITION_CONDITIONAL 0x2 |
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210 | #define mask_CONDITION_CONDITIONAL_NF 0x0 // Branch if Flag is clear |
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211 | #define mask_CONDITION_CONDITIONAL_F 0x1 // Branch if Flag is set |
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212 | #define mask_CONDITION_REG 0x4 // Branch if a register is read |
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213 | #define mask_CONDITION_STACK 0x8 // Branch with pop in stack pointer |
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214 | |
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215 | //-------------------------------------------------[ branch_state ]----- |
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216 | #define cst_BRANCH_STATE_NONE 0x0 // 0 0 |
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217 | #define cst_BRANCH_STATE_NSPEC_TAKE 0x1 // 0 1 -> incondionnal |
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218 | #define cst_BRANCH_STATE_SPEC_NTAKE 0x2 // 1 0 |
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219 | #define cst_BRANCH_STATE_SPEC_TAKE 0x3 // 1 1 |
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220 | */ |
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221 | |
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222 | /* |
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223 | #define M_CPU_SIZE_INST 32 |
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224 | |
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225 | //---------------------------------------------------- |
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226 | // Exception type |
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227 | //---------------------------------------------------- |
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228 | |
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229 | #define M_CPU_LOG2_NB_EXCP 5 |
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230 | #define M_CPU_NB_EXCP 32 |
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231 | |
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232 | #define EXCP_NO 0x00 // none exception |
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233 | #define EXCP_RESET 0x01 // software or hardware reset |
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234 | #define EXCP_BERR 0x02 // Access at a invalid physical adress |
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235 | #define EXCP_D_PAGE 0x03 // No matching or page violation protection in pages tables |
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236 | #define EXCP_I_PAGE 0x04 // No matching or page violation protection in pages tables |
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237 | #define EXCP_TICK_TIMER 0x05 // Tick timer interruption |
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238 | #define EXCP_ALIGNMENT 0x06 // Load/Store access is not aligned |
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239 | #define EXCP_ILL_INST 0x07 // Instruction is illegal (no implemented) |
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240 | #define EXCP_IRQ 0x08 // External interruption |
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241 | #define EXCP_D_TLB 0x09 // DTLB miss |
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242 | #define EXCP_I_TLB 0x0a // ITLB miss |
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243 | #define EXCP_RANGE 0x0b // Overflow or access at a unimplemented register or context |
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244 | #define EXCP_SYSCALL 0x0c // System Call |
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245 | #define EXCP_FP 0x0d // Caused by a floating instruction |
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246 | #define EXCP_TRAP 0x0e // L.trap or debug unit |
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247 | #define EXCP_RES0 0x0f // Reserved for a futur usage |
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248 | #define EXCP_RES1 0x10 // Reserved for a futur usage |
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249 | #define EXCP_RES2 0x11 // Reserved for a futur usage |
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250 | #define EXCP_RES3 0x12 // Reserved for a futur usage |
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251 | #define EXCP_RES4 0x13 // Reserved for a futur usage |
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252 | #define EXCP_RES5 0x14 // Reserved for a futur usage |
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253 | #define EXCP_RES6 0x15 // Reserved for implemented specific exceptions |
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254 | #define EXCP_RES7 0x16 // Reserved for implemented specific exceptions |
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255 | #define EXCP_RES8 0x17 // Reserved for implemented specific exceptions |
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256 | #define EXCP_RES9 0x18 // Reserved for implemented specific exceptions |
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257 | #define EXCP_CUST0 0x19 // Reserved for custom exceptions |
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258 | #define EXCP_CUST1 0x1a // Reserved for custom exceptions |
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259 | #define EXCP_CUST2 0x1b // Reserved for custom exceptions |
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260 | #define EXCP_CUST3 0x1c // Reserved for custom exceptions |
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261 | #define EXCP_CUST4 0x1d // Reserved for custom exceptions |
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262 | #define EXCP_CUST5 0x1e // Reserved for custom exceptions |
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263 | #define EXCP_CUST6 0x1f // Reserved for custom exceptions |
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264 | |
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265 | //---------------------------------------------------- |
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266 | // Flags |
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267 | //---------------------------------------------------- |
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268 | |
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269 | #define M_CPU_NB_FLAG 3 |
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270 | |
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271 | // Integer flags |
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272 | #define FLAG_F 0x1 // Conditionnal branch flag |
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273 | #define FLAG_CY 0x2 // Carry was produced by last arithmétic operation |
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274 | #define FLAG_OV 0x4 // Overflow occured during last arithmetic operation |
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275 | |
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276 | // Floating flags |
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277 | #define FLAG_OVF 0x004 // Overflow occured during last arithmetic operation |
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278 | #define FLAG_UNF 0x008 // Underflow flags |
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279 | #define FLAG_SNF 0x010 // Result SNAN |
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280 | #define FLAG_QNF 0x020 // Result QNAN |
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281 | #define FLAG_ZF 0x040 // Result is nul |
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282 | #define FLAG_IXF 0x080 // Result is inexact |
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283 | #define FLAG_IVF 0x100 // Result is invalid |
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284 | #define FLAG_INF 0x200 // Result is infinite |
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285 | #define FLAG_DZF 0x400 // Division by zero |
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286 | |
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287 | // Position of flag in "rename register SR" (NOT IN "SR") |
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288 | #define FLAG_POS_F 0x0 // Conditionnal branch flag |
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289 | #define FLAG_POS_CY 0x1 // Carry was produced by last arithmétic operation |
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290 | #define FLAG_POS_OV 0x0 // Overflow occured during last arithmetic operation |
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291 | |
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292 | //---------------------------------------------------- |
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293 | // Instruction type |
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294 | //---------------------------------------------------- |
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295 | |
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296 | #define M_CPU_LOG2_NB_TYPE 4 |
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297 | |
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298 | #define TYPE_NOP 0x0 |
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299 | #define TYPE_ALU_F 0x1 // Instruction ALU with flag using (ADD, SUB, ADDC ...) |
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300 | #define TYPE_ALU_NF 0x2 // Instruction ALU without flag using (AND, OR ...) |
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301 | #define TYPE_MAC 0x3 // Instruction ALU with utilisation of register HI/LO |
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302 | #define TYPE_J 0x4 // Branch instruction |
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303 | #define TYPE_SPR_READ 0x5 // Instruction special : l.mfspr |
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304 | #define TYPE_SPR_WRITE 0x6 // Instruction special : l.mtspr |
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305 | #define TYPE_SPECIAL 0x7 // Instruction execute in decode stage |
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306 | #define TYPE_CUSTOM 0x8 // Instruction Custom |
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307 | |
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308 | #define TYPE_LOAD_Z 0x9 // Load access (extended by zero) |
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309 | #define TYPE_LOAD_S 0xa // Load access (sign extended) |
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310 | #define TYPE_STORE 0xc // Store access |
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311 | |
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312 | //---------------------------------------------------- |
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313 | // Condition to branch |
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314 | //---------------------------------------------------- |
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315 | |
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316 | #define M_CPU_LOG2_NB_COND 4 |
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317 | |
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318 | #define COND_NONE 0x0 // None condition (jump) |
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319 | #define COND_F 0x2 // Branch if Flag is set |
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320 | #define COND_NF 0x3 // Branch if Flag is clear |
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321 | #define COND_REG 0x4 // Branch if a register is read |
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322 | #define COND_STACK 0x8 // Branch with pop in stack pointer |
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323 | |
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324 | //---------------------------------------------------- |
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325 | // Event : State and Type |
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326 | //---------------------------------------------------- |
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327 | |
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328 | #define EVENT_STATE_NO_EVENT 0 // no event : current case |
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329 | #define EVENT_STATE_EVENT 1 // Have a event : make necessary to manage the event |
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330 | #define EVENT_STATE_WAITEND 2 // Wait end of manage event (restaure a good context) |
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331 | #define EVENT_STATE_END 3 // CPU can continue |
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332 | |
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333 | #define EVENT_TYPE_MISS 0 // miss of speculation |
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334 | #define EVENT_TYPE_EXCP 1 // exception or interruption occure |
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335 | |
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336 | // SPEC? TAKE? |
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337 | #define BRANCH_STATE_NONE 0 // 0 0 |
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338 | #define BRANCH_STATE_NSPEC_TAKE 1 // 0 1 -> incondionnal |
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339 | #define BRANCH_STATE_SPEC_NTAKE 2 // 1 0 |
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340 | #define BRANCH_STATE_SPEC_TAKE 3 // 1 1 |
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341 | |
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342 | //---------------------------------------------------- |
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343 | // Name to particular register |
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344 | //---------------------------------------------------- |
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345 | |
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346 | //~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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347 | // GENERAL PURPOSE REGISTER |
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348 | //~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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349 | #define M_CPU_LOG2_NB_GPR_LOG 5 |
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350 | #define M_CPU_NB_GPR_LOG (1<<M_CPU_LOG2_NB_GPR_LOG) |
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351 | |
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352 | #define GPR_LOG_LR 0x09 // Link register |
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353 | #define REG_PHY_SR 0x00 // Status register |
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354 | |
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355 | //~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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356 | // SPECIAL PURPOSE REGISTER |
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357 | //~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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358 | #define M_CPU_LOG2_NB_SPR_LOG 1 |
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359 | #define M_CPU_NB_SPR_LOG (1<<M_CPU_LOG2_NB_SPR_LOG) |
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360 | #define M_CPU_SPR_SIZE_DATA 2 // Size of the most great register |
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361 | |
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362 | #define SPR_LOG_SR_F 0x00 // Status register bit F (size = 1) |
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363 | #define SPR_LOG_SR_CY_OV 0x01 // Status register bit overflow and carry (size = 2) |
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364 | //#define SPR_LOG_SR_LO 0x02 // MAC LSB (size = 32) |
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365 | //#define SPR_LOG_SR_HI 0x03 // MAC MSB (size = 32) |
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366 | */ |
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367 | |
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368 | /* |
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369 | //---------------------------------------------------- |
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370 | // Code Operation (before decode) |
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371 | //---------------------------------------------------- |
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372 | |
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373 | // Codop - [31:26] Instructions with immediat |
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374 | #define OPCOD_L_J 0x00 // 000_000 |
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375 | #define OPCOD_L_JAL 0x01 // 000_001 |
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376 | #define OPCOD_L_BNF 0x03 // 000_011 |
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377 | #define OPCOD_L_BF 0x04 // 000_100 |
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378 | #define OPCOD_L_RFE 0x09 // 001_001 |
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379 | #define OPCOD_L_JR 0x11 // 010_001 |
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380 | #define OPCOD_L_JALR 0x12 // 010_010 |
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381 | #define OPCOD_L_MACI 0x13 // 010_011 |
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382 | #define OPCOD_L_CUST1 0x1c // 011_100 |
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383 | #define OPCOD_L_CUST2 0x1d // 011_101 |
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384 | #define OPCOD_L_CUST3 0x1e // 011_110 |
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385 | #define OPCOD_L_CUST4 0x1f // 011_111 |
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386 | #define OPCOD_L_CUST5 0x3c // 111_100 |
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387 | #define OPCOD_L_CUST6 0x3d // 111_101 |
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388 | #define OPCOD_L_CUST7 0x3e // 111_110 |
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389 | #define OPCOD_L_CUST8 0x3f // 111_111 |
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390 | #define OPCOD_L_LD 0x20 // 100_000 |
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391 | #define OPCOD_L_LWZ 0x21 // 100_001 |
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392 | #define OPCOD_L_LWS 0x22 // 100_010 |
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393 | #define OPCOD_L_LBZ 0x23 // 100_011 |
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394 | #define OPCOD_L_LBS 0x24 // 100_100 |
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395 | #define OPCOD_L_LHZ 0x25 // 100_101 |
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396 | #define OPCOD_L_LHS 0x26 // 100_110 |
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397 | #define OPCOD_L_ADDI 0x27 // 100_111 |
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398 | #define OPCOD_L_ADDIC 0x28 // 101_000 |
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399 | #define OPCOD_L_ANDI 0x29 // 101_001 |
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400 | #define OPCOD_L_ORI 0x2a // 101_010 |
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401 | #define OPCOD_L_XORI 0x2b // 101_011 |
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402 | #define OPCOD_L_MULI 0x2c // 101_100 |
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403 | #define OPCOD_L_MFSPR 0x2d // 101_101 |
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404 | #define OPCOD_L_MTSPR 0x30 // 110_000 |
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405 | #define OPCOD_L_SD 0x32 // 110_010 |
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406 | #define OPCOD_L_SW 0x35 // 110_101 |
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407 | #define OPCOD_L_SB 0x36 // 110_110 |
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408 | #define OPCOD_L_SH 0x37 // 110_111 |
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409 | |
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410 | #define OPCOD_INST_LV 0x0a // 001_010 // Instruction ORVDX64 |
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411 | #define OPCOD_INST_LF 0x33 // 110_011 // Instruction ORFPX32/64 |
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412 | |
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413 | #define OPCOD_SPECIAL 0x38 // 111_000 // Instructions Register-Register |
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414 | #define OPCOD_SPECIAL_1 0x39 // 111_001 // Instructions "set flag" with register |
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415 | #define OPCOD_SPECIAL_2 0x2f // 101_111 // Instructions "set flag" with immediat |
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416 | #define OPCOD_SPECIAL_6 0x2e // 101_110 // Instruction Shift/Rotate with immediat |
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417 | #define OPCOD_SPECIAL_7 0x31 // 110_001 // Instructions multiply with HI-LO |
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418 | #define OPCOD_SPECIAL_8 0x06 // 000_110 // Instructions acces at HI-LO |
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419 | |
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420 | // OPCOD_SPECIAL instructions - [9:8] [3:0] Instructions Register-Register |
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421 | #define OPCOD_L_ADD 0x00 // 00_0000 |
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422 | #define OPCOD_L_ADDC 0x01 // 00_0001 |
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423 | #define OPCOD_L_SUB 0x02 // 00_0010 |
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424 | #define OPCOD_L_AND 0x03 // 00_0011 |
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425 | #define OPCOD_L_OR 0x04 // 00_0100 |
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426 | #define OPCOD_L_XOR 0x05 // 00_0101 |
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427 | #define OPCOD_L_CMOV 0x0e // 00_1110 |
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428 | #define OPCOD_L_FF1 0x0f // 00_1111 |
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429 | #define OPCOD_L_FL1 0x1f // 01_1111 |
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430 | #define OPCOD_L_MUL 0x36 // 11_0110 |
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431 | #define OPCOD_L_DIV 0x39 // 11_1001 |
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432 | #define OPCOD_L_DIVU 0x3a // 11_1010 |
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433 | #define OPCOD_L_MULU 0x3b // 11_1011 |
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434 | |
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435 | #define OPCOD_SPECIAL_3 0xc // 1100 // Instructions extend |
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436 | #define OPCOD_SPECIAL_4 0xd // 1101 // Instructions extend (64b) |
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437 | #define OPCOD_SPECIAL_5 0x8 // 1000 // Instruction Shift/Rotate with register |
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438 | |
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439 | // OPCOD_SPECIAL_1 instructions - [25:21] Instructions "set flag" with register |
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440 | #define OPCOD_L_SFEQ 0x00 // 00000 |
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441 | #define OPCOD_L_SFNE 0x01 // 00001 |
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442 | #define OPCOD_L_SFGTU 0x02 // 00010 |
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443 | #define OPCOD_L_SFGEU 0x03 // 00011 |
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444 | #define OPCOD_L_SFLTU 0x04 // 00100 |
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445 | #define OPCOD_L_SFLEU 0x05 // 00101 |
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446 | #define OPCOD_L_SFGTS 0x0a // 01010 |
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447 | #define OPCOD_L_SFGES 0x0b // 01011 |
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448 | #define OPCOD_L_SFLTS 0x0c // 01100 |
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449 | #define OPCOD_L_SFLES 0x0d // 01101 |
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450 | |
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451 | // OPCOD_SPECIAL_2 instructions - [25:21] Instructions "set flag" with immediat |
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452 | #define OPCOD_L_SFEQI 0x00 // 00000 |
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453 | #define OPCOD_L_SFNEI 0x01 // 00001 |
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454 | #define OPCOD_L_SFGTUI 0x02 // 00010 |
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455 | #define OPCOD_L_SFGEUI 0x03 // 00011 |
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456 | #define OPCOD_L_SFLTUI 0x04 // 00100 |
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457 | #define OPCOD_L_SFLEUI 0x05 // 00101 |
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458 | #define OPCOD_L_SFGTSI 0x0a // 01010 |
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459 | #define OPCOD_L_SFGESI 0x0b // 01011 |
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460 | #define OPCOD_L_SFLTSI 0x0c // 01100 |
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461 | #define OPCOD_L_SFLESI 0x0d // 01101 |
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462 | |
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463 | // OPCOD_SPECIAL_3 instructions - [9:6] Instructions extend |
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464 | #define OPCOD_L_EXTHS 0x0 // 0000 |
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465 | #define OPCOD_L_EXTHZ 0x2 // 0010 |
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466 | #define OPCOD_L_EXTBS 0x1 // 0001 |
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467 | #define OPCOD_L_EXTBZ 0x3 // 0011 |
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468 | |
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469 | // OPCOD_SPECIAL_4 instructions - [9:6] Instructions extend (64b) |
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470 | #define OPCOD_L_EXTWS 0x0 // 0000 |
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471 | #define OPCOD_L_EXTWZ 0x1 // 0001 |
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472 | |
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473 | // OPCOD_SPECIAL_5 instructions - [7:6] Instruction Shift/Rotate with register |
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474 | #define OPCOD_L_SLL 0x0 // 00 |
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475 | #define OPCOD_L_SRL 0x1 // 01 |
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476 | #define OPCOD_L_SRA 0x2 // 10 |
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477 | #define OPCOD_L_ROR 0x3 // 11 |
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478 | |
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479 | // OPCOD_SPECIAL_6 instructions - [7:6] Instruction Shift/Rotate with immediat |
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480 | #define OPCOD_L_SLLI 0x0 // 00 |
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481 | #define OPCOD_L_SRLI 0x1 // 01 |
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482 | #define OPCOD_L_SRAI 0x2 // 10 |
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483 | #define OPCOD_L_RORI 0x3 // 11 |
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484 | |
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485 | // OPCOD_SPECIAL_7 instructions - [3:0] Instructions multiply with HI-LO |
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486 | #define OPCOD_L_MAC 0x1 // 0001 |
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487 | #define OPCOD_L_MSB 0x2 // 0010 |
---|
488 | |
---|
489 | // OPCOD_SPECIAL_8 instructions - [17] Instructions acces at HI-LO |
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490 | #define OPCOD_L_MOVHI 0x0 // 0 |
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491 | #define OPCOD_L_MACRC 0x1 // 1 |
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492 | |
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493 | // Particular case Instructions systems |
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494 | #define OPCOD_L_MSYNC 0x22000000 |
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495 | #define OPCOD_L_CSYNC 0x23000000 |
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496 | #define OPCOD_L_PSYNC 0x22800000 |
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497 | #define OPCOD_L_NOP 0x1500 |
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498 | #define OPCOD_L_SYS 0x2000 |
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499 | #define OPCOD_L_TRAP 0x2100 |
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500 | |
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501 | //---------------------------------------------------- |
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502 | // Code Operation (after decode) |
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503 | //---------------------------------------------------- |
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504 | |
---|
505 | typedef enum |
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506 | { |
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507 | // ##### WARNING : This opcode must be the first##### |
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508 | INST_L_NO_IMPLEMENTED , // Operation is not implemented |
---|
509 | |
---|
510 | INST_L_ADD , // L.ADD , L.ADDI , L.ADDC , L.ADDIC |
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511 | INST_L_AND , // L.AND , L.ANDI |
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512 | INST_L_OR , // L.OR , L.ORI |
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513 | INST_L_XOR , // L.XOR , L.XORI |
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514 | INST_L_CMOV , // L.CMOV |
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515 | INST_L_SUB , // L.SUB |
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516 | INST_L_FF1 , // L.FF1 |
---|
517 | INST_L_EXTBS , // L.EXTBS |
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518 | INST_L_EXTBZ , // L.EXTBZ |
---|
519 | INST_L_EXTHS , // L.EXTHS |
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520 | INST_L_EXTHZ , // L.EXTHZ |
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521 | INST_L_EXTWS , // L.EXTWS |
---|
522 | INST_L_EXTWZ , // L.EXTWZ |
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523 | INST_L_e , // |
---|
524 | INST_L_f , // |
---|
525 | INST_L_MUL , // L.MUL , L.MULI |
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526 | INST_L_MULU , // L.MULU |
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527 | INST_L_DIV , // L.DIV |
---|
528 | INST_L_DIVU , // L.DIVU |
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529 | INST_L_SLL , // L.SLL , L.SLLI |
---|
530 | INST_L_SRL , // L.SRL , L.SRLI |
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531 | INST_L_SRA , // L.SRA , L.SRAI |
---|
532 | INST_L_ROR , // L.ROR , L.RORI |
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533 | INST_L_SFGES , // L.SFGES , L.SFGESI |
---|
534 | INST_L_SFGEU , // L.SFGEU , L.SFGEUI |
---|
535 | INST_L_SFGTS , // L.SFGTS , L.SFGTSI |
---|
536 | INST_L_SFGTU , // L.SFGTU , L.SFGTUI |
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537 | INST_L_SFLES , // L.SFLES , L.SFLESI |
---|
538 | INST_L_SFLEU , // L.SFLEU , L.SFLEUI |
---|
539 | INST_L_SFLTS , // L.SFLTS , L.SFLTSI |
---|
540 | INST_L_SFLTU , // L.SFLTU , L.SFLTUI |
---|
541 | INST_L_SFEQ , // L.SFEQ , L.SFEQI |
---|
542 | INST_L_SFNE , // L.SFNE , L.SFNEI |
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543 | INST_L_READ , // L.BNF , L.BF , L.JR |
---|
544 | INST_L_MOVHI , // L.MOVI |
---|
545 | INST_L_CSYNC , // L.CSYNC |
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546 | INST_L_MSYNC , // L.MSYNC |
---|
547 | INST_L_PSYNC , // L.PSYNC |
---|
548 | INST_L_RFE , // L.RFE |
---|
549 | INST_L_MAC , // L.MAC , L.MACI |
---|
550 | INST_L_MSB , // L.MSB |
---|
551 | INST_L_MACRC , // L.MACRC |
---|
552 | INST_L_2b , // |
---|
553 | INST_L_MEMB , // L.LBS , L.LBZ , L.SB |
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554 | INST_L_MEMH , // L.LHS , L.LHZ , L.SH |
---|
555 | INST_L_MEMW , // L.LWS , L.LWZ , L.SW |
---|
556 | INST_L_MEMD , // L.LD , L.SD |
---|
557 | INST_L_CUST1 , // L.CUST1 |
---|
558 | INST_L_CUST2 , // L.CUST2 |
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559 | INST_L_CUST3 , // L.CUST3 |
---|
560 | INST_L_CUST4 , // L.CUST4 |
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561 | INST_L_CUST5 , // L.CUST5 |
---|
562 | INST_L_CUST6 , // L.CUST6 |
---|
563 | INST_L_CUST7 , // L.CUST7 |
---|
564 | INST_L_CUST8 , // L.CUST8 |
---|
565 | INST_L_38 , // |
---|
566 | INST_L_39 , // |
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567 | INST_L_3a , // |
---|
568 | INST_L_3b , // |
---|
569 | INST_L_3c , // |
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570 | INST_L_3d , // |
---|
571 | INST_L_3e , // |
---|
572 | INST_NOP // L.NOP |
---|
573 | } opcod_t; |
---|
574 | |
---|
575 | #define LOG2_NB_INST_L 6 |
---|
576 | #define NB_INST_L 64 // +1 -> INST_L_NO_IMPLEMENTED |
---|
577 | //#define NB_INST_L (INST_L_NO_IMPLEMENTED+1) |
---|
578 | */ |
---|
579 | |
---|
580 | }; // end namespace behavioural |
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581 | }; // end namespace morpheo |
---|
582 | |
---|
583 | #endif |
---|