[42] | 1 | #ifdef VHDL |
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| 2 | /* |
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| 3 | * $Id: Component_vhdl_instance.cpp 113 2009-04-14 18:39:12Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/include/Component.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | |
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[43] | 14 | #undef FUNCTION |
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| 15 | #define FUNCTION "Component::vhdl_instance" |
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[42] | 16 | void Component::vhdl_instance (Vhdl * & vhdl) |
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| 17 | { |
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[43] | 18 | log_printf(FUNC,Behavioural,FUNCTION,"Begin"); |
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| 19 | |
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[42] | 20 | uint32_t cpt = 0; |
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[75] | 21 | std::map<Signal *,std::string> tab; |
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[42] | 22 | |
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[44] | 23 | // buffer all output |
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[58] | 24 | |
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[44] | 25 | { |
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| 26 | // for each interface |
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[75] | 27 | std::list<Interface_fifo *> * list_interface = (_entity)->get_interfaces_list()->get_interface_list(); |
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| 28 | std::list<Interface_fifo *>::iterator j = list_interface->begin(); |
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[95] | 29 | bool print_comment = false; |
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[44] | 30 | if (not list_interface->empty()) |
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| 31 | { |
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| 32 | while (j != list_interface->end()) |
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| 33 | { |
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| 34 | // for each signal |
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[75] | 35 | std::list<Signal *> * list_signal = (*j)->get_signal_list(); |
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| 36 | std::list<Signal *>::iterator k = list_signal->begin(); |
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[44] | 37 | if (not list_signal->empty()) |
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| 38 | { |
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| 39 | while (k != list_signal->end()) |
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| 40 | { |
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| 41 | Signal * signal = (*k); |
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| 42 | |
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| 43 | // test if is connect with external interface or with an another component AND if this port is mapped. |
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| 44 | if ( (signal->get_direction() == OUT) and |
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| 45 | (signal->get_connect_from_signal () != NULL) ) |
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| 46 | { |
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[95] | 47 | if (not print_comment) |
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| 48 | { |
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| 49 | vhdl->set_body ("------------------------------------------------------"); |
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| 50 | vhdl->set_body ("-- Output's Buffer"); |
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| 51 | vhdl->set_body ("------------------------------------------------------"); |
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| 52 | |
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| 53 | print_comment = true; |
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| 54 | } |
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| 55 | |
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[44] | 56 | // Create name |
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[75] | 57 | std::string signal_name = "signal_"+toString(cpt++); |
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[44] | 58 | |
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| 59 | tab [signal ] = signal_name; |
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| 60 | tab [signal->get_connect_from_signal()] = signal_name; |
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| 61 | |
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| 62 | // Add a new signal and the affectation |
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| 63 | vhdl->set_signal (signal_name, signal->get_size()); |
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| 64 | vhdl->set_body (signal->get_name()+" <= "+signal_name+";"); |
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| 65 | } |
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| 66 | else |
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| 67 | { |
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| 68 | tab [signal ] = signal->get_name(); |
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| 69 | } |
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| 70 | ++k; |
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| 71 | } |
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| 72 | } |
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| 73 | ++j; |
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| 74 | } |
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[95] | 75 | |
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| 76 | if (print_comment) |
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| 77 | { |
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| 78 | vhdl->set_body (""); |
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| 79 | vhdl->set_body ("------------------------------------------------------"); |
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| 80 | vhdl->set_body (""); |
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| 81 | } |
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[44] | 82 | } |
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| 83 | } |
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| 84 | |
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[42] | 85 | vhdl->set_library_work (_entity->get_name() + "_Pack"); |
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| 86 | |
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| 87 | // for each entity |
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[75] | 88 | std::list<Tcomponent_t *> * list_component = _list_component; |
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| 89 | std::list<Tcomponent_t *>::iterator i = list_component->begin(); |
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[42] | 90 | if (not list_component->empty()) |
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| 91 | { |
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| 92 | while (i != list_component->end()) |
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| 93 | { |
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[113] | 94 | Entity * entity = (*i)->_entity; |
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| 95 | Tinstance_t instance = (*i)->_instance; |
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| 96 | std::string architecture = (*i)->_architecture; |
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| 97 | std::string package = "work"; |
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[42] | 98 | |
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[57] | 99 | if (instance & INSTANCE_LIBRARY) |
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| 100 | vhdl->set_library_work (entity->get_name() + "_Pack"); |
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[44] | 101 | |
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[57] | 102 | if (instance & INSTANCE_COMPONENT) |
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| 103 | { |
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[75] | 104 | std::list<std::string> list_port_map; |
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[57] | 105 | |
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| 106 | // for each interface |
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[75] | 107 | std::list<Interface_fifo *> * list_interface = entity->get_interfaces_list()->get_interface_list(); |
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| 108 | std::list<Interface_fifo *>::iterator j = list_interface->begin(); |
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[57] | 109 | if (not list_interface->empty()) |
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| 110 | { |
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| 111 | while (j != list_interface->end()) |
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| 112 | { |
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| 113 | // for each signal |
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[75] | 114 | std::list<Signal *> * list_signal = (*j)->get_signal_list(); |
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| 115 | std::list<Signal *>::iterator k = list_signal->begin(); |
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[57] | 116 | if (not list_signal->empty()) |
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| 117 | { |
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| 118 | while (k != list_signal->end()) |
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| 119 | { |
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| 120 | // test if is connect with external interface or with an another component. |
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| 121 | Signal * signal_src = (*k); |
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| 122 | |
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| 123 | if (signal_src->presence_vhdl () == true) |
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| 124 | { |
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| 125 | Signal * signal_dest = signal_src->get_connect_to_signal(); |
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[75] | 126 | std::string name_src = signal_src->get_name(); |
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| 127 | std::string name_dest; |
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[57] | 128 | |
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[44] | 129 | // // Test if destination signal is a interface port ? |
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| 130 | // if (_entity->find_signal(signal_dest) == false) |
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| 131 | // { |
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[57] | 132 | // find if signal is already link |
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[75] | 133 | std::map<Signal *,std::string>::iterator it = tab.find(signal_dest); |
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[57] | 134 | if (tab.find(signal_dest) == tab.end()) |
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| 135 | { |
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| 136 | // Create name |
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| 137 | name_dest = "signal_"+toString(cpt++); |
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| 138 | |
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| 139 | tab [signal_src ] = name_dest; |
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| 140 | tab [signal_dest] = name_dest; |
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| 141 | |
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| 142 | // Add a new signal |
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| 143 | vhdl->set_signal (name_dest, signal_src->get_size()); |
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| 144 | } |
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| 145 | else |
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| 146 | { |
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| 147 | // find !!!! |
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| 148 | name_dest = (*it).second; |
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| 149 | tab [signal_src ] = name_dest; |
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| 150 | } |
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[44] | 151 | // } |
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| 152 | // else |
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| 153 | // { |
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| 154 | // // Test if output |
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| 155 | // if (signal_dest->get_direction() == OUT) |
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| 156 | // { |
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| 157 | // // Take buffer's signal |
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[75] | 158 | // map<Signal *,std::string>::iterator it = tab.find(signal_dest); |
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[44] | 159 | // name_dest = (*it).second; |
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| 160 | |
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| 161 | // cout << " * OUT - name : " << name_dest << endl; |
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| 162 | // } |
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| 163 | // else |
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| 164 | // { |
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| 165 | // name_dest = signal_dest->get_name(); |
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| 166 | // cout << " * IN - name : " << name_dest << endl; |
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| 167 | // } |
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| 168 | // } |
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[65] | 169 | |
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| 170 | vhdl->set_body_component_port_map (list_port_map, |
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| 171 | name_src , signal_src ->get_size(), |
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| 172 | name_dest, signal_dest->get_size() ); |
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[57] | 173 | } |
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| 174 | ++k; |
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| 175 | } |
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| 176 | } |
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| 177 | ++j; |
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| 178 | } |
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| 179 | } |
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[113] | 180 | vhdl->set_body_component ("instance_"+entity->get_name(), |
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| 181 | entity->get_name(), |
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| 182 | architecture, |
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| 183 | package, |
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| 184 | list_port_map); |
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[57] | 185 | |
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| 186 | } |
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[42] | 187 | ++i; |
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| 188 | } |
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| 189 | } |
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[43] | 190 | log_printf(FUNC,Behavioural,FUNCTION,"End"); |
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[42] | 191 | }; |
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[57] | 192 | |
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[42] | 193 | }; // end namespace behavioural |
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| 194 | }; // end namespace morpheo |
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| 195 | #endif |
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