[42] | 1 | #ifdef VHDL |
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| 2 | /* |
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| 3 | * $Id$ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/include/Component.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | |
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[43] | 14 | #undef FUNCTION |
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| 15 | #define FUNCTION "Component::vhdl_instance" |
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[42] | 16 | void Component::vhdl_instance (Vhdl * & vhdl) |
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| 17 | { |
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[43] | 18 | log_printf(FUNC,Behavioural,FUNCTION,"Begin"); |
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| 19 | |
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[42] | 20 | uint32_t cpt = 0; |
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| 21 | map<Signal *,string> tab; |
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| 22 | |
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[44] | 23 | // buffer all output |
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| 24 | { |
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| 25 | vhdl->set_body ("------------------------------------------------------"); |
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| 26 | vhdl->set_body ("-- Output's Buffer"); |
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| 27 | vhdl->set_body ("------------------------------------------------------"); |
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| 28 | |
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| 29 | // for each interface |
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| 30 | list<Interface_fifo *> * list_interface = (_entity)->get_interfaces_list()->get_interface_list(); |
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| 31 | list<Interface_fifo *>::iterator j = list_interface->begin(); |
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| 32 | if (not list_interface->empty()) |
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| 33 | { |
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| 34 | while (j != list_interface->end()) |
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| 35 | { |
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| 36 | // for each signal |
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| 37 | list<Signal *> * list_signal = (*j)->get_signal_list(); |
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| 38 | list<Signal *>::iterator k = list_signal->begin(); |
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| 39 | if (not list_signal->empty()) |
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| 40 | { |
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| 41 | while (k != list_signal->end()) |
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| 42 | { |
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| 43 | Signal * signal = (*k); |
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| 44 | |
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| 45 | // test if is connect with external interface or with an another component AND if this port is mapped. |
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| 46 | if ( (signal->get_direction() == OUT) and |
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| 47 | (signal->get_connect_from_signal () != NULL) ) |
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| 48 | { |
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| 49 | // Create name |
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| 50 | string signal_name = "signal_"+toString(cpt++); |
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| 51 | |
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| 52 | tab [signal ] = signal_name; |
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| 53 | tab [signal->get_connect_from_signal()] = signal_name; |
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| 54 | |
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| 55 | // Add a new signal and the affectation |
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| 56 | vhdl->set_signal (signal_name, signal->get_size()); |
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| 57 | vhdl->set_body (signal->get_name()+" <= "+signal_name+";"); |
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| 58 | } |
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| 59 | else |
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| 60 | { |
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| 61 | tab [signal ] = signal->get_name(); |
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| 62 | } |
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| 63 | ++k; |
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| 64 | } |
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| 65 | } |
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| 66 | ++j; |
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| 67 | } |
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| 68 | } |
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| 69 | vhdl->set_body (""); |
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| 70 | vhdl->set_body ("------------------------------------------------------"); |
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| 71 | vhdl->set_body (""); |
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| 72 | } |
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| 73 | |
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[42] | 74 | vhdl->set_library_work (_entity->get_name() + "_Pack"); |
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| 75 | |
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| 76 | // for each entity |
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| 77 | list<Entity *> * list_component = _list_component; |
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| 78 | list<Entity *>::iterator i = list_component->begin(); |
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| 79 | if (not list_component->empty()) |
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| 80 | { |
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| 81 | while (i != list_component->end()) |
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| 82 | { |
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| 83 | vhdl->set_library_work ((*i)->get_name() + "_Pack"); |
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| 84 | |
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| 85 | list<string> list_port_map; |
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| 86 | |
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| 87 | // for each interface |
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| 88 | list<Interface_fifo *> * list_interface = (*i)->get_interfaces_list()->get_interface_list(); |
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| 89 | list<Interface_fifo *>::iterator j = list_interface->begin(); |
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| 90 | if (not list_interface->empty()) |
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| 91 | { |
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| 92 | while (j != list_interface->end()) |
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| 93 | { |
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| 94 | // for each signal |
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| 95 | list<Signal *> * list_signal = (*j)->get_signal_list(); |
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| 96 | list<Signal *>::iterator k = list_signal->begin(); |
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| 97 | if (not list_signal->empty()) |
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| 98 | { |
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| 99 | while (k != list_signal->end()) |
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| 100 | { |
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| 101 | // test if is connect with external interface or with an another component. |
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| 102 | Signal * signal_src = (*k); |
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[44] | 103 | |
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[42] | 104 | if (signal_src->presence_vhdl () == true) |
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| 105 | { |
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[44] | 106 | Signal * signal_dest = signal_src->get_connect_to_signal(); |
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[42] | 107 | string name_src = signal_src->get_name(); |
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| 108 | string name_dest; |
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| 109 | |
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[44] | 110 | // // Test if destination signal is a interface port ? |
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| 111 | // if (_entity->find_signal(signal_dest) == false) |
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| 112 | // { |
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[42] | 113 | // find if signal is already link |
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[44] | 114 | map<Signal *,string>::iterator it = tab.find(signal_dest); |
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| 115 | if (tab.find(signal_dest) == tab.end()) |
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[42] | 116 | { |
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| 117 | // Create name |
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| 118 | name_dest = "signal_"+toString(cpt++); |
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| 119 | |
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| 120 | tab [signal_src ] = name_dest; |
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| 121 | tab [signal_dest] = name_dest; |
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| 122 | |
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| 123 | // Add a new signal |
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| 124 | vhdl->set_signal (name_dest, signal_src->get_size()); |
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| 125 | } |
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| 126 | else |
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[44] | 127 | { |
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| 128 | // find !!!! |
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| 129 | name_dest = (*it).second; |
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| 130 | tab [signal_src ] = name_dest; |
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| 131 | } |
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| 132 | // } |
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| 133 | // else |
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| 134 | // { |
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| 135 | // cout << "Kane à dit : " << signal_dest->get_name() << endl; |
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| 136 | // // Test if output |
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| 137 | // if (signal_dest->get_direction() == OUT) |
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| 138 | // { |
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| 139 | // // Take buffer's signal |
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| 140 | // map<Signal *,string>::iterator it = tab.find(signal_dest); |
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| 141 | // name_dest = (*it).second; |
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| 142 | |
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| 143 | // cout << " * OUT - name : " << name_dest << endl; |
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| 144 | // } |
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| 145 | // else |
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| 146 | // { |
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| 147 | // name_dest = signal_dest->get_name(); |
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| 148 | // cout << " * IN - name : " << name_dest << endl; |
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| 149 | // } |
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| 150 | // } |
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[42] | 151 | |
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| 152 | vhdl->set_body_component_port_map (list_port_map, name_src, name_dest); |
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| 153 | } |
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| 154 | ++k; |
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| 155 | } |
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| 156 | } |
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| 157 | ++j; |
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| 158 | } |
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| 159 | } |
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| 160 | vhdl->set_body_component ("instance_"+(*i)->get_name(),(*i)->get_name(),list_port_map); |
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| 161 | ++i; |
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| 162 | } |
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| 163 | } |
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[43] | 164 | log_printf(FUNC,Behavioural,FUNCTION,"End"); |
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[42] | 165 | }; |
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| 166 | |
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| 167 | }; // end namespace behavioural |
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| 168 | }; // end namespace morpheo |
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| 169 | #endif |
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