[42] | 1 | #ifdef VHDL |
---|
| 2 | /* |
---|
| 3 | * $Id$ |
---|
| 4 | * |
---|
| 5 | * [ Description ] |
---|
| 6 | * |
---|
| 7 | */ |
---|
| 8 | |
---|
| 9 | #include "Behavioural/include/Component.h" |
---|
| 10 | |
---|
| 11 | namespace morpheo { |
---|
| 12 | namespace behavioural { |
---|
| 13 | |
---|
[43] | 14 | #undef FUNCTION |
---|
| 15 | #define FUNCTION "Component::vhdl_instance" |
---|
[42] | 16 | void Component::vhdl_instance (Vhdl * & vhdl) |
---|
| 17 | { |
---|
[43] | 18 | log_printf(FUNC,Behavioural,FUNCTION,"Begin"); |
---|
| 19 | |
---|
[42] | 20 | uint32_t cpt = 0; |
---|
| 21 | map<Signal *,string> tab; |
---|
| 22 | |
---|
[44] | 23 | // buffer all output |
---|
[58] | 24 | |
---|
[44] | 25 | { |
---|
| 26 | // for each interface |
---|
| 27 | list<Interface_fifo *> * list_interface = (_entity)->get_interfaces_list()->get_interface_list(); |
---|
| 28 | list<Interface_fifo *>::iterator j = list_interface->begin(); |
---|
| 29 | if (not list_interface->empty()) |
---|
| 30 | { |
---|
[58] | 31 | vhdl->set_body ("------------------------------------------------------"); |
---|
| 32 | vhdl->set_body ("-- Output's Buffer"); |
---|
| 33 | vhdl->set_body ("------------------------------------------------------"); |
---|
| 34 | |
---|
[44] | 35 | while (j != list_interface->end()) |
---|
| 36 | { |
---|
| 37 | // for each signal |
---|
| 38 | list<Signal *> * list_signal = (*j)->get_signal_list(); |
---|
| 39 | list<Signal *>::iterator k = list_signal->begin(); |
---|
| 40 | if (not list_signal->empty()) |
---|
| 41 | { |
---|
| 42 | while (k != list_signal->end()) |
---|
| 43 | { |
---|
| 44 | Signal * signal = (*k); |
---|
| 45 | |
---|
| 46 | // test if is connect with external interface or with an another component AND if this port is mapped. |
---|
| 47 | if ( (signal->get_direction() == OUT) and |
---|
| 48 | (signal->get_connect_from_signal () != NULL) ) |
---|
| 49 | { |
---|
| 50 | // Create name |
---|
| 51 | string signal_name = "signal_"+toString(cpt++); |
---|
| 52 | |
---|
| 53 | tab [signal ] = signal_name; |
---|
| 54 | tab [signal->get_connect_from_signal()] = signal_name; |
---|
| 55 | |
---|
| 56 | // Add a new signal and the affectation |
---|
| 57 | vhdl->set_signal (signal_name, signal->get_size()); |
---|
| 58 | vhdl->set_body (signal->get_name()+" <= "+signal_name+";"); |
---|
| 59 | } |
---|
| 60 | else |
---|
| 61 | { |
---|
| 62 | tab [signal ] = signal->get_name(); |
---|
| 63 | } |
---|
| 64 | ++k; |
---|
| 65 | } |
---|
| 66 | } |
---|
| 67 | ++j; |
---|
| 68 | } |
---|
[58] | 69 | vhdl->set_body (""); |
---|
| 70 | vhdl->set_body ("------------------------------------------------------"); |
---|
| 71 | vhdl->set_body (""); |
---|
[44] | 72 | } |
---|
| 73 | } |
---|
| 74 | |
---|
[42] | 75 | vhdl->set_library_work (_entity->get_name() + "_Pack"); |
---|
| 76 | |
---|
| 77 | // for each entity |
---|
[57] | 78 | list<Tcomponent_t *> * list_component = _list_component; |
---|
| 79 | list<Tcomponent_t *>::iterator i = list_component->begin(); |
---|
[42] | 80 | if (not list_component->empty()) |
---|
| 81 | { |
---|
| 82 | while (i != list_component->end()) |
---|
| 83 | { |
---|
[57] | 84 | Entity * entity = (*i)->_entity; |
---|
| 85 | Tinstance_t instance = (*i)->_instance; |
---|
[42] | 86 | |
---|
[57] | 87 | if (instance & INSTANCE_LIBRARY) |
---|
| 88 | vhdl->set_library_work (entity->get_name() + "_Pack"); |
---|
[44] | 89 | |
---|
[57] | 90 | if (instance & INSTANCE_COMPONENT) |
---|
| 91 | { |
---|
| 92 | list<string> list_port_map; |
---|
| 93 | |
---|
| 94 | // for each interface |
---|
| 95 | list<Interface_fifo *> * list_interface = entity->get_interfaces_list()->get_interface_list(); |
---|
| 96 | list<Interface_fifo *>::iterator j = list_interface->begin(); |
---|
| 97 | if (not list_interface->empty()) |
---|
| 98 | { |
---|
| 99 | while (j != list_interface->end()) |
---|
| 100 | { |
---|
| 101 | // for each signal |
---|
| 102 | list<Signal *> * list_signal = (*j)->get_signal_list(); |
---|
| 103 | list<Signal *>::iterator k = list_signal->begin(); |
---|
| 104 | if (not list_signal->empty()) |
---|
| 105 | { |
---|
| 106 | while (k != list_signal->end()) |
---|
| 107 | { |
---|
| 108 | // test if is connect with external interface or with an another component. |
---|
| 109 | Signal * signal_src = (*k); |
---|
| 110 | |
---|
| 111 | if (signal_src->presence_vhdl () == true) |
---|
| 112 | { |
---|
| 113 | Signal * signal_dest = signal_src->get_connect_to_signal(); |
---|
| 114 | string name_src = signal_src->get_name(); |
---|
| 115 | string name_dest; |
---|
| 116 | |
---|
[44] | 117 | // // Test if destination signal is a interface port ? |
---|
| 118 | // if (_entity->find_signal(signal_dest) == false) |
---|
| 119 | // { |
---|
[57] | 120 | // find if signal is already link |
---|
| 121 | map<Signal *,string>::iterator it = tab.find(signal_dest); |
---|
| 122 | if (tab.find(signal_dest) == tab.end()) |
---|
| 123 | { |
---|
| 124 | // Create name |
---|
| 125 | name_dest = "signal_"+toString(cpt++); |
---|
| 126 | |
---|
| 127 | tab [signal_src ] = name_dest; |
---|
| 128 | tab [signal_dest] = name_dest; |
---|
| 129 | |
---|
| 130 | // Add a new signal |
---|
| 131 | vhdl->set_signal (name_dest, signal_src->get_size()); |
---|
| 132 | } |
---|
| 133 | else |
---|
| 134 | { |
---|
| 135 | // find !!!! |
---|
| 136 | name_dest = (*it).second; |
---|
| 137 | tab [signal_src ] = name_dest; |
---|
| 138 | } |
---|
[44] | 139 | // } |
---|
| 140 | // else |
---|
| 141 | // { |
---|
| 142 | // cout << "Kane à dit : " << signal_dest->get_name() << endl; |
---|
| 143 | // // Test if output |
---|
| 144 | // if (signal_dest->get_direction() == OUT) |
---|
| 145 | // { |
---|
| 146 | // // Take buffer's signal |
---|
| 147 | // map<Signal *,string>::iterator it = tab.find(signal_dest); |
---|
| 148 | // name_dest = (*it).second; |
---|
| 149 | |
---|
| 150 | // cout << " * OUT - name : " << name_dest << endl; |
---|
| 151 | // } |
---|
| 152 | // else |
---|
| 153 | // { |
---|
| 154 | // name_dest = signal_dest->get_name(); |
---|
| 155 | // cout << " * IN - name : " << name_dest << endl; |
---|
| 156 | // } |
---|
| 157 | // } |
---|
[42] | 158 | |
---|
[57] | 159 | vhdl->set_body_component_port_map (list_port_map, name_src, name_dest); |
---|
| 160 | } |
---|
| 161 | ++k; |
---|
| 162 | } |
---|
| 163 | } |
---|
| 164 | ++j; |
---|
| 165 | } |
---|
| 166 | } |
---|
| 167 | vhdl->set_body_component ("instance_"+entity->get_name(),entity->get_name(),list_port_map); |
---|
| 168 | |
---|
| 169 | } |
---|
[42] | 170 | ++i; |
---|
| 171 | } |
---|
| 172 | } |
---|
[43] | 173 | log_printf(FUNC,Behavioural,FUNCTION,"End"); |
---|
[42] | 174 | }; |
---|
[57] | 175 | |
---|
[42] | 176 | }; // end namespace behavioural |
---|
| 177 | }; // end namespace morpheo |
---|
| 178 | #endif |
---|