1 | #ifdef VHDL |
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2 | /* |
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3 | * $Id$ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/include/Component.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | |
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14 | #undef FUNCTION |
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15 | #define FUNCTION "Component::vhdl_instance" |
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16 | void Component::vhdl_instance (Vhdl * & vhdl) |
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17 | { |
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18 | log_printf(FUNC,Behavioural,FUNCTION,"Begin"); |
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19 | |
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20 | uint32_t cpt = 0; |
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21 | map<Signal *,string> tab; |
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22 | |
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23 | vhdl->set_library_work (_entity->get_name() + "_Pack"); |
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24 | |
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25 | // for each entity |
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26 | list<Entity *> * list_component = _list_component; |
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27 | list<Entity *>::iterator i = list_component->begin(); |
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28 | if (not list_component->empty()) |
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29 | { |
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30 | while (i != list_component->end()) |
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31 | { |
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32 | vhdl->set_library_work ((*i)->get_name() + "_Pack"); |
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33 | |
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34 | list<string> list_port_map; |
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35 | |
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36 | // for each interface |
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37 | list<Interface_fifo *> * list_interface = (*i)->get_interfaces_list()->get_interface_list(); |
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38 | list<Interface_fifo *>::iterator j = list_interface->begin(); |
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39 | if (not list_interface->empty()) |
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40 | { |
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41 | while (j != list_interface->end()) |
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42 | { |
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43 | // for each signal |
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44 | list<Signal *> * list_signal = (*j)->get_signal_list(); |
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45 | list<Signal *>::iterator k = list_signal->begin(); |
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46 | if (not list_signal->empty()) |
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47 | { |
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48 | while (k != list_signal->end()) |
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49 | { |
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50 | // test if is connect with external interface or with an another component. |
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51 | Signal * signal_src = (*k); |
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52 | if (signal_src->presence_vhdl () == true) |
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53 | { |
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54 | Signal * signal_dest = (*k)->get_signal_link(); |
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55 | string name_src = signal_src->get_name(); |
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56 | string name_dest; |
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57 | |
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58 | if (_entity->find_signal(signal_dest) == false) |
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59 | { |
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60 | // find if signal is already link |
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61 | map<Signal *,string>::iterator it = tab.find(signal_src); |
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62 | if (tab.find(signal_src) == tab.end()) |
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63 | { |
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64 | // Create name |
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65 | name_dest = "signal_"+toString(cpt++); |
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66 | |
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67 | tab [signal_src ] = name_dest; |
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68 | tab [signal_dest] = name_dest; |
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69 | |
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70 | // Add a new signal |
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71 | vhdl->set_signal (name_dest, signal_src->get_size()); |
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72 | } |
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73 | else |
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74 | name_dest = (*it).second; |
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75 | } |
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76 | else |
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77 | name_dest = signal_dest->get_name(); |
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78 | |
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79 | vhdl->set_body_component_port_map (list_port_map, name_src, name_dest); |
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80 | } |
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81 | ++k; |
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82 | } |
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83 | } |
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84 | ++j; |
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85 | } |
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86 | } |
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87 | vhdl->set_body_component ("instance_"+(*i)->get_name(),(*i)->get_name(),list_port_map); |
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88 | ++i; |
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89 | } |
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90 | } |
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91 | log_printf(FUNC,Behavioural,FUNCTION,"End"); |
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92 | }; |
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93 | |
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94 | }; // end namespace behavioural |
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95 | }; // end namespace morpheo |
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96 | #endif |
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