1 | #ifdef VHDL_TESTBENCH |
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2 | |
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3 | /* |
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4 | * $Id$ |
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5 | * |
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6 | * [ Description ] |
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7 | * |
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8 | */ |
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9 | |
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10 | #include "Behavioural/include/Interfaces.h" |
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11 | |
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12 | namespace morpheo { |
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13 | namespace behavioural { |
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14 | |
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15 | void Interfaces::testbench_generate_file (void) |
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16 | { |
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17 | log_printf(FUNC,Behavioural,"generate_file","Begin"); |
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18 | |
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19 | Vhdl * vhdl = new Vhdl(_name+"_Testbench"); |
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20 | string counter = "counter"; |
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21 | Signal * clock = this->get_clock(); |
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22 | Signal * reset = this->get_reset(); |
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23 | string clock_name = clock->get_name(); |
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24 | string reset_name = reset->get_name(); |
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25 | uint32_t cycle = this->get_cycle(); |
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26 | |
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27 | vhdl->set_signal (clock_name, 1, 0); |
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28 | vhdl->set_signal (reset_name, 1, 0); |
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29 | vhdl->set_signal (counter, "natural"); |
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30 | this->set_signal (vhdl); |
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31 | |
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32 | vhdl->set_body(""); |
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33 | vhdl->set_body("------------------------------------------------------"); |
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34 | vhdl->set_body("-- Component - Intanciation"); |
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35 | vhdl->set_body("------------------------------------------------------"); |
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36 | vhdl->set_body(""); |
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37 | |
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38 | list<string> * list_signal = new list<string>; |
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39 | this->get_signal (list_signal); |
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40 | |
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41 | vhdl->set_library_work (_name + "_Pack"); |
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42 | vhdl->set_body("instance_"+_name+" : "+_name); |
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43 | vhdl->set_body("port map ("); |
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44 | |
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45 | list<string>::iterator i = list_signal->begin(); |
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46 | if (i != list_signal->end()) |
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47 | { |
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48 | vhdl->set_body("\t "+*i+"\t=>\t"+*i); |
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49 | ++i; |
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50 | } |
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51 | while (i != list_signal->end()) |
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52 | { |
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53 | vhdl->set_body("\t,"+*i+"\t=>\t"+*i); |
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54 | ++i; |
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55 | } |
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56 | vhdl->set_body(" );"); |
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57 | |
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58 | delete list_signal; |
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59 | |
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60 | string test_name = this->testbench_body(vhdl,counter, reset_name); |
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61 | |
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62 | vhdl->set_body(""); |
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63 | vhdl->set_body("------------------------------------------------------"); |
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64 | vhdl->set_body("-- reset"); |
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65 | vhdl->set_body("------------------------------------------------------"); |
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66 | vhdl->set_body(""); |
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67 | vhdl->set_body("-- if the systemC simulate have multiple reset, we make the last"); |
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68 | vhdl->set_body(reset_name+" <= '1' after 150 ns;"); |
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69 | |
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70 | vhdl->set_body(""); |
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71 | vhdl->set_body("------------------------------------------------------"); |
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72 | vhdl->set_body("-- process clock_name"); |
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73 | vhdl->set_body("------------------------------------------------------"); |
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74 | vhdl->set_body(""); |
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75 | vhdl->set_body(clock_name+" <= not "+clock_name+" after 50 ns;"); |
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76 | vhdl->set_body(""); |
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77 | vhdl->set_body("process ("+clock_name+")"); |
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78 | vhdl->set_body("begin"); |
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79 | vhdl->set_body("\tif ("+clock_name+"'event and "+clock_name+" = '1') then"); |
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80 | vhdl->set_body(""); |
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81 | vhdl->set_body("\t\tif ("+reset_name+" = '0') then"); |
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82 | vhdl->set_body(""); |
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83 | vhdl->set_body("\t\t\t"+counter+" <= "+toString(reset->get_reset_cycle(true))+";"); |
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84 | vhdl->set_body(""); |
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85 | vhdl->set_body("\t\telse"); |
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86 | vhdl->set_body(""); |
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87 | vhdl->set_body("\t\t\t"+counter+" <= "+counter+"+1;"); |
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88 | vhdl->set_body(""); |
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89 | vhdl->set_body("\t\t\tassert not ("+counter+" >= "+toString(cycle)+") report \"Test OK\" severity FAILURE;"); |
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90 | vhdl->set_body("\t\t\tassert not ("+test_name+" = '0') report \"Test KO\" severity FAILURE;"); |
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91 | |
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92 | #ifdef VHDL_TESTBENCH_ASSERT |
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93 | vhdl->set_body("\t\t\t-- Assert ..."); |
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94 | for (uint32_t cpt=0; cpt<=cycle; cpt++) |
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95 | vhdl->set_body("\t\t\tassert not ("+counter+" = "+toString(cpt)+") report \"===== Test number "+toString(cpt)+" =====\" severity NOTE;"); |
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96 | #endif |
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97 | |
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98 | vhdl->set_body(""); |
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99 | vhdl->set_body("\t\tend if;"); |
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100 | vhdl->set_body("\tend if;"); |
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101 | vhdl->set_body("end process;"); |
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102 | |
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103 | |
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104 | vhdl->generate_file(false,true); |
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105 | |
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106 | delete vhdl; |
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107 | |
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108 | log_printf(FUNC,Behavioural,"generate_file","End"); |
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109 | }; |
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110 | |
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111 | }; // end namespace behavioural |
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112 | }; // end namespace morpheo |
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113 | |
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114 | #endif |
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