[72] | 1 | #include "Behavioural/include/SPR_access_mode.h" |
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| 2 | |
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| 3 | namespace morpheo { |
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| 4 | namespace behavioural { |
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| 5 | |
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| 6 | void SPR_access_mode::implement_group (uint32_t num_group, uint32_t nb_reg ) |
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| 7 | { |
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| 8 | if (_spr_generic[num_group] != NULL) |
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| 9 | throw ERRORMORPHEO("SPR_access_mode::implement_group", "implement more once a group."); |
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| 10 | |
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| 11 | _max_register_by_group[num_group] = nb_reg; |
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| 12 | _spr_generic [num_group] = new spr_access_mode_t [nb_reg]; |
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| 13 | } |
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| 14 | |
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| 15 | uint32_t SPR_access_mode::implement_group (uint32_t num_group) |
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| 16 | { |
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| 17 | if (_spr_generic[num_group] != NULL) |
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| 18 | throw ERRORMORPHEO("SPR_access_mode::implement_group", "implement more once a group."); |
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| 19 | |
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| 20 | switch (num_group) |
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| 21 | { |
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| 22 | case GROUP_SYSTEM_AND_CONTROL : |
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| 23 | { |
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| 24 | implement_group(GROUP_SYSTEM_AND_CONTROL ,NB_REG_GROUP_SYSTEM_AND_CONTROL ); |
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| 25 | |
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| 26 | for (uint32_t i=0 ; i<=8 ; i++) |
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| 27 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_ONLY; |
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| 28 | for (uint32_t i=16; i<=18; i++) |
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| 29 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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[88] | 30 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 19]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY; |
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| 31 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 19]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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[72] | 32 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND; |
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| 33 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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[117] | 34 | |
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| 35 | // new register : CID, TID, TSR |
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| 36 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 21]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY; |
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| 37 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 21]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 38 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 22]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY; |
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| 39 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 22]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 40 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 23]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY; |
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| 41 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 23]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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[72] | 42 | |
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[97] | 43 | const uint32_t nb_shadow = 1; // max 16 |
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[72] | 44 | |
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[97] | 45 | for (uint32_t i=32; i<32+nb_shadow; i++) |
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[72] | 46 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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[97] | 47 | for (uint32_t i=48; i<48+nb_shadow; i++) |
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[72] | 48 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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[97] | 49 | for (uint32_t i=64; i<64+nb_shadow; i++) |
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[72] | 50 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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[97] | 51 | // for (uint32_t i=1024; i<1024+32*nb_shadow; i++) |
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| 52 | // _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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[72] | 53 | |
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| 54 | break; |
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| 55 | } |
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| 56 | case GROUP_DMMU : |
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| 57 | { |
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| 58 | implement_group(GROUP_DMMU ,NB_REG_GROUP_DMMU ); |
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| 59 | |
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| 60 | for (uint32_t i=0; i<=2; i++) |
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| 61 | _spr_generic [GROUP_DMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 62 | _spr_generic [GROUP_DMMU ][ 2]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; |
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| 63 | for (uint32_t i=4; i<=11; i++) |
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| 64 | _spr_generic [GROUP_DMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 65 | for (uint32_t i=512; i<=1535; i++) |
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| 66 | _spr_generic [GROUP_DMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 67 | |
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| 68 | break; |
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| 69 | } |
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| 70 | case GROUP_IMMU : |
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| 71 | { |
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| 72 | implement_group(GROUP_IMMU ,NB_REG_GROUP_IMMU ); |
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| 73 | |
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| 74 | for (uint32_t i=0; i<=2; i++) |
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| 75 | _spr_generic [GROUP_IMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 76 | _spr_generic [GROUP_IMMU ][ 2]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; |
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| 77 | for (uint32_t i=4; i<=11; i++) |
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| 78 | _spr_generic [GROUP_IMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 79 | for (uint32_t i=512; i<=1536; i++) |
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| 80 | _spr_generic [GROUP_IMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 81 | |
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| 82 | break; |
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| 83 | } |
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| 84 | case GROUP_DCACHE : |
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| 85 | { |
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| 86 | implement_group(GROUP_DCACHE ,NB_REG_GROUP_DCACHE ); |
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| 87 | |
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| 88 | _spr_generic [GROUP_DCACHE ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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[88] | 89 | for (uint32_t i=1; i<=5; i++) |
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[72] | 90 | { |
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| 91 | _spr_generic [GROUP_DCACHE ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; |
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| 92 | _spr_generic [GROUP_DCACHE ][ i]._user_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; |
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| 93 | } |
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| 94 | _spr_generic [GROUP_DCACHE ][ 3]._user_access_mode = SPR_ACCESS_MODE_NONE; |
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| 95 | |
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| 96 | break; |
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| 97 | } |
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| 98 | case GROUP_ICACHE : |
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| 99 | { |
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| 100 | implement_group(GROUP_ICACHE ,NB_REG_GROUP_ICACHE ); |
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| 101 | |
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| 102 | _spr_generic [GROUP_ICACHE ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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[88] | 103 | for (uint32_t i=1; i<=3; i++) |
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[72] | 104 | { |
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| 105 | _spr_generic [GROUP_ICACHE ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; |
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| 106 | _spr_generic [GROUP_ICACHE ][ i]._user_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; |
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| 107 | } |
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| 108 | _spr_generic [GROUP_ICACHE ][ 2]._user_access_mode = SPR_ACCESS_MODE_NONE; |
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| 109 | |
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| 110 | break; |
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| 111 | } |
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| 112 | case GROUP_MAC : |
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| 113 | { |
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| 114 | implement_group(GROUP_MAC ,NB_REG_GROUP_MAC ); |
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| 115 | |
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| 116 | for (uint32_t i=1; i<=2; i++) |
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| 117 | { |
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| 118 | _spr_generic [GROUP_MAC ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 119 | _spr_generic [GROUP_MAC ][ i]._user_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 120 | } |
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| 121 | |
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| 122 | break; |
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| 123 | } |
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| 124 | case GROUP_DEBUG : |
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| 125 | { |
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| 126 | implement_group(GROUP_DEBUG ,NB_REG_GROUP_DEBUG ); |
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| 127 | |
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| 128 | for (uint32_t i=0; i<=21; i++) |
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| 129 | _spr_generic [GROUP_DEBUG ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 130 | |
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| 131 | break; |
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| 132 | } |
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| 133 | case GROUP_PERFORMANCE_COUNTER : |
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| 134 | { |
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| 135 | implement_group(GROUP_PERFORMANCE_COUNTER ,NB_REG_GROUP_PERFORMANCE_COUNTER ); |
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| 136 | |
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| 137 | for (uint32_t i=0; i<=7; i++) |
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| 138 | { |
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| 139 | _spr_generic [GROUP_PERFORMANCE_COUNTER][ i]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND; |
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| 140 | _spr_generic [GROUP_PERFORMANCE_COUNTER][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 141 | } |
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| 142 | for (uint32_t i=8; i<=15; i++) |
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| 143 | _spr_generic [GROUP_PERFORMANCE_COUNTER][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 144 | |
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| 145 | break; |
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| 146 | } |
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| 147 | case GROUP_POWER_MANAGEMENT : |
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| 148 | { |
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| 149 | implement_group(GROUP_POWER_MANAGEMENT ,NB_REG_GROUP_POWER_MANAGEMENT ); |
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| 150 | |
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| 151 | _spr_generic [GROUP_POWER_MANAGEMENT ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 152 | |
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| 153 | break; |
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| 154 | } |
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| 155 | case GROUP_PIC : |
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| 156 | { |
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| 157 | implement_group(GROUP_PIC ,NB_REG_GROUP_PIC ); |
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| 158 | |
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| 159 | _spr_generic [GROUP_PIC ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 160 | _spr_generic [GROUP_PIC ][ 2]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 161 | |
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| 162 | break; |
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| 163 | } |
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| 164 | case GROUP_TICK_TIMER : |
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| 165 | { |
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| 166 | implement_group(GROUP_TICK_TIMER ,NB_REG_GROUP_TICK_TIMER ); |
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| 167 | |
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| 168 | _spr_generic [GROUP_TICK_TIMER ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 169 | _spr_generic [GROUP_TICK_TIMER ][ 1]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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| 170 | _spr_generic [GROUP_TICK_TIMER ][ 1]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND; |
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| 171 | |
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| 172 | break; |
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| 173 | } |
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| 174 | case GROUP_FLOATING_POINT : |
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| 175 | { |
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| 176 | implement_group(GROUP_FLOATING_POINT ,NB_REG_GROUP_FLOATING_POINT ); |
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| 177 | break; |
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| 178 | } |
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| 179 | case GROUP_RESERVED_1 : |
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| 180 | case GROUP_RESERVED_2 : |
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| 181 | case GROUP_RESERVED_3 : |
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| 182 | case GROUP_RESERVED_4 : |
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| 183 | case GROUP_RESERVED_5 : |
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| 184 | case GROUP_RESERVED_6 : |
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| 185 | case GROUP_RESERVED_7 : |
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| 186 | case GROUP_RESERVED_8 : |
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| 187 | case GROUP_RESERVED_9 : |
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| 188 | case GROUP_RESERVED_10 : |
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| 189 | case GROUP_RESERVED_11 : |
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| 190 | case GROUP_RESERVED_12 : |
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| 191 | { |
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| 192 | throw ERRORMORPHEO("SPR_access_mode::implement_group", "group number is invalid : it's a reserved group."); |
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| 193 | break; |
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| 194 | } |
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| 195 | case GROUP_CUSTOM_1 : |
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| 196 | case GROUP_CUSTOM_2 : |
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| 197 | case GROUP_CUSTOM_3 : |
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| 198 | case GROUP_CUSTOM_4 : |
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| 199 | case GROUP_CUSTOM_5 : |
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| 200 | case GROUP_CUSTOM_6 : |
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| 201 | case GROUP_CUSTOM_7 : |
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| 202 | case GROUP_CUSTOM_8 : |
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| 203 | { |
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| 204 | throw ERRORMORPHEO("SPR_access_mode::implement_group", "group number is invalid : it's a custom group."); |
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| 205 | break; |
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| 206 | } |
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| 207 | default : |
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| 208 | { |
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| 209 | throw ERRORMORPHEO("SPR_access_mode::implement_group", "group number is invalid : it's a unknow group."); |
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| 210 | break; |
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| 211 | } |
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| 212 | } |
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| 213 | |
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| 214 | return _max_register_by_group[num_group]; |
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| 215 | } |
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| 216 | |
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| 217 | }; // end namespace behavioural |
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| 218 | }; // end namespace morpheo |
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| 219 | |
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