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SPR_access_mode_implement_group.cpp @ 117

Last change on this file since 117 was 117, checked in by rosiere, 15 years ago
1) Platforms : add new organization for test 2) Load_Store_Unit : add array to count nb_check in store_queue 3) Issue_queue and Core_Glue : rewrite the issue network 4) Special_Register_Unit : add reset value to register CID 5) Softwares : add multicontext test 6) Softwares : add SPECINT 7) Softwares : add MiBench? 7) Read_queue : inhib access for r0 8) Change Core_Glue (network) - dont yet support priority and load balancing scheme
Property svn:keywords set to `Id`
File size: 9.1 KB

Line
1	#include "Behavioural/include/SPR_access_mode.h"
2
3	namespace morpheo {
4	namespace behavioural {
5
6	void SPR_access_mode::implement_group (uint32_t num_group, uint32_t nb_reg )
7	{
8	if (_spr_generic[num_group] != NULL)
9	throw ERRORMORPHEO("SPR_access_mode::implement_group", "implement more once a group.");
10
11	_max_register_by_group[num_group] = nb_reg;
12	_spr_generic [num_group] = new spr_access_mode_t [nb_reg];
13	}
14
15	uint32_t SPR_access_mode::implement_group (uint32_t num_group)
16	{
17	if (_spr_generic[num_group] != NULL)
18	throw ERRORMORPHEO("SPR_access_mode::implement_group", "implement more once a group.");
19
20	switch (num_group)
21	{
22	case GROUP_SYSTEM_AND_CONTROL :
23	{
24	implement_group(GROUP_SYSTEM_AND_CONTROL ,NB_REG_GROUP_SYSTEM_AND_CONTROL );
25
26	for (uint32_t i=0 ; i<=8 ; i++)
27	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_ONLY;
28	for (uint32_t i=16; i<=18; i++)
29	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
30	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 19]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY;
31	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 19]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
32	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND;
33	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
34
35	// new register : CID, TID, TSR
36	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 21]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY;
37	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 21]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
38	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 22]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY;
39	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 22]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
40	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 23]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY;
41	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 23]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
42
43	const uint32_t nb_shadow = 1; // max 16
44
45	for (uint32_t i=32; i<32+nb_shadow; i++)
46	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
47	for (uint32_t i=48; i<48+nb_shadow; i++)
48	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
49	for (uint32_t i=64; i<64+nb_shadow; i++)
50	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
51	// for (uint32_t i=1024; i<1024+32*nb_shadow; i++)
52	// _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
53
54	break;
55	}
56	case GROUP_DMMU :
57	{
58	implement_group(GROUP_DMMU ,NB_REG_GROUP_DMMU );
59
60	for (uint32_t i=0; i<=2; i++)
61	_spr_generic [GROUP_DMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
62	_spr_generic [GROUP_DMMU ][ 2]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY;
63	for (uint32_t i=4; i<=11; i++)
64	_spr_generic [GROUP_DMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
65	for (uint32_t i=512; i<=1535; i++)
66	_spr_generic [GROUP_DMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
67
68	break;
69	}
70	case GROUP_IMMU :
71	{
72	implement_group(GROUP_IMMU ,NB_REG_GROUP_IMMU );
73
74	for (uint32_t i=0; i<=2; i++)
75	_spr_generic [GROUP_IMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
76	_spr_generic [GROUP_IMMU ][ 2]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY;
77	for (uint32_t i=4; i<=11; i++)
78	_spr_generic [GROUP_IMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
79	for (uint32_t i=512; i<=1536; i++)
80	_spr_generic [GROUP_IMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
81
82	break;
83	}
84	case GROUP_DCACHE :
85	{
86	implement_group(GROUP_DCACHE ,NB_REG_GROUP_DCACHE );
87
88	_spr_generic [GROUP_DCACHE ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
89	for (uint32_t i=1; i<=5; i++)
90	{
91	_spr_generic [GROUP_DCACHE ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY;
92	_spr_generic [GROUP_DCACHE ][ i]._user_access_mode = SPR_ACCESS_MODE_WRITE_ONLY;
93	}
94	_spr_generic [GROUP_DCACHE ][ 3]._user_access_mode = SPR_ACCESS_MODE_NONE;
95
96	break;
97	}
98	case GROUP_ICACHE :
99	{
100	implement_group(GROUP_ICACHE ,NB_REG_GROUP_ICACHE );
101
102	_spr_generic [GROUP_ICACHE ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
103	for (uint32_t i=1; i<=3; i++)
104	{
105	_spr_generic [GROUP_ICACHE ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY;
106	_spr_generic [GROUP_ICACHE ][ i]._user_access_mode = SPR_ACCESS_MODE_WRITE_ONLY;
107	}
108	_spr_generic [GROUP_ICACHE ][ 2]._user_access_mode = SPR_ACCESS_MODE_NONE;
109
110	break;
111	}
112	case GROUP_MAC :
113	{
114	implement_group(GROUP_MAC ,NB_REG_GROUP_MAC );
115
116	for (uint32_t i=1; i<=2; i++)
117	{
118	_spr_generic [GROUP_MAC ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
119	_spr_generic [GROUP_MAC ][ i]._user_access_mode = SPR_ACCESS_MODE_READ_WRITE;
120	}
121
122	break;
123	}
124	case GROUP_DEBUG :
125	{
126	implement_group(GROUP_DEBUG ,NB_REG_GROUP_DEBUG );
127
128	for (uint32_t i=0; i<=21; i++)
129	_spr_generic [GROUP_DEBUG ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
130
131	break;
132	}
133	case GROUP_PERFORMANCE_COUNTER :
134	{
135	implement_group(GROUP_PERFORMANCE_COUNTER ,NB_REG_GROUP_PERFORMANCE_COUNTER );
136
137	for (uint32_t i=0; i<=7; i++)
138	{
139	_spr_generic [GROUP_PERFORMANCE_COUNTER][ i]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND;
140	_spr_generic [GROUP_PERFORMANCE_COUNTER][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
141	}
142	for (uint32_t i=8; i<=15; i++)
143	_spr_generic [GROUP_PERFORMANCE_COUNTER][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
144
145	break;
146	}
147	case GROUP_POWER_MANAGEMENT :
148	{
149	implement_group(GROUP_POWER_MANAGEMENT ,NB_REG_GROUP_POWER_MANAGEMENT );
150
151	_spr_generic [GROUP_POWER_MANAGEMENT ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
152
153	break;
154	}
155	case GROUP_PIC :
156	{
157	implement_group(GROUP_PIC ,NB_REG_GROUP_PIC );
158
159	_spr_generic [GROUP_PIC ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
160	_spr_generic [GROUP_PIC ][ 2]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
161
162	break;
163	}
164	case GROUP_TICK_TIMER :
165	{
166	implement_group(GROUP_TICK_TIMER ,NB_REG_GROUP_TICK_TIMER );
167
168	_spr_generic [GROUP_TICK_TIMER ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
169	_spr_generic [GROUP_TICK_TIMER ][ 1]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
170	_spr_generic [GROUP_TICK_TIMER ][ 1]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND;
171
172	break;
173	}
174	case GROUP_FLOATING_POINT :
175	{
176	implement_group(GROUP_FLOATING_POINT ,NB_REG_GROUP_FLOATING_POINT );
177	break;
178	}
179	case GROUP_RESERVED_1 :
180	case GROUP_RESERVED_2 :
181	case GROUP_RESERVED_3 :
182	case GROUP_RESERVED_4 :
183	case GROUP_RESERVED_5 :
184	case GROUP_RESERVED_6 :
185	case GROUP_RESERVED_7 :
186	case GROUP_RESERVED_8 :
187	case GROUP_RESERVED_9 :
188	case GROUP_RESERVED_10 :
189	case GROUP_RESERVED_11 :
190	case GROUP_RESERVED_12 :
191	{
192	throw ERRORMORPHEO("SPR_access_mode::implement_group", "group number is invalid : it's a reserved group.");
193	break;
194	}
195	case GROUP_CUSTOM_1 :
196	case GROUP_CUSTOM_2 :
197	case GROUP_CUSTOM_3 :
198	case GROUP_CUSTOM_4 :
199	case GROUP_CUSTOM_5 :
200	case GROUP_CUSTOM_6 :
201	case GROUP_CUSTOM_7 :
202	case GROUP_CUSTOM_8 :
203	{
204	throw ERRORMORPHEO("SPR_access_mode::implement_group", "group number is invalid : it's a custom group.");
205	break;
206	}
207	default :
208	{
209	throw ERRORMORPHEO("SPR_access_mode::implement_group", "group number is invalid : it's a unknow group.");
210	break;
211	}
212	}
213
214	return _max_register_by_group[num_group];
215	}
216
217	}; // end namespace behavioural
218	}; // end namespace morpheo
219

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_implement_group.cpp @ 117

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