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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_implement_group.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 16 years ago
Almost complete design with Test and test platform
Property svn:keywords set to `Id`
File size: 8.4 KB

Line
1	#include "Behavioural/include/SPR_access_mode.h"
2
3	namespace morpheo {
4	namespace behavioural {
5
6	void SPR_access_mode::implement_group (uint32_t num_group, uint32_t nb_reg )
7	{
8	if (_spr_generic[num_group] != NULL)
9	throw ERRORMORPHEO("SPR_access_mode::implement_group", "implement more once a group.");
10
11	_max_register_by_group[num_group] = nb_reg;
12	_spr_generic [num_group] = new spr_access_mode_t [nb_reg];
13	}
14
15	uint32_t SPR_access_mode::implement_group (uint32_t num_group)
16	{
17	if (_spr_generic[num_group] != NULL)
18	throw ERRORMORPHEO("SPR_access_mode::implement_group", "implement more once a group.");
19
20	switch (num_group)
21	{
22	case GROUP_SYSTEM_AND_CONTROL :
23	{
24	implement_group(GROUP_SYSTEM_AND_CONTROL ,NB_REG_GROUP_SYSTEM_AND_CONTROL );
25
26	for (uint32_t i=0 ; i<=8 ; i++)
27	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_ONLY;
28	for (uint32_t i=16; i<=18; i++)
29	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
30	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 19]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY;
31	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 19]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
32	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND;
33	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
34
35	const uint32_t nb_shadow = 1;
36
37	for (uint32_t i=32; i<=32+nb_shadow; i++)
38	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
39	for (uint32_t i=48; i<=48+nb_shadow; i++)
40	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
41	for (uint32_t i=64; i<=64+nb_shadow; i++)
42	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
43	for (uint32_t i=1024; i<=1024+32*nb_shadow; i++)
44	_spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
45
46	break;
47	}
48	case GROUP_DMMU :
49	{
50	implement_group(GROUP_DMMU ,NB_REG_GROUP_DMMU );
51
52	for (uint32_t i=0; i<=2; i++)
53	_spr_generic [GROUP_DMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
54	_spr_generic [GROUP_DMMU ][ 2]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY;
55	for (uint32_t i=4; i<=11; i++)
56	_spr_generic [GROUP_DMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
57	for (uint32_t i=512; i<=1535; i++)
58	_spr_generic [GROUP_DMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
59
60	break;
61	}
62	case GROUP_IMMU :
63	{
64	implement_group(GROUP_IMMU ,NB_REG_GROUP_IMMU );
65
66	for (uint32_t i=0; i<=2; i++)
67	_spr_generic [GROUP_IMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
68	_spr_generic [GROUP_IMMU ][ 2]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY;
69	for (uint32_t i=4; i<=11; i++)
70	_spr_generic [GROUP_IMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
71	for (uint32_t i=512; i<=1536; i++)
72	_spr_generic [GROUP_IMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
73
74	break;
75	}
76	case GROUP_DCACHE :
77	{
78	implement_group(GROUP_DCACHE ,NB_REG_GROUP_DCACHE );
79
80	_spr_generic [GROUP_DCACHE ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
81	for (uint32_t i=1; i<=5; i++)
82	{
83	_spr_generic [GROUP_DCACHE ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY;
84	_spr_generic [GROUP_DCACHE ][ i]._user_access_mode = SPR_ACCESS_MODE_WRITE_ONLY;
85	}
86	_spr_generic [GROUP_DCACHE ][ 3]._user_access_mode = SPR_ACCESS_MODE_NONE;
87
88	break;
89	}
90	case GROUP_ICACHE :
91	{
92	implement_group(GROUP_ICACHE ,NB_REG_GROUP_ICACHE );
93
94	_spr_generic [GROUP_ICACHE ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
95	for (uint32_t i=1; i<=3; i++)
96	{
97	_spr_generic [GROUP_ICACHE ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY;
98	_spr_generic [GROUP_ICACHE ][ i]._user_access_mode = SPR_ACCESS_MODE_WRITE_ONLY;
99	}
100	_spr_generic [GROUP_ICACHE ][ 2]._user_access_mode = SPR_ACCESS_MODE_NONE;
101
102	break;
103	}
104	case GROUP_MAC :
105	{
106	implement_group(GROUP_MAC ,NB_REG_GROUP_MAC );
107
108	for (uint32_t i=1; i<=2; i++)
109	{
110	_spr_generic [GROUP_MAC ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
111	_spr_generic [GROUP_MAC ][ i]._user_access_mode = SPR_ACCESS_MODE_READ_WRITE;
112	}
113
114	break;
115	}
116	case GROUP_DEBUG :
117	{
118	implement_group(GROUP_DEBUG ,NB_REG_GROUP_DEBUG );
119
120	for (uint32_t i=0; i<=21; i++)
121	_spr_generic [GROUP_DEBUG ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
122
123	break;
124	}
125	case GROUP_PERFORMANCE_COUNTER :
126	{
127	implement_group(GROUP_PERFORMANCE_COUNTER ,NB_REG_GROUP_PERFORMANCE_COUNTER );
128
129	for (uint32_t i=0; i<=7; i++)
130	{
131	_spr_generic [GROUP_PERFORMANCE_COUNTER][ i]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND;
132	_spr_generic [GROUP_PERFORMANCE_COUNTER][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
133	}
134	for (uint32_t i=8; i<=15; i++)
135	_spr_generic [GROUP_PERFORMANCE_COUNTER][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
136
137	break;
138	}
139	case GROUP_POWER_MANAGEMENT :
140	{
141	implement_group(GROUP_POWER_MANAGEMENT ,NB_REG_GROUP_POWER_MANAGEMENT );
142
143	_spr_generic [GROUP_POWER_MANAGEMENT ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
144
145	break;
146	}
147	case GROUP_PIC :
148	{
149	implement_group(GROUP_PIC ,NB_REG_GROUP_PIC );
150
151	_spr_generic [GROUP_PIC ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
152	_spr_generic [GROUP_PIC ][ 2]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
153
154	break;
155	}
156	case GROUP_TICK_TIMER :
157	{
158	implement_group(GROUP_TICK_TIMER ,NB_REG_GROUP_TICK_TIMER );
159
160	_spr_generic [GROUP_TICK_TIMER ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
161	_spr_generic [GROUP_TICK_TIMER ][ 1]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE;
162	_spr_generic [GROUP_TICK_TIMER ][ 1]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND;
163
164	break;
165	}
166	case GROUP_FLOATING_POINT :
167	{
168	implement_group(GROUP_FLOATING_POINT ,NB_REG_GROUP_FLOATING_POINT );
169	break;
170	}
171	case GROUP_RESERVED_1 :
172	case GROUP_RESERVED_2 :
173	case GROUP_RESERVED_3 :
174	case GROUP_RESERVED_4 :
175	case GROUP_RESERVED_5 :
176	case GROUP_RESERVED_6 :
177	case GROUP_RESERVED_7 :
178	case GROUP_RESERVED_8 :
179	case GROUP_RESERVED_9 :
180	case GROUP_RESERVED_10 :
181	case GROUP_RESERVED_11 :
182	case GROUP_RESERVED_12 :
183	{
184	throw ERRORMORPHEO("SPR_access_mode::implement_group", "group number is invalid : it's a reserved group.");
185	break;
186	}
187	case GROUP_CUSTOM_1 :
188	case GROUP_CUSTOM_2 :
189	case GROUP_CUSTOM_3 :
190	case GROUP_CUSTOM_4 :
191	case GROUP_CUSTOM_5 :
192	case GROUP_CUSTOM_6 :
193	case GROUP_CUSTOM_7 :
194	case GROUP_CUSTOM_8 :
195	{
196	throw ERRORMORPHEO("SPR_access_mode::implement_group", "group number is invalid : it's a custom group.");
197	break;
198	}
199	default :
200	{
201	throw ERRORMORPHEO("SPR_access_mode::implement_group", "group number is invalid : it's a unknow group.");
202	break;
203	}
204	}
205
206	return _max_register_by_group[num_group];
207	}
208
209	}; // end namespace behavioural
210	}; // end namespace morpheo
211

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