1 | /* |
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2 | * $Id$ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | */ |
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7 | |
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8 | #include "Behavioural/include/Signal.h" |
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9 | |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | |
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14 | #ifdef VHDL |
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15 | void Signal::set_port (Vhdl * & vhdl) |
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16 | { |
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17 | log_printf(FUNC,Behavioural,"set_port (Vhdl)","Begin"); |
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18 | |
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19 | if ((_presence_port == PORT_VHDL_YES_TESTBENCH_YES) or |
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20 | (_presence_port == PORT_VHDL_YES_TESTBENCH_NO ) or |
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21 | (_presence_port == CLOCK_VHDL_YES) or |
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22 | (_presence_port == RESET_VHDL_YES)) |
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23 | vhdl->set_port (_name,_direction,_size); |
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24 | |
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25 | log_printf(FUNC,Behavioural,"set_port (Vhdl)","End"); |
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26 | }; |
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27 | |
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28 | #ifdef VHDL_TESTBENCH |
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29 | void Signal::set_signal (Vhdl * & vhdl) |
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30 | { |
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31 | log_printf(FUNC,Behavioural,"set_signal (Vhdl)","Begin"); |
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32 | |
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33 | if ( (_presence_port == PORT_VHDL_YES_TESTBENCH_YES) |
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34 | or (_presence_port == PORT_VHDL_NO_TESTBENCH_YES ) |
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35 | // or (_presence_port == CLOCK_VHDL_YES) |
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36 | // or (_presence_port == CLOCK_VHDL_NO ) |
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37 | // or (_presence_port == RESET_VHDL_YES) |
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38 | // or (_presence_port == RESET_VHDL_NO ) |
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39 | ) |
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40 | vhdl->set_signal (_name ,_size); |
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41 | |
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42 | if (_direction == OUT) |
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43 | vhdl->set_signal (_name+"_test",_size); |
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44 | |
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45 | log_printf(FUNC,Behavioural,"set_signal (Vhdl)","End"); |
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46 | }; |
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47 | #endif |
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48 | #endif |
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49 | |
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50 | }; // end namespace behavioural |
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51 | }; // end namespace morpheo |
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