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[2] | 1 | #ifdef VHDL_TESTBENCH |
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| 2 | |
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| 3 | /* |
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| 4 | * $Id$ |
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| 5 | * |
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| 6 | * [ Description ] |
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| 7 | * must be call after all add port |
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| 8 | */ |
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| 9 | |
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| 10 | #include "Behavioural/include/Vhdl_Testbench.h" |
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| 11 | |
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| 12 | #include <sstream> |
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| 13 | using namespace std; |
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| 14 | |
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| 15 | namespace morpheo { |
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| 16 | namespace behavioural { |
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| 17 | |
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| 18 | void Vhdl_Testbench::set_clock (string name, |
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| 19 | bool model_have_clock) |
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| 20 | { |
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| 21 | _clock_name = name; |
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| 22 | _vhdl->set_signal (name,std_logic(1),"'0'"); |
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| 23 | |
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| 24 | if (model_have_clock == true) |
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| 25 | _list_port.push_back(name); |
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| 26 | |
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| 27 | _num_input = _list_input_size .begin(); |
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| 28 | _num_output = _list_output_size.begin(); |
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| 29 | }; |
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| 30 | |
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| 31 | }; // end namespace behavioural |
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| 32 | }; // end namespace morpheo |
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| 33 | |
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| 34 | #endif |
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