[2] | 1 | <?xml version="1.0" encoding="ISO-8859-1" ?> |
---|
| 2 | |
---|
| 3 | <cpu name="IBM Power 5" > |
---|
| 4 | |
---|
| 5 | <!-- **************************** --> |
---|
| 6 | <!-- * Définition du processeur * --> |
---|
| 7 | <!-- **************************** --> |
---|
| 8 | |
---|
| 9 | <type> |
---|
| 10 | <definition id="0"> |
---|
| 11 | <allow id="0" /> |
---|
| 12 | </definition> |
---|
| 13 | |
---|
| 14 | <definition id="1"> |
---|
| 15 | <allow id="0" /> |
---|
| 16 | <allow id="2" /> |
---|
| 17 | </definition> |
---|
| 18 | |
---|
| 19 | <affectation name="INST_L_ADD" /> |
---|
| 20 | <affectation name="INST_L_SUB" type="0" /> |
---|
| 21 | <affectation type="1" name="INST_L_AND" /> |
---|
| 22 | </type> |
---|
| 23 | |
---|
| 24 | <!-- defaut : delay = 1 et latence = 1 --> |
---|
| 25 | <latence id="0"> |
---|
| 26 | |
---|
| 27 | </latence> |
---|
| 28 | |
---|
| 29 | <latence id="1"> |
---|
| 30 | <operation name="inst1" /> |
---|
| 31 | <operation name="inst2" delay="8" /> |
---|
| 32 | <operation name="inst3" delay="1" latence="2" /> |
---|
| 33 | <operation name="inst4" latence="1" delay="2" /> |
---|
| 34 | <operation name="inst5" latence="2" /> |
---|
| 35 | <operation latence="1" name="inst6" delay="2" /> |
---|
| 36 | <operation latence="1" delay="2" name="inst7" /> |
---|
| 37 | </latence> |
---|
| 38 | |
---|
| 39 | <internal> |
---|
| 40 | |
---|
| 41 | <global> |
---|
| 42 | <size_data value="32" /> |
---|
| 43 | <scheme_bypass algo ="complet"/> |
---|
| 44 | <isa> |
---|
| 45 | <ORFPX type="1" value="1" /> |
---|
| 46 | <ORBIS value="true" /> |
---|
| 47 | <ORVDX value="false" type="2" /> |
---|
| 48 | </isa> |
---|
| 49 | </global> |
---|
| 50 | |
---|
| 51 | <cache> |
---|
| 52 | <icache id="0"> |
---|
| 53 | <arbiter algo ="roundrobin" /> |
---|
| 54 | <nb_port value="2" /> |
---|
| 55 | </icache> |
---|
| 56 | <icache id="1"> |
---|
| 57 | <nb_port value="2" /> |
---|
| 58 | <arbiter algo ="roundrobin" /> |
---|
| 59 | </icache> |
---|
| 60 | <icache id="2"> |
---|
| 61 | <nb_port value="2" /> |
---|
| 62 | </icache> |
---|
| 63 | <icache id="3"> |
---|
| 64 | <arbiter algo ="roundrobin" /> |
---|
| 65 | </icache> |
---|
| 66 | <icache id="4"> |
---|
| 67 | </icache> |
---|
| 68 | |
---|
| 69 | <dcache id="0"> |
---|
| 70 | <arbiter algo ="roundrobin" /> |
---|
| 71 | <nb_port value="2" /> |
---|
| 72 | </dcache> |
---|
| 73 | </cache> |
---|
| 74 | |
---|
| 75 | <!-- Etage 1 : Ifetch --> |
---|
| 76 | <ifetch id="0"> |
---|
| 77 | <link_icache id="0" /> |
---|
| 78 | <link_predictor id="0" /> |
---|
| 79 | <link_decod id="0" /> |
---|
| 80 | </ifetch> |
---|
| 81 | |
---|
| 82 | <ifetch id="1"> |
---|
| 83 | <nb_inst_fetch value="4" /> |
---|
| 84 | <size_fetch_queue value="3" /> |
---|
| 85 | |
---|
| 86 | <link_icache id="0" /> |
---|
| 87 | <link_decod id="0" /> |
---|
| 88 | <link_predictor id="0" /> |
---|
| 89 | </ifetch> |
---|
| 90 | |
---|
| 91 | <ifetch id="2"> |
---|
| 92 | |
---|
| 93 | <link_decod id="0" /> |
---|
| 94 | <link_icache id="0" /> |
---|
| 95 | |
---|
| 96 | <size_fetch_queue value="3" /> |
---|
| 97 | |
---|
| 98 | <link_predictor id="0" /> |
---|
| 99 | </ifetch> |
---|
| 100 | |
---|
| 101 | <ifetch id="3"> |
---|
| 102 | <nb_inst_fetch value="4" /> |
---|
| 103 | |
---|
| 104 | <link_decod id="0" /> |
---|
| 105 | <link_predictor id="0" /> |
---|
| 106 | <link_icache id="0" /> |
---|
| 107 | </ifetch> |
---|
| 108 | |
---|
| 109 | |
---|
| 110 | <!-- Predicteur de branchement --> |
---|
| 111 | <prediction id="0"> |
---|
| 112 | |
---|
| 113 | <arbiter algo ="roundrobin" /> |
---|
| 114 | <scheme_predictor algo ="all" /> |
---|
| 115 | <size_return_address_stack value="8" /> |
---|
| 116 | <size_update_prediction value="4" /> |
---|
| 117 | |
---|
| 118 | <branch_target_buffer> |
---|
| 119 | <size_branch_target_buffer value="32" /> |
---|
| 120 | <associativity_branch_target_buffer value="4" /> |
---|
| 121 | </branch_target_buffer> |
---|
| 122 | |
---|
| 123 | <meta_predictor> |
---|
| 124 | <size_prediction value="32" /> |
---|
| 125 | <nb_bit_counter value="2" /> |
---|
| 126 | </meta_predictor> |
---|
| 127 | |
---|
| 128 | <global_predictor> |
---|
| 129 | <size_prediction_history_table value="4" /> |
---|
| 130 | <size_prediction value="16" /> |
---|
| 131 | <nb_bit_counter value="2" /> |
---|
| 132 | </global_predictor> |
---|
| 133 | |
---|
| 134 | <local_predictor> |
---|
| 135 | <size_prediction_history_table value="4" /> |
---|
| 136 | <size_prediction_l1 value="8" /> |
---|
| 137 | <size_prediction_l2 value="16" /> |
---|
| 138 | <nb_bit_counter value="2" /> |
---|
| 139 | <xor value="false" /> |
---|
| 140 | </local_predictor> |
---|
| 141 | |
---|
| 142 | </prediction> |
---|
| 143 | |
---|
| 144 | |
---|
| 145 | |
---|
| 146 | |
---|
| 147 | |
---|
| 148 | <branch_queue id="0"> |
---|
| 149 | <!-- |
---|
| 150 | <arbiter algo ="roundrobin" /> |
---|
| 151 | <nb_branch_speculated value="4" /> |
---|
| 152 | <nb_branch_complete value="1" /> |
---|
| 153 | --> |
---|
| 154 | </branch_queue> |
---|
| 155 | |
---|
| 156 | |
---|
| 157 | |
---|
| 158 | |
---|
| 159 | |
---|
| 160 | <!-- Etage 2 : Décodage --> |
---|
| 161 | <decod id="0"> |
---|
| 162 | <!-- |
---|
| 163 | <arbiter algo ="roundrobin" /> |
---|
| 164 | <link_rename id="0" /> |
---|
| 165 | <link_branch_queue id="0" /> |
---|
| 166 | <nb_inst_decod value="3" /> |
---|
| 167 | <nb_inst_rename value="3" /> |
---|
| 168 | <size_decod_queue value="4" /> |
---|
| 169 | --> |
---|
| 170 | </decod> |
---|
| 171 | |
---|
| 172 | |
---|
| 173 | |
---|
| 174 | |
---|
| 175 | <!-- Etage 3 : Renommage --> |
---|
| 176 | <rename id="0"> |
---|
| 177 | <!-- |
---|
| 178 | <arbiter algo ="roundrobin" /> |
---|
| 179 | |
---|
| 180 | <slot> |
---|
| 181 | <route id="0" /> |
---|
| 182 | </slot> |
---|
| 183 | |
---|
| 184 | <link_commit id="0" /> |
---|
| 185 | <link_load_store_queue id="0" /> |
---|
| 186 | <link_special_register_file id="0" /> |
---|
| 187 | |
---|
| 188 | <nb_inst_rename value="5" /> |
---|
| 189 | <nb_inst_select_windows value="9" /> |
---|
| 190 | <size_rename_queue value="15" /> |
---|
| 191 | <nb_gpr_phy value="128" /> |
---|
| 192 | <nb_gpr_free value="4" /> |
---|
| 193 | <nb_spr_phy value="32" /> |
---|
| 194 | <nb_spr_free value="2" /> |
---|
| 195 | --> |
---|
| 196 | </rename> |
---|
| 197 | |
---|
| 198 | |
---|
| 199 | |
---|
| 200 | |
---|
| 201 | |
---|
| 202 | <!-- Etage 4 Selection/Issue --> |
---|
| 203 | <select_issue> |
---|
| 204 | <!-- lien entre un slot est un cluster --> |
---|
| 205 | <slot id="0"> |
---|
| 206 | <!-- lien entre un cluster et une waitunit --> |
---|
| 207 | <cluster id="0"> |
---|
| 208 | <route id="0" /> |
---|
| 209 | </cluster> |
---|
| 210 | </slot> |
---|
| 211 | </select_issue> |
---|
| 212 | |
---|
| 213 | |
---|
| 214 | |
---|
| 215 | |
---|
| 216 | |
---|
| 217 | <!-- Etage 5 : Execution --> |
---|
| 218 | <execute> |
---|
| 219 | |
---|
| 220 | <!-- Clusterisation des unités d'éxecution --> |
---|
| 221 | <cluster id="0"> |
---|
| 222 | <!-- bypass intra cluster --> |
---|
| 223 | <bypass_register value="false" /> |
---|
| 224 | <bypass_status value="false" /> |
---|
| 225 | |
---|
| 226 | <!-- Wait Unit (Selection queue - Reservation Station) --> |
---|
| 227 | <waitunit id="0"> |
---|
| 228 | <size_select_queue value="4" /> |
---|
| 229 | <size_reservation_station value="4" /> |
---|
| 230 | <dispatch> |
---|
| 231 | <route id="0" /> |
---|
| 232 | </dispatch> |
---|
| 233 | </waitunit> |
---|
| 234 | |
---|
| 235 | <!-- Executive Unit (Ue (type des opérations accepté et latence des opérations) - Execute queue) --> |
---|
| 236 | <executiveunit id="0"> |
---|
| 237 | <arbiter algo ="roundrobin" /> |
---|
| 238 | <size_execute_queue value="4" /> |
---|
| 239 | <nb_inst_execute value="2" /> |
---|
| 240 | <type value="0" /> |
---|
| 241 | <latence value="0" /> |
---|
| 242 | </executiveunit> |
---|
| 243 | |
---|
| 244 | </cluster> |
---|
| 245 | </execute> |
---|
| 246 | |
---|
| 247 | |
---|
| 248 | |
---|
| 249 | |
---|
| 250 | <!-- Etage 5bis : Memory --> |
---|
| 251 | <memory id="0"> |
---|
| 252 | <arbiter algo ="roundrobin" /> |
---|
| 253 | <link_dcache id="0" /> |
---|
| 254 | <link_commit id="0" /> |
---|
| 255 | <nb_inst_commit value="4" /> |
---|
| 256 | <nb_memory_complete value="5" /> |
---|
| 257 | <size_load_store_queue value="32" /> |
---|
| 258 | <bypass_memory_in value="false" /> |
---|
| 259 | <bypass_memory_out value="false" /> |
---|
| 260 | <bypass_memory_internal value="false" /> |
---|
| 261 | </memory> |
---|
| 262 | |
---|
| 263 | |
---|
| 264 | |
---|
| 265 | |
---|
| 266 | <!-- Banc de registres |
---|
| 267 | (Autant de RegFile que d'étage 3) --> |
---|
| 268 | <general_registerfile id="0"> |
---|
| 269 | <arbiter algo ="roundrobin" /> |
---|
| 270 | <nb_gpr_reader value="5" /> |
---|
| 271 | <nb_gpr_writer value="5" /> |
---|
| 272 | <nb_spr_reader value="5" /> |
---|
| 273 | <nb_spr_writer value="5" /> |
---|
| 274 | </general_registerfile> |
---|
| 275 | |
---|
| 276 | |
---|
| 277 | |
---|
| 278 | |
---|
| 279 | |
---|
| 280 | <!-- Etage 6 : Commit --> |
---|
| 281 | <commit id="0"> |
---|
| 282 | <arbiter algo ="roundrobin" /> |
---|
| 283 | <nb_inst_commit value="4" /> |
---|
| 284 | <nb_inst_update value="5" /> |
---|
| 285 | <nb_inst_update_windows value="9" /> |
---|
| 286 | <size_re_order_buffer value="32" /> |
---|
| 287 | <commit_out_of_order_thread value="false" /> |
---|
| 288 | </commit> |
---|
| 289 | |
---|
| 290 | |
---|
| 291 | </internal> |
---|
| 292 | |
---|
| 293 | </cpu> |
---|