source: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_automate-fsm_dcache_req.fig @ 42

Last change on this file since 42 was 42, checked in by rosiere, 17 years ago

Modification des classes d'encapsulation des interfaces :

  • gère les signaux à écrire dans le vhdl
  • les traces pour le testbench
  • la génération des vhdl structurelles

-> test sur la Pattern History Table

File size: 2.6 KB
Line 
1#FIG 3.2
2Landscape
3Center
4Inches
5Letter 
6100.00
7Single
8-2
91200 2
105 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5362.500 2700.000 5550 2700 5250 2550 5250 2850
11        3 0 1.00 60.00 120.00
125 1 0 1 0 7 50 -1 -1 0.000 0 0 1 0 6525.000 4725.000 6450 4200 6900 4350 7050 4800
13        3 0 1.00 60.00 120.00
145 1 0 1 0 7 50 -1 -1 0.000 0 0 1 0 6675.000 4425.000 6750 4950 6300 4800 6150 4350
15        3 0 1.00 60.00 120.00
165 1 0 1 0 7 50 -1 -1 0.000 0 0 1 0 7350.000 5512.500 7500 5400 7350 5700 7200 5400
17        3 0 1.00 60.00 120.00
185 1 0 1 0 7 50 -1 -1 0.000 0 0 1 0 4350.000 5512.500 4500 5400 4350 5700 4200 5400
19        3 0 1.00 60.00 120.00
205 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5025.000 4425.000 4950 4950 5400 4800 5550 4350
21        3 0 1.00 60.00 120.00
225 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5175.000 4725.000 5250 4200 4800 4350 4650 4800
23        3 0 1.00 60.00 120.00
245 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 5362.500 3750.000 5550 3750 5250 3600 5250 3900
25        3 0 1.00 60.00 120.00
266 5175 3675 6525 4425
271 1 0 1 0 11 50 -1 20 0.000 1 0.0000 5850 4050 600 300 5850 4050 6450 3750
284 1 0 50 -1 2 8 0.0000 0 105 420 5850 4050 Request\001
29-6
306 5175 2625 6525 3375
311 1 0 1 0 11 50 -1 20 0.000 1 0.0000 5850 3000 600 300 5850 3000 6450 2700
324 1 0 50 -1 2 8 0.0000 0 90 210 5850 3000 Init\001
33-6
346 6675 4725 8025 5475
351 1 0 1 0 11 50 -1 20 0.000 1 0.0000 7350 5100 600 300 7350 5100 7950 4800
364 1 0 50 -1 2 8 0.0000 0 105 1185 7350 5025 QUEUE_READ_HIT\001
374 1 0 50 -1 2 8 0.0000 0 105 255 7350 5250 Busy\001
38-6
396 3675 4725 5025 5475
401 1 0 1 0 11 50 -1 20 0.000 1 0.0000 4350 5100 600 300 4350 5100 4950 4800
414 1 0 50 -1 2 8 0.0000 0 105 255 4350 5250 Busy\001
424 1 0 50 -1 2 8 0.0000 0 105 780 4350 5025 QUEUE_REQ\001
43-6
442 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2
45        3 0 1.00 60.00 120.00
46         6450 2550 6300 2775
472 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
48        3 0 1.00 60.00 120.00
49         5850 3300 5850 3750
504 0 0 50 -1 0 8 0.0000 0 105 645 5925 3525 (3) : end_init\001
514 1 0 50 -1 0 8 0.0000 0 120 1230 7350 5850 (5) : queue_read_hit.full\001
524 2 0 50 -1 0 8 0.0000 0 120 1485 6675 5250 (6) : not(queue_read_hit.full)\001
534 1 0 50 -1 0 8 0.0000 0 120 990 4350 5850 (8) : queue_req.full\001
544 0 0 50 -1 0 8 0.0000 0 120 1245 5025 5100 (9) : not(queue_req.full)\001
554 2 0 50 -1 0 8 0.0000 0 105 885 5175 3525 (10) : not(A or B)\001
564 0 0 50 -1 0 8 0.0000 0 120 2430 3750 6300 A : ((read and miss) or write).request_queue.full\001
574 1 0 50 -1 0 8 0.0000 0 105 810 6525 2475 (1) : not(nreset)\001
584 1 0 50 -1 0 8 0.0000 0 105 900 5175 2475 (2) : not(end_init)\001
594 0 0 50 -1 0 8 0.0000 0 120 3345 3750 6450 B : ((read and not (miss)) or (type_others)) and queue_read_hit.full\001
604 0 0 50 -1 0 8 0.0000 0 105 315 6975 4275 (4) : B\001
614 2 0 50 -1 0 8 0.0000 0 105 330 4725 4275 (7) : A\001
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