source: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_coherence_memoire.fig @ 42

Last change on this file since 42 was 42, checked in by rosiere, 17 years ago

Modification des classes d'encapsulation des interfaces :

  • gère les signaux à écrire dans le vhdl
  • les traces pour le testbench
  • la génération des vhdl structurelles

-> test sur la Pattern History Table
File size: 1.2 KB
Line 
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2Landscape
3Center
4Inches
5Letter 
6100.00
7Single
8-2
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115 1 0 1 0 7 50 -1 -1 0.000 0 1 0 0 5193.750 2700.000 4800 2325 4650 2700 4800 3075
125 1 0 1 0 7 50 -1 -1 0.000 0 1 0 0 5193.750 5100.000 4800 4725 4650 5100 4800 5475
134 0 0 50 -1 0 12 0.0000 4 135 375 4950 3300 Lock\001
144 0 0 50 -1 0 12 0.0000 4 135 600 4950 4650 UnLock\001
154 0 0 50 -1 0 12 0.0000 4 15 135 4950 4050 ...\001
164 0 0 50 -1 0 12 0.0000 4 15 135 4950 2700 ...\001
174 0 0 50 -1 0 12 0.0000 4 15 135 4950 5100 ...\001
184 2 0 50 -1 0 12 0.0000 4 135 585 4500 3900 Access\001
194 2 0 50 -1 0 12 0.0000 4 135 810 4500 2550 No access\001
204 2 0 50 -1 0 12 0.0000 4 135 810 4500 4950 No access\001
214 2 0 50 -1 0 12 0.0000 4 135 690 4500 3000 variables\001
224 2 0 50 -1 0 12 0.0000 4 135 690 4500 4350 variables\001
234 2 0 50 -1 0 12 0.0000 4 135 840 4500 4125 to a shared\001
244 2 0 50 -1 0 12 0.0000 4 135 840 4500 2775 to a shared\001
254 2 0 50 -1 0 12 0.0000 4 135 840 4500 5175 to a shared\001
264 2 0 50 -1 0 12 0.0000 4 135 690 4500 5400 variables\001
274 0 0 50 -1 0 12 0.0000 4 180 2700 4950 3600 Flush (addressof  shared variables)\001
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