source: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_methodologie.fig @ 17

Last change on this file since 17 was 17, checked in by rosiere, 17 years ago

Documentation : ajout du séminaire du 01/06/2007
File size: 2.1 KB
Line 
1#FIG 3.2  Produced by xfig version 3.2.5-alpha5
2Landscape
3Center
4Inches
5Letter 
6100.00
7Single
8-2
91200 2
105 1 0 1 0 7 50 -1 -1 0.000 0 0 1 0 2625.000 9450.000 1950 10350 1500 9450 1950 8550
11        3 0 1.00 120.00 240.00
125 1 0 1 0 7 50 -1 -1 0.000 0 0 1 0 2700.000 6750.000 1950 8550 750 6750 1950 4950
13        3 0 1.00 120.00 240.00
145 1 0 1 0 7 50 -1 -1 0.000 0 0 1 0 2625.000 5850.000 1950 6750 1500 5850 1950 4950
15        3 0 1.00 120.00 240.00
165 1 0 1 0 7 50 -1 -1 0.000 0 0 1 0 2625.000 4050.000 1950 4950 1500 4050 1950 3150
17        3 0 1.00 120.00 240.00
185 1 0 1 0 7 50 -1 -1 0.000 0 0 1 0 2625.000 2250.000 1950 3150 1500 2250 1950 1350
19        3 0 1.00 120.00 240.00
205 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 -1125.000 4050.000 4650 6750 5250 4050 4650 1350
21        3 0 1.00 120.00 240.00
225 1 0 1 0 7 50 -1 -1 0.000 0 1 1 0 -262.500 4987.500 4650 8625 5850 4950 4650 1350
23        3 0 1.00 120.00 240.00
241 1 0 1 0 7 50 -1 -1 0.000 1 0.0000 3300 4950 1350 600 3300 4950 4650 4350
251 1 0 1 0 7 50 -1 -1 0.000 1 0.0000 3300 8550 1350 600 3300 8550 4650 7950
261 1 0 1 0 7 50 -1 -1 0.000 1 0.0000 3300 10349 1350 600 3300 10349 4650 9749
271 1 0 1 0 7 50 -1 -1 0.000 1 0.0000 3300 3149 1350 600 3300 3149 4650 2549
281 1 0 1 0 7 50 -1 -1 0.000 1 0.0000 3300 1350 1350 600 3300 1350 4650 750
291 1 0 1 0 7 50 -1 -1 0.000 1 0.0000 3300 6750 1350 600 3300 6750 4650 6150
302 1 0 1 0 7 50 -1 -1 0.000 0 0 7 1 0 2
31        3 0 1.00 120.00 240.00
32         3300 9150 3300 9750
332 1 0 1 0 7 50 -1 -1 0.000 0 0 7 1 0 2
34        3 0 1.00 120.00 240.00
35         3300 7350 3300 7950
362 1 0 1 0 7 50 -1 -1 0.000 0 0 7 1 0 2
37        3 0 1.00 120.00 240.00
38         3300 1950 3300 2550
392 1 0 1 0 7 50 -1 -1 0.000 0 0 7 1 0 2
40        3 0 1.00 120.00 240.00
41         3300 3750 3300 4350
422 1 0 1 0 7 50 -1 -1 0.000 0 0 7 1 0 2
43        3 0 1.00 120.00 240.00
44         3300 5550 3300 6150
454 1 0 50 -1 -1 20 0.0000 4 300 2400 3300 6900 SystemC / VHDL\001
464 1 0 50 -1 -1 20 0.0000 4 300 1815 3300 6600 Compatibilit\351\001
474 1 0 50 -1 -1 20 0.0000 4 225 930 3300 4950 VHDL\001
484 1 0 50 -1 -1 20 0.0000 4 225 1440 3300 3150 TestBench\001
494 1 0 50 -1 -1 20 0.0000 4 300 1200 3300 1350 SystemC\001
504 1 0 50 -1 -1 20 0.0000 4 300 2325 3300 8550 FPGA - Synth\350se\001
514 1 0 50 -1 -1 20 0.0000 4 300 2370 3300 10350 FPGA - Mappage\001
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