[100] | 1 | %------------------------------------------------------------------------------ |
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| 2 | % $Id: document-morpheo-vhdl_generation-fr-05_01_registerfile.tex 100 2009-01-08 13:06:27Z rosiere $ |
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| 3 | %------------------------------------------------------------------------------ |
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| 4 | |
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| 5 | \subSection{Banc de Registres Monolithique} |
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| 6 | |
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| 7 | \subsubSection{Fichier RegisterFile\_Monolithic\_vhdl.cpp} |
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| 8 | |
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| 9 | \lstparam{C++} |
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| 10 | \begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl.cpp}] |
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| 11 | void RegisterFile_Monolithic::vhdl (void) |
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| 12 | { |
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| 13 | Vhdl * vhdl = new Vhdl (_name); |
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| 14 | |
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| 15 | _interfaces->set_port (vhdl); |
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| 16 | _component ->vhdl_instance(vhdl); |
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| 17 | |
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| 18 | vhdl_declaration (vhdl); |
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| 19 | vhdl_body (vhdl); |
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| 20 | |
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| 21 | vhdl->generate_file(); |
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| 22 | |
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| 23 | delete vhdl; |
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| 24 | }; |
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| 25 | \end{lstlisting} |
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| 26 | |
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| 27 | |
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| 28 | \subsubSection{Fichier RegisterFile\_Monolithic\_vhdl\_declaration.cpp} |
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| 29 | |
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| 30 | \lstparam{C++} |
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| 31 | \begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl\_declaration.cpp}] |
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| 32 | void RegisterFile_Monolithic::vhdl_declaration (Vhdl * & vhdl) |
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| 33 | { |
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| 34 | vhdl->set_type ("Tregfile", "array " + std_logic_range(_param->_nb_word,true)+ |
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| 35 | " of "+ |
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| 36 | std_logic(_param->_size_word)); |
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| 37 | |
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| 38 | vhdl->set_signal ("reg_DATA", "Tregfile"); |
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| 39 | }; |
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| 40 | \end{lstlisting} |
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| 41 | |
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| 42 | \subsubSection{Fichier RegisterFile\_Monolithic\_vhdl\_body.cpp} |
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| 43 | |
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| 44 | \lstparam{C++} |
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| 45 | \begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl\_body.cpp}] |
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| 46 | void RegisterFile_Monolithic::vhdl_body (Vhdl * & vhdl) |
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| 47 | { |
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| 48 | vhdl->set_body (0,""); |
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| 49 | vhdl->set_comment(0,"---------------------------------------------------"); |
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| 50 | vhdl->set_comment(0," Ack"); |
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| 51 | vhdl->set_comment(0,"---------------------------------------------------"); |
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| 52 | vhdl->set_body (0,""); |
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| 53 | |
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| 54 | for (uint32_t i = 0; i < _param->_nb_port_read; i++) |
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| 55 | vhdl->set_body (0,"out_READ_"+toString(i)+"_ACK <= '1';"); |
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| 56 | for (uint32_t i = 0; i < _param->_nb_port_write; i++) |
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| 57 | vhdl->set_body (0,"out_WRITE_"+toString(i)+"_ACK <= '1';"); |
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| 58 | |
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| 59 | vhdl->set_body (0,""); |
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| 60 | vhdl->set_comment(0,"---------------------------------------------------"); |
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| 61 | vhdl->set_comment(0," Read RegisterFile"); |
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| 62 | vhdl->set_comment(0,"---------------------------------------------------"); |
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| 63 | vhdl->set_body (0,""); |
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| 64 | |
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| 65 | for (uint32_t i = 0; i < _param->_nb_port_read; i++) |
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| 66 | { |
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| 67 | std::string str_address; |
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| 68 | if (_param->_have_port_address) |
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| 69 | str_address = "conv_integer(in_READ_"+toString(i)+"_ADDRESS)"; |
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| 70 | else |
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| 71 | str_address = "0"; |
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| 72 | |
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| 73 | vhdl->set_body (0,"out_READ_"+toString(i)+"_DATA <= reg_DATA ("+str_address+ |
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| 74 | ") when in_READ_"+toString(i)+"_VAL = '1' else "+ |
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| 75 | std_logic_others(_param->_size_word,0)+";"); |
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| 76 | } |
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| 77 | |
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| 78 | vhdl->set_body (0,""); |
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| 79 | vhdl->set_comment(0,"---------------------------------------------------"); |
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| 80 | vhdl->set_comment(0," Write RegisterFile"); |
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| 81 | vhdl->set_comment(0,"---------------------------------------------------"); |
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| 82 | vhdl->set_body (0,""); |
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| 83 | |
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| 84 | vhdl->set_body (0,"RegisterFile_write: process (in_CLOCK)"); |
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| 85 | vhdl->set_body (0,"begin -- process RegisterFile_write"); |
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| 86 | vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); |
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| 87 | |
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| 88 | for (uint32_t i = 0; i < _param->_nb_port_write; i++) |
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| 89 | { |
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| 90 | std::string str_address; |
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| 91 | if (_param->_have_port_address) |
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| 92 | str_address = "conv_integer(in_WRITE_"+toString(i)+"_ADDRESS)"; |
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| 93 | else |
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| 94 | str_address = "0"; |
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| 95 | |
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| 96 | vhdl->set_body (2,"if (in_WRITE_"+toString(i)+"_VAL = '1') then"); |
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| 97 | vhdl->set_body (3,"reg_DATA("+str_address+") <= in_WRITE_"+toString(i)+"_DATA;"); |
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| 98 | vhdl->set_body (2,"end if;"); |
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| 99 | } |
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| 100 | |
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| 101 | vhdl->set_body (1,"end if;"); |
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| 102 | vhdl->set_body (0,"end process RegisterFile_write;"); |
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| 103 | }; |
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| 104 | \end{lstlisting} |
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| 105 | |
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| 106 | \subsubSection{Fichier RegisterFile\_Monolithic.vhdl} |
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| 107 | |
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| 108 | \lstparam{VHDL} |
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| 109 | \begin{lstlisting}[caption={RegisterFile\_Monolithic.cpp}] |
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| 110 | library ieee; |
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| 111 | use ieee.numeric_bit.all; |
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| 112 | use ieee.numeric_std.all; |
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| 113 | use ieee.std_logic_1164.all; |
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| 114 | use ieee.std_logic_arith.all; |
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| 115 | use ieee.std_logic_misc.all; |
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| 116 | --use ieee.std_logic_signed.all; |
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| 117 | use ieee.std_logic_unsigned.all; |
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| 118 | --use ieee.std_logic_textio.all; |
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| 119 | |
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| 120 | |
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| 121 | library work; |
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| 122 | use work.RegisterFile_Monolithic_Pack.all; |
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| 123 | |
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| 124 | |
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| 125 | entity RegisterFile_Monolithic is |
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| 126 | port ( in_CLOCK : in std_logic; |
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| 127 | in_NRESET : in std_logic; |
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| 128 | in_READ_0_VAL : in std_logic; |
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| 129 | out_READ_0_ACK : out std_logic; |
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| 130 | in_READ_0_ADDRESS : in std_logic_vector(8 downto 0); |
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| 131 | out_READ_0_DATA : out std_logic_vector(31 downto 0); |
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| 132 | in_WRITE_0_VAL : in std_logic; |
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| 133 | out_WRITE_0_ACK : out std_logic; |
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| 134 | in_WRITE_0_ADDRESS: in std_logic_vector(8 downto 0); |
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| 135 | in_WRITE_0_DATA : in std_logic_vector(31 downto 0) |
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| 136 | ); |
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| 137 | end RegisterFile_Monolithic; |
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| 138 | |
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| 139 | architecture behavioural of RegisterFile_Monolithic is |
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| 140 | type Tregfile is array (511 downto 0) of std_logic_vector(31 downto 0); |
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| 141 | |
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| 142 | signal reg_DATA : Tregfile; |
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| 143 | |
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| 144 | begin |
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| 145 | ----------------------------------------------------- |
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| 146 | -- Ackitement |
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| 147 | ----------------------------------------------------- |
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| 148 | |
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| 149 | out_READ_0_ACK <= '1'; |
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| 150 | out_WRITE_0_ACK <= '1'; |
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| 151 | |
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| 152 | ----------------------------------------------------- |
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| 153 | -- Read RegisterFile |
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| 154 | ----------------------------------------------------- |
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| 155 | |
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| 156 | out_READ_0_DATA <= reg_DATA (conv_integer(in_READ_0_ADDRESS)) |
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| 157 | when in_READ_0_VAL = '1' |
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| 158 | else (others => '0'); |
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| 159 | |
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| 160 | ----------------------------------------------------- |
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| 161 | -- Write RegisterFile |
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| 162 | ----------------------------------------------------- |
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| 163 | |
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| 164 | RegisterFile_write: process (in_CLOCK) |
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| 165 | begin -- process RegisterFile_write |
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| 166 | if in_CLOCK'event and in_CLOCK = '1' then |
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| 167 | if (in_WRITE_0_VAL = '1') then |
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| 168 | reg_DATA(conv_integer(in_WRITE_0_ADDRESS)) <= in_WRITE_0_DATA; |
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| 169 | end if; |
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| 170 | end if; |
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| 171 | end process RegisterFile_write; |
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| 172 | end behavioural; |
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| 173 | \end{lstlisting} |
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