1 | %------------------------------------------------------------------------------ |
---|
2 | % $Id: document-morpheo-vhdl_generation-fr-05_01_registerfile.tex 100 2009-01-08 13:06:27Z rosiere $ |
---|
3 | %------------------------------------------------------------------------------ |
---|
4 | |
---|
5 | \subSection{Banc de Registres Monolithique} |
---|
6 | |
---|
7 | \subsubSection{Fichier RegisterFile\_Monolithic\_vhdl.cpp} |
---|
8 | |
---|
9 | \lstparam{C++} |
---|
10 | \begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl.cpp}] |
---|
11 | void RegisterFile_Monolithic::vhdl (void) |
---|
12 | { |
---|
13 | Vhdl * vhdl = new Vhdl (_name); |
---|
14 | |
---|
15 | _interfaces->set_port (vhdl); |
---|
16 | _component ->vhdl_instance(vhdl); |
---|
17 | |
---|
18 | vhdl_declaration (vhdl); |
---|
19 | vhdl_body (vhdl); |
---|
20 | |
---|
21 | vhdl->generate_file(); |
---|
22 | |
---|
23 | delete vhdl; |
---|
24 | }; |
---|
25 | \end{lstlisting} |
---|
26 | |
---|
27 | |
---|
28 | \subsubSection{Fichier RegisterFile\_Monolithic\_vhdl\_declaration.cpp} |
---|
29 | |
---|
30 | \lstparam{C++} |
---|
31 | \begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl\_declaration.cpp}] |
---|
32 | void RegisterFile_Monolithic::vhdl_declaration (Vhdl * & vhdl) |
---|
33 | { |
---|
34 | vhdl->set_type ("Tregfile", "array " + std_logic_range(_param->_nb_word,true)+ |
---|
35 | " of "+ |
---|
36 | std_logic(_param->_size_word)); |
---|
37 | |
---|
38 | vhdl->set_signal ("reg_DATA", "Tregfile"); |
---|
39 | }; |
---|
40 | \end{lstlisting} |
---|
41 | |
---|
42 | \subsubSection{Fichier RegisterFile\_Monolithic\_vhdl\_body.cpp} |
---|
43 | |
---|
44 | \lstparam{C++} |
---|
45 | \begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl\_body.cpp}] |
---|
46 | void RegisterFile_Monolithic::vhdl_body (Vhdl * & vhdl) |
---|
47 | { |
---|
48 | vhdl->set_body (0,""); |
---|
49 | vhdl->set_comment(0,"---------------------------------------------------"); |
---|
50 | vhdl->set_comment(0," Ack"); |
---|
51 | vhdl->set_comment(0,"---------------------------------------------------"); |
---|
52 | vhdl->set_body (0,""); |
---|
53 | |
---|
54 | for (uint32_t i = 0; i < _param->_nb_port_read; i++) |
---|
55 | vhdl->set_body (0,"out_READ_"+toString(i)+"_ACK <= '1';"); |
---|
56 | for (uint32_t i = 0; i < _param->_nb_port_write; i++) |
---|
57 | vhdl->set_body (0,"out_WRITE_"+toString(i)+"_ACK <= '1';"); |
---|
58 | |
---|
59 | vhdl->set_body (0,""); |
---|
60 | vhdl->set_comment(0,"---------------------------------------------------"); |
---|
61 | vhdl->set_comment(0," Read RegisterFile"); |
---|
62 | vhdl->set_comment(0,"---------------------------------------------------"); |
---|
63 | vhdl->set_body (0,""); |
---|
64 | |
---|
65 | for (uint32_t i = 0; i < _param->_nb_port_read; i++) |
---|
66 | { |
---|
67 | std::string str_address; |
---|
68 | if (_param->_have_port_address) |
---|
69 | str_address = "conv_integer(in_READ_"+toString(i)+"_ADDRESS)"; |
---|
70 | else |
---|
71 | str_address = "0"; |
---|
72 | |
---|
73 | vhdl->set_body (0,"out_READ_"+toString(i)+"_DATA <= reg_DATA ("+str_address+ |
---|
74 | ") when in_READ_"+toString(i)+"_VAL = '1' else "+ |
---|
75 | std_logic_others(_param->_size_word,0)+";"); |
---|
76 | } |
---|
77 | |
---|
78 | vhdl->set_body (0,""); |
---|
79 | vhdl->set_comment(0,"---------------------------------------------------"); |
---|
80 | vhdl->set_comment(0," Write RegisterFile"); |
---|
81 | vhdl->set_comment(0,"---------------------------------------------------"); |
---|
82 | vhdl->set_body (0,""); |
---|
83 | |
---|
84 | vhdl->set_body (0,"RegisterFile_write: process (in_CLOCK)"); |
---|
85 | vhdl->set_body (0,"begin -- process RegisterFile_write"); |
---|
86 | vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); |
---|
87 | |
---|
88 | for (uint32_t i = 0; i < _param->_nb_port_write; i++) |
---|
89 | { |
---|
90 | std::string str_address; |
---|
91 | if (_param->_have_port_address) |
---|
92 | str_address = "conv_integer(in_WRITE_"+toString(i)+"_ADDRESS)"; |
---|
93 | else |
---|
94 | str_address = "0"; |
---|
95 | |
---|
96 | vhdl->set_body (2,"if (in_WRITE_"+toString(i)+"_VAL = '1') then"); |
---|
97 | vhdl->set_body (3,"reg_DATA("+str_address+") <= in_WRITE_"+toString(i)+"_DATA;"); |
---|
98 | vhdl->set_body (2,"end if;"); |
---|
99 | } |
---|
100 | |
---|
101 | vhdl->set_body (1,"end if;"); |
---|
102 | vhdl->set_body (0,"end process RegisterFile_write;"); |
---|
103 | }; |
---|
104 | \end{lstlisting} |
---|
105 | |
---|
106 | \subsubSection{Fichier RegisterFile\_Monolithic.vhdl} |
---|
107 | |
---|
108 | \lstparam{VHDL} |
---|
109 | \begin{lstlisting}[caption={RegisterFile\_Monolithic.cpp}] |
---|
110 | library ieee; |
---|
111 | use ieee.numeric_bit.all; |
---|
112 | use ieee.numeric_std.all; |
---|
113 | use ieee.std_logic_1164.all; |
---|
114 | use ieee.std_logic_arith.all; |
---|
115 | use ieee.std_logic_misc.all; |
---|
116 | --use ieee.std_logic_signed.all; |
---|
117 | use ieee.std_logic_unsigned.all; |
---|
118 | --use ieee.std_logic_textio.all; |
---|
119 | |
---|
120 | |
---|
121 | library work; |
---|
122 | use work.RegisterFile_Monolithic_Pack.all; |
---|
123 | |
---|
124 | |
---|
125 | entity RegisterFile_Monolithic is |
---|
126 | port ( in_CLOCK : in std_logic; |
---|
127 | in_NRESET : in std_logic; |
---|
128 | in_READ_0_VAL : in std_logic; |
---|
129 | out_READ_0_ACK : out std_logic; |
---|
130 | in_READ_0_ADDRESS : in std_logic_vector(8 downto 0); |
---|
131 | out_READ_0_DATA : out std_logic_vector(31 downto 0); |
---|
132 | in_WRITE_0_VAL : in std_logic; |
---|
133 | out_WRITE_0_ACK : out std_logic; |
---|
134 | in_WRITE_0_ADDRESS: in std_logic_vector(8 downto 0); |
---|
135 | in_WRITE_0_DATA : in std_logic_vector(31 downto 0) |
---|
136 | ); |
---|
137 | end RegisterFile_Monolithic; |
---|
138 | |
---|
139 | architecture behavioural of RegisterFile_Monolithic is |
---|
140 | type Tregfile is array (511 downto 0) of std_logic_vector(31 downto 0); |
---|
141 | |
---|
142 | signal reg_DATA : Tregfile; |
---|
143 | |
---|
144 | begin |
---|
145 | ----------------------------------------------------- |
---|
146 | -- Ackitement |
---|
147 | ----------------------------------------------------- |
---|
148 | |
---|
149 | out_READ_0_ACK <= '1'; |
---|
150 | out_WRITE_0_ACK <= '1'; |
---|
151 | |
---|
152 | ----------------------------------------------------- |
---|
153 | -- Read RegisterFile |
---|
154 | ----------------------------------------------------- |
---|
155 | |
---|
156 | out_READ_0_DATA <= reg_DATA (conv_integer(in_READ_0_ADDRESS)) |
---|
157 | when in_READ_0_VAL = '1' |
---|
158 | else (others => '0'); |
---|
159 | |
---|
160 | ----------------------------------------------------- |
---|
161 | -- Write RegisterFile |
---|
162 | ----------------------------------------------------- |
---|
163 | |
---|
164 | RegisterFile_write: process (in_CLOCK) |
---|
165 | begin -- process RegisterFile_write |
---|
166 | if in_CLOCK'event and in_CLOCK = '1' then |
---|
167 | if (in_WRITE_0_VAL = '1') then |
---|
168 | reg_DATA(conv_integer(in_WRITE_0_ADDRESS)) <= in_WRITE_0_DATA; |
---|
169 | end if; |
---|
170 | end if; |
---|
171 | end process RegisterFile_write; |
---|
172 | end behavioural; |
---|
173 | \end{lstlisting} |
---|