[91] | 1 | #FIG 3.2 |
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| 2 | Landscape |
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| 3 | Center |
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| 4 | Inches |
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| 5 | Letter |
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| 6 | 100.00 |
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| 7 | Single |
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| 8 | -2 |
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| 9 | 1200 2 |
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| 10 | 6 11475 2550 13200 4200 |
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| 11 | 6 11550 3750 12750 4200 |
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| 12 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 13 | 11550 3750 12150 3750 12150 4200 11550 4200 11550 3750 |
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| 14 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 15 | 12150 3750 12750 3750 12750 4200 12150 4200 12150 3750 |
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| 16 | 4 1 0 50 -1 0 8 0.0000 0 105 375 11850 4125 request\001 |
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| 17 | 4 1 0 50 -1 0 8 0.0000 0 90 375 12450 4125 respons\001 |
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| 18 | 4 1 0 50 -1 0 8 0.0000 0 75 375 11850 3900 Dcache\001 |
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| 19 | 4 1 0 50 -1 0 8 0.0000 0 75 375 12450 3900 Dcache\001 |
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| 20 | -6 |
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| 21 | 4 0 0 50 -1 0 8 0.7854 0 75 375 12150 3600 Dcache\001 |
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| 22 | 4 0 0 50 -1 0 8 0.7854 0 120 1305 11550 3600 speculative_access_queue\001 |
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| 23 | 4 0 0 50 -1 0 8 0.7854 0 105 570 12750 3600 load_queue\001 |
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| 24 | -6 |
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| 25 | 6 6450 3375 8025 4200 |
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| 26 | 2 2 0 0 0 4 55 -1 20 1.500 0 0 -1 0 0 5 |
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| 27 | 6450 3975 6750 3975 6750 4125 6450 4125 6450 3975 |
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| 28 | 2 2 0 0 0 13 55 -1 20 1.500 0 0 -1 0 0 5 |
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| 29 | 6450 3375 6750 3375 6750 3525 6450 3525 6450 3375 |
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| 30 | 2 2 0 0 0 17 55 -1 20 1.500 0 0 -1 0 0 5 |
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| 31 | 6450 3675 6750 3675 6750 3825 6450 3825 6450 3675 |
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| 32 | 4 0 0 55 -1 0 8 0.0000 0 75 510 6900 3525 Front End\001 |
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| 33 | 4 0 0 55 -1 0 8 0.0000 0 105 1065 6900 3825 Out Of Order Engine\001 |
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| 34 | 4 0 0 55 -1 0 8 0.0000 0 105 720 6900 4125 Execute Loop\001 |
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| 35 | -6 |
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| 36 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 37 | 7050 4800 7650 4800 7650 5250 7050 5250 7050 4800 |
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| 38 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 39 | 6450 4800 7050 4800 7050 5250 6450 5250 6450 4800 |
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| 40 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 41 | 7650 4800 8250 4800 8250 5250 7650 5250 7650 4800 |
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| 42 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 43 | 8250 4800 8850 4800 8850 5250 8250 5250 8250 4800 |
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| 44 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 45 | 8850 4800 9450 4800 9450 5250 8850 5250 8850 4800 |
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| 46 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 47 | 9450 4800 10050 4800 10050 5250 9450 5250 9450 4800 |
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| 48 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 49 | 10050 4800 10650 4800 10650 5250 10050 5250 10050 4800 |
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| 50 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 51 | 10650 4800 11250 4800 11250 5250 10650 5250 10650 4800 |
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| 52 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 53 | 11250 4800 11850 4800 11850 5250 11250 5250 11250 4800 |
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| 54 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 55 | 11850 4800 12450 4800 12450 5250 11850 5250 11850 4800 |
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| 56 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 57 | 12450 4800 13050 4800 13050 5250 12450 5250 12450 4800 |
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| 58 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 59 | 13050 4800 13650 4800 13650 5250 13050 5250 13050 4800 |
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| 60 | 2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 |
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| 61 | 13650 4800 14250 4800 14250 5250 13650 5250 13650 4800 |
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| 62 | 2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2 |
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| 63 | 11850 4800 11550 4200 |
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| 64 | 2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2 |
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| 65 | 12450 4800 12750 4200 |
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| 66 | 2 2 0 1 0 13 55 -1 20 3.000 0 0 -1 0 0 5 |
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| 67 | 6450 4800 9450 4800 9450 5250 6450 5250 6450 4800 |
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| 68 | 2 2 0 1 0 17 55 -1 20 3.000 0 0 -1 0 0 5 |
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| 69 | 9450 4800 10650 4800 10650 5250 9450 5250 9450 4800 |
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| 70 | 2 2 0 0 0 4 55 -1 20 1.500 0 0 -1 0 0 5 |
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| 71 | 12750 4200 11550 4200 11550 3750 12750 3750 12750 4200 |
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| 72 | 2 2 0 0 0 17 55 -1 20 1.500 0 0 -1 0 0 5 |
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| 73 | 13050 4800 13650 4800 13650 5250 13050 5250 13050 4800 |
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| 74 | 2 2 0 0 0 4 55 -1 20 1.500 0 0 -1 0 0 5 |
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| 75 | 12750 4200 11550 4200 11550 3750 12750 3750 12750 4200 |
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| 76 | 2 2 0 0 0 4 55 -1 20 1.500 0 0 -1 0 0 5 |
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| 77 | 10650 5250 13050 5250 13050 4800 10650 4800 10650 5250 |
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| 78 | 2 2 0 0 0 13 55 -1 20 1.500 0 0 -1 0 0 5 |
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| 79 | 13650 4950 14250 4950 14250 4800 13650 4800 13650 4950 |
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| 80 | 2 2 0 0 0 17 55 -1 20 1.500 0 0 -1 0 0 5 |
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| 81 | 13650 4950 14250 4950 14250 5100 13650 5100 13650 4950 |
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| 82 | 2 2 0 0 0 4 55 -1 20 1.500 0 0 -1 0 0 5 |
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| 83 | 13650 5250 14250 5250 14250 5100 13650 5100 13650 5250 |
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| 84 | 4 0 0 50 -1 0 8 5.4978 0 75 330 8250 5400 Icache\001 |
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| 85 | 4 0 0 50 -1 0 8 5.4978 0 90 765 6450 5400 PC_next_next\001 |
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| 86 | 4 0 0 50 -1 0 8 5.4978 0 75 165 7650 5400 PC\001 |
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| 87 | 4 0 0 50 -1 0 8 5.4978 0 90 465 7050 5400 PC_next\001 |
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| 88 | 4 0 0 50 -1 0 8 5.4978 0 105 675 8850 5400 Ifetch_queue\001 |
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| 89 | 4 0 0 50 -1 0 8 5.4978 0 105 690 9450 5400 Decod_queue\001 |
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| 90 | 4 0 0 50 -1 0 8 5.4978 0 105 675 10050 5400 Issue_queuec\001 |
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| 91 | 4 0 0 50 -1 0 8 5.4978 0 105 615 10650 5400 Read_queue\001 |
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| 92 | 4 0 0 50 -1 0 8 5.4978 0 105 990 11250 5400 Reservation_station\001 |
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| 93 | 4 0 0 50 -1 0 8 5.4978 0 105 555 12450 5400 Write_unit\001 |
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| 94 | 4 0 0 50 -1 0 8 5.4978 0 105 690 13050 5400 Execute_unit\001 |
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| 95 | 4 0 0 50 -1 0 8 5.4978 0 90 900 13650 5400 Re_Order_Buffer\001 |
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| 96 | 4 1 0 50 -1 0 8 0.0000 0 75 60 6750 4650 1\001 |
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| 97 | 4 1 0 50 -1 0 8 0.0000 0 75 60 7350 4650 2\001 |
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| 98 | 4 1 0 50 -1 0 8 0.0000 0 75 60 7950 4650 3\001 |
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| 99 | 4 1 0 50 -1 0 8 0.0000 0 75 60 8550 4650 4\001 |
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| 100 | 4 1 0 50 -1 0 8 0.0000 0 75 60 9150 4650 5\001 |
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| 101 | 4 1 0 50 -1 0 8 0.0000 0 75 60 9750 4650 6\001 |
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| 102 | 4 1 0 50 -1 0 8 0.0000 0 75 60 10350 4650 7\001 |
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| 103 | 4 1 0 50 -1 0 8 0.0000 0 75 60 10950 4650 8\001 |
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| 104 | 4 1 0 50 -1 0 8 0.0000 0 75 60 11550 4650 9\001 |
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| 105 | 4 1 0 50 -1 0 8 0.0000 0 75 120 12150 4650 10\001 |
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| 106 | 4 1 0 50 -1 0 8 0.0000 0 75 120 12750 4650 11\001 |
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| 107 | 4 1 0 50 -1 0 8 0.0000 0 75 120 13350 4650 12\001 |
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| 108 | 4 1 0 50 -1 0 8 0.0000 0 75 120 13950 4650 13\001 |
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| 109 | 4 1 0 50 -1 0 8 0.0000 0 75 330 7950 4950 Icache\001 |
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| 110 | 4 1 0 50 -1 0 8 0.0000 0 75 330 8550 4950 Icache\001 |
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| 111 | 4 1 0 50 -1 0 8 0.0000 0 75 330 9150 5025 Decod\001 |
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| 112 | 4 1 0 50 -1 0 8 0.0000 0 75 405 9750 5025 Rename\001 |
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| 113 | 4 1 0 50 -1 0 8 0.0000 0 75 255 10350 5025 Issue\001 |
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| 114 | 4 1 0 50 -1 0 8 0.0000 0 75 255 10950 4950 Read\001 |
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| 115 | 4 1 0 50 -1 0 8 0.0000 0 120 435 11550 5025 Dispatch\001 |
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| 116 | 4 1 0 50 -1 0 8 0.0000 0 75 435 12150 5025 Execute\001 |
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| 117 | 4 1 0 50 -1 0 8 0.0000 0 90 300 12750 4950 Write\001 |
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| 118 | 4 1 0 50 -1 0 8 0.0000 0 90 405 13350 5025 Commit\001 |
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| 119 | 4 1 0 50 -1 0 8 0.0000 0 105 360 13950 5025 Update\001 |
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| 120 | 4 1 0 50 -1 0 8 0.0000 0 105 375 7950 5175 request\001 |
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| 121 | 4 1 0 50 -1 0 8 0.0000 0 90 375 8550 5175 respons\001 |
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| 122 | 4 1 0 50 -1 0 8 0.0000 0 105 435 10950 5175 Register\001 |
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| 123 | 4 1 0 50 -1 0 8 0.0000 0 105 435 12750 5175 Register\001 |
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| 124 | 4 2 0 50 -1 0 8 0.0000 0 90 780 11250 4050 instruction load\001 |
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| 125 | 4 1 0 50 -1 0 8 0.0000 0 90 525 7350 5025 Prediction\001 |
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| 126 | 4 1 0 50 -1 0 8 0.0000 0 90 240 6750 5025 Wait\001 |
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