Last change
on this file since 91 was
88,
checked in by rosiere, 16 years ago
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Almost complete design
with Test and test platform
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-
Property svn:keywords set to
Id
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File size:
2.0 KB
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1 | # |
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2 | # $Id: Makefile.flags 88 2008-12-10 18:31:39Z rosiere $ |
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3 | # |
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4 | # [ Description ] |
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5 | # |
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6 | |
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7 | #-----[ Simulator ]---------------------------------------- |
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8 | SIMULATOR = systemcass |
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9 | |
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10 | # 3 simulators : |
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11 | # systemc - SystemC |
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12 | # systemcass - SystemCASS |
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13 | # systemcass_deps - Systemcass, and use port dependency information instead of sensitivity list |
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14 | |
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15 | #-----[ Flags ]-------------------------------------------- |
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16 | MORPHEO_FLAGS = -DSYSTEMC \ |
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17 | -DDEBUG=DEBUG_TRACE \ |
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18 | -DSTATISTICS \ |
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19 | -DVHDL \ |
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20 | -DVHDL_TESTBENCH \ |
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21 | -DVHDL_TESTBENCH_ASSERT \ |
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22 | -DTRANSLATION |
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23 | |
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24 | # -DPRINT_COLOR \ |
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25 | # -DLOG_FILE \ |
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26 | # -DPOSITION \ |
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27 | # -DREGISTER_INIT \ |
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28 | |
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29 | # Flags : |
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30 | # DEBUG={level} - Print Debug Message |
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31 | # LOG_FILE - Print Message in a log file |
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32 | # SYSTEMC - To generate a systemc's model |
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33 | # VHDL - To generate a vhdl's models |
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34 | # VHDL_TESTBENCH (need SYSTEMC) - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model |
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35 | # VHDL_TESTBENCH_ASSERT (need VHDL_TESTBENCH) - In the simulation, generate in testbench's file an serie of assert |
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36 | # POSITION - To generate a position's files (it's input of viewer) |
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37 | # STATISTICS (need SYSTEMC) - In the simulation, generate a statistics's file |
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38 | # INFORMATION (need STATISTICS) - Instance Information : |
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39 | # * Static : at the instance creation |
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40 | # * register number |
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41 | # * worst way |
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42 | # * Dynamique : at the runtime |
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43 | # * consomation |
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44 | # TRANSLATION - Translate message |
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45 | # REGISTER_INIT - Init a lot of register |
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46 | # PRINT_COLOR - Print with colors |
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