[2] | 1 | #include <stdio.h> |
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| 2 | #include <stdarg.h> |
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| 3 | #include <stdlib.h> |
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| 4 | #include <signal.h> |
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| 5 | #include <sys/time.h> |
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| 6 | #include <libgen.h> |
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| 7 | #include <systemc.h> |
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| 8 | #include <cmath> |
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| 9 | |
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| 10 | /********************************************************************* |
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| 11 | * Inclusion des modèles |
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| 12 | *********************************************************************/ |
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| 13 | #include "shared/macro.h" |
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| 14 | #include "shared/soclib_caches_interfaces.h" |
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| 15 | #include "shared/soclib_segment_table.h" |
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| 16 | #include "shared/mapping_memory.h" |
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| 17 | /********************************************************************* |
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| 18 | * Inclusion et parametrage du processeur |
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| 19 | *********************************************************************/ |
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| 20 | #include "m_cpu_configuration.h" |
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| 21 | #include "processor/M_CPU/Configuration/m_cpu_configuration.h" |
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| 22 | #include "processor/M_CPU/M_CPU.h" |
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| 23 | |
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| 24 | #include "hierarchy_memory/hierarchy_memory.h" |
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| 25 | |
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| 26 | using namespace hierarchy_memory; |
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| 27 | using namespace std; |
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| 28 | /********************************************************************* |
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| 29 | * Définitions des paramètres des composants |
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| 30 | *********************************************************************/ |
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| 31 | |
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| 32 | #define WITH_XTTY false |
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| 33 | #define NB_CONTEXT (M_CPU_NB_CLUSTER * M_CPU_NB_UL * M_CPU_NB_THREAD) |
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| 34 | |
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| 35 | // Parametre du CPU dans un fichier externe |
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| 36 | #define ICACHE_TEMPLATE LOG2_M_CPU_NB_CLUSTER + LOG2_M_CPU_NB_UL + LOG2_M_CPU_NB_THREAD+1, (LOG2_M_CPU_SIZE_IFETCH_QUEUE)+1 , M_CPU_SIZE_ADDR_INST, M_CPU_SIZE_INST,M_CPU_NB_INST_FETCH |
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| 37 | #define DCACHE_TEMPLATE LOG2_M_CPU_NB_CLUSTER + LOG2_M_CPU_NB_UL + LOG2_M_CPU_NB_THREAD+1, (LOG2_M_CPU_SIZE_LOAD_STORE_QUEUE)+1, M_CPU_SIZE_ADDR_DATA, M_CPU_SIZE_DATA |
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| 38 | |
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| 39 | //#define OFFSET_NB_LINE (power2(NB_CONTEXT)/power2(M_CPU_NB_CLUSTER)) |
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| 40 | #define OFFSET_NB_LINE 1 |
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| 41 | |
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| 42 | // nb_line, size_line, size_word, associativity, hit_latence, miss_penality |
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| 43 | #define L1_ICACHE "L1_ICACHE",(128*OFFSET_NB_LINE), 16, 4, 4, 2, 4 |
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| 44 | #define L1_DCACHE "L1_DCACHE",(128*OFFSET_NB_LINE), 16, 4, 4, 2, 4 |
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| 45 | #define L2_CACHE "L2_CACHE" , 16384, 32, 4, 8, 6, 100 |
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| 46 | |
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| 47 | #define NB_IPORT 1 |
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| 48 | #define NB_DPORT M_CPU_NB_DATA_ACCESS |
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| 49 | |
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| 50 | #define SIZE_BUFFER_IRSP 4 |
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| 51 | #define SIZE_BUFFER_DRSP 4 |
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| 52 | |
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| 53 | #define HIERARCHY_MEMORY_TEMPLATE LOG2_M_CPU_NB_CLUSTER + LOG2_M_CPU_NB_UL + LOG2_M_CPU_NB_THREAD+1, (LOG2_M_CPU_SIZE_IFETCH_QUEUE)+1 , M_CPU_SIZE_ADDR_INST, M_CPU_SIZE_INST,M_CPU_NB_INST_FETCH, (LOG2_M_CPU_SIZE_LOAD_STORE_QUEUE)+1, M_CPU_SIZE_ADDR_DATA, M_CPU_SIZE_DATA |
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| 54 | #define MAPPING_TABLE_CLUSTER_TEMPLATE LOG2_M_CPU_NB_UL, M_CPU_NB_UL, LOG2_M_CPU_NB_INST_SELECT, M_CPU_NB_INST_SELECT |
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| 55 | #define MAPPING_TABLE_UE_TEMPLATE LOG2_M_CPU_NB_CLUSTER, M_CPU_NB_CLUSTER, LOG2_M_CPU_NB_INST_SELECT, M_CPU_NB_INST_SELECT |
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| 56 | #define MAPPING_TABLE_DISPATCH_TEMPLATE LOG2_M_CPU_NB_INST_SELECT, M_CPU_NB_INST_SELECT, LOG2_M_CPU_NB_UE, M_CPU_NB_UE |
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| 57 | #define TYPE_TABLE_INST_L_TEMPLATE LOG2_NB_INST_L, NB_INST_L |
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| 58 | |
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| 59 | |
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| 60 | /********************************************************************* |
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| 61 | * Variable global |
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| 62 | *********************************************************************/ |
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| 63 | timeval time_begin; |
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| 64 | timeval time_end; |
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| 65 | unsigned int nb_cycles_simulated = 0; |
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| 66 | |
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| 67 | /******************************************************** |
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| 68 | * Déclarations des composants |
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| 69 | ********************************************************/ |
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| 70 | |
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| 71 | UE_CONFIGURATION ** ue_configuration; |
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| 72 | MAPPING_TABLE <MAPPING_TABLE_CLUSTER_TEMPLATE> ** mapping_table_cluster; |
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| 73 | MAPPING_TABLE <MAPPING_TABLE_UE_TEMPLATE> * mapping_table_ue; |
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| 74 | MAPPING_TABLE <MAPPING_TABLE_DISPATCH_TEMPLATE> * mapping_table_dispatch; |
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| 75 | |
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| 76 | TYPE_TABLE <TYPE_TABLE_INST_L_TEMPLATE> * type_table_inst_l; |
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| 77 | |
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| 78 | HIERARCHY_MEMORY<HIERARCHY_MEMORY_TEMPLATE> * memory; |
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| 79 | M_CPU <M_CPU_CONFIGURATION> * m_cpu; |
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| 80 | |
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| 81 | /********************************************************************* |
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| 82 | * print_time |
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| 83 | *********************************************************************/ |
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| 84 | void print_time (timeval time_begin, timeval time_end, unsigned int nb_cycles_simulated, unsigned int nb_cycles_current) |
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| 85 | { |
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| 86 | double average = (double)(nb_cycles_simulated) / (double)(time_end.tv_sec-time_begin.tv_sec); |
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| 87 | |
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| 88 | cout << nb_cycles_current << "\t(" << average << " cycles / seconds )" << endl; |
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| 89 | } |
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| 90 | |
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| 91 | /********************************************************************* |
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| 92 | * clean_exit |
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| 93 | *********************************************************************/ |
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| 94 | void clean_exit () |
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| 95 | { |
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| 96 | sc_stop(); |
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| 97 | |
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| 98 | gettimeofday(&time_end ,NULL); |
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| 99 | print_time(time_begin,time_end,(unsigned int)sc_simulation_time()-nb_cycles_simulated,(unsigned int)sc_simulation_time()); |
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| 100 | |
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| 101 | delete memory; |
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| 102 | |
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| 103 | for (unsigned int i = 0; i < M_CPU_NB_CLUSTER; i ++) |
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| 104 | delete mapping_table_cluster[i]; |
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| 105 | for (unsigned int i = 0; i < M_CPU_NB_UE; i ++) |
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| 106 | delete ue_configuration[i]; |
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| 107 | |
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| 108 | delete mapping_table_ue; |
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| 109 | delete mapping_table_dispatch; |
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| 110 | delete type_table_inst_l; |
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| 111 | |
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| 112 | delete m_cpu; |
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| 113 | } |
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| 114 | |
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| 115 | /********************************************************************* |
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| 116 | * handler_signal |
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| 117 | *********************************************************************/ |
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| 118 | void handler_signal(int signum) |
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| 119 | { |
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| 120 | switch (signum) |
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| 121 | { |
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| 122 | case SIGTERM : |
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| 123 | case SIGINT : |
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| 124 | { |
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| 125 | perror("Stop of simulation\n"); |
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| 126 | clean_exit(); |
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| 127 | exit(2); |
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| 128 | break; |
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| 129 | } |
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| 130 | default : |
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| 131 | { |
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| 132 | break; |
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| 133 | } |
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| 134 | }//end switch signum |
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| 135 | } |
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| 136 | |
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| 137 | /********************************************************************* |
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| 138 | * simulation |
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| 139 | *********************************************************************/ |
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| 140 | unsigned int simulation () |
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| 141 | { |
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| 142 | // Test if can continue the simulation (all thread have not send the stop signal) |
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| 143 | if (memory->stop() == true) |
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| 144 | return 0; |
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| 145 | |
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| 146 | cout << "How many cycle to simulate ? (0 to stop the simulation)" << endl; |
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| 147 | |
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| 148 | int nb_cycle; |
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| 149 | cin >> nb_cycle; |
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| 150 | |
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| 151 | cout << " ... again " << nb_cycle << " cycles" << endl; |
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| 152 | return nb_cycle; |
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| 153 | } |
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| 154 | |
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| 155 | /********************************************************************* |
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| 156 | * power2 |
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| 157 | *********************************************************************/ |
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| 158 | // return the Y=2^n with 2^(n-1) < X <= 2^n |
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| 159 | // Warning : possible bug if X > 0x80000000 |
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| 160 | uint32_t power2 (uint32_t x) |
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| 161 | { |
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| 162 | uint32_t mask; |
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| 163 | |
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| 164 | for (mask = 1; mask < x; mask <<= 1); |
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| 165 | |
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| 166 | return mask; |
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| 167 | } |
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| 168 | |
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| 169 | /********************************************************************* |
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| 170 | * usage |
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| 171 | *********************************************************************/ |
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| 172 | |
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| 173 | void usage(char * name_fct) |
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| 174 | { |
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| 175 | cerr << "usage : " << name_fct << " filename [nb_cycle]" << endl; |
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| 176 | cerr << " * filename : name of binary" << endl; |
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| 177 | cerr << " * nb_cycle : number of cycle to simulate" << endl; |
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| 178 | exit(1); |
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| 179 | } |
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| 180 | |
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| 181 | /********************************************************************* |
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| 182 | * sc_main |
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| 183 | *********************************************************************/ |
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| 184 | |
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| 185 | int sc_main(int argc, char* argv[]) |
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| 186 | { |
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| 187 | // Trap signal |
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| 188 | signal(SIGTERM, handler_signal); |
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| 189 | signal(SIGINT , handler_signal); |
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| 190 | |
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| 191 | if ( (argc != 2) && |
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| 192 | (argc != 3)) |
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| 193 | usage(argv[0]); |
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| 194 | |
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| 195 | unsigned int nb_cycles = 0; |
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| 196 | bool nb_cycles_define = false; |
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| 197 | const char * filename = argv[1]; |
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| 198 | |
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| 199 | if (argc >= 3) |
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| 200 | { |
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| 201 | nb_cycles_define = true; |
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| 202 | nb_cycles = atoi(argv[2]); |
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| 203 | } |
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| 204 | |
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| 205 | /********************************************************************* |
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| 206 | * Déclarations des variables pour la simulation |
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| 207 | *********************************************************************/ |
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| 208 | |
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| 209 | /********************************************************************* |
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| 210 | * Déclarations des signaux |
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| 211 | *********************************************************************/ |
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| 212 | sc_clock CLK ("clock",1,0.5); |
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| 213 | sc_signal<bool> NRESET; |
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| 214 | |
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| 215 | ICACHE_SIGNALS <ICACHE_TEMPLATE> ** icache_signals; |
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| 216 | DCACHE_SIGNALS <DCACHE_TEMPLATE> ** dcache_signals; |
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| 217 | |
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| 218 | /******************************************************** |
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| 219 | * Segment table |
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| 220 | ********************************************************/ |
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| 221 | |
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| 222 | log_printf(INFO,"<sc_main> Table des segments\n"); |
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| 223 | SOCLIB_SEGMENT_TABLE segtable; |
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| 224 | segtable.setMSBNumber (8); |
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| 225 | segtable.setDefaultTarget(0,0); |
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| 226 | |
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| 227 | //shared data segment |
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| 228 | |
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| 229 | // Add a segment :name , address of base , size , global index , local index, uncache |
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| 230 | segtable.addSegment("text" , TEXT_BASE , TEXT_SIZE , 0 ,0 , false); |
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| 231 | segtable.addSegment("data" , DATA_CACHED_BASE , DATA_CACHED_SIZE , 0 ,0 , false); |
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| 232 | segtable.addSegment("data_unc" , DATA_UNCACHED_BASE , DATA_UNCACHED_SIZE , 0 ,0 , true ); |
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| 233 | segtable.addSegment("stack" , STACK_BASE , STACK_SIZE , 0 ,0 , false); |
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| 234 | segtable.addSegment("tty" , TTY_BASE , TTY_SIZE , 0 ,0 , true ); |
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| 235 | segtable.addSegment("sim2os" , SIM2OS_BASE , SIM2OS_SIZE , 0 ,0 , true ); |
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| 236 | segtable.addSegment("ramlock" , RAMLOCK_BASE , RAMLOCK_SIZE , 0 ,0 , true ); |
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| 237 | |
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| 238 | /******************************************************** |
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| 239 | * Déclaration des signaux |
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| 240 | ********************************************************/ |
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| 241 | log_printf(INFO,"<sc_main> Déclaration des signaux\n"); |
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| 242 | icache_signals = new ICACHE_SIGNALS <ICACHE_TEMPLATE> * [M_CPU_NB_CLUSTER]; |
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| 243 | dcache_signals = new DCACHE_SIGNALS <DCACHE_TEMPLATE> * [M_CPU_NB_CLUSTER]; |
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| 244 | |
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| 245 | |
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| 246 | for (unsigned int it_m_cpu_nb_cluster = 0; it_m_cpu_nb_cluster < M_CPU_NB_CLUSTER; it_m_cpu_nb_cluster ++) |
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| 247 | { |
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| 248 | icache_signals [it_m_cpu_nb_cluster] = new ICACHE_SIGNALS <ICACHE_TEMPLATE> [NB_IPORT]; |
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| 249 | dcache_signals [it_m_cpu_nb_cluster] = new DCACHE_SIGNALS <DCACHE_TEMPLATE> [NB_DPORT]; |
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| 250 | } |
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| 251 | |
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| 252 | /******************************************************** |
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| 253 | * Déclaration des composants |
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| 254 | ********************************************************/ |
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| 255 | |
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| 256 | log_printf(INFO,"<sc_main> Déclaration des composants\n"); |
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| 257 | |
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| 258 | // UE_CONFIGURATION |
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| 259 | |
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| 260 | ue_configuration = new UE_CONFIGURATION * [M_CPU_NB_UE]; |
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| 261 | for (unsigned int i = 0; i < M_CPU_NB_UE; i ++) |
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| 262 | { |
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| 263 | std::ostringstream name_ue_configuration; |
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| 264 | name_ue_configuration << "ue_configuration[" << i << "]"; |
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| 265 | ue_configuration[i] = new UE_CONFIGURATION (name_ue_configuration.str().c_str()); |
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| 266 | } |
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| 267 | |
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| 268 | // MAPPING_TABLE (CLUSTER) |
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| 269 | |
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| 270 | mapping_table_cluster = new MAPPING_TABLE <MAPPING_TABLE_CLUSTER_TEMPLATE> * [M_CPU_NB_CLUSTER]; |
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| 271 | for (unsigned int i = 0; i < (M_CPU_NB_CLUSTER); i ++) |
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| 272 | { |
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| 273 | std::ostringstream name_mapping_table_cluster; |
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| 274 | name_mapping_table_cluster << "mapping_table_cluster[" << i << "]"; |
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| 275 | mapping_table_cluster[i] = new MAPPING_TABLE <MAPPING_TABLE_CLUSTER_TEMPLATE> (name_mapping_table_cluster.str().c_str()); |
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| 276 | } |
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| 277 | |
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| 278 | // MAPPING_TABLE (UE) |
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| 279 | std::ostringstream name_mapping_table_ue; |
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| 280 | name_mapping_table_ue << "mapping_table_ue"; |
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| 281 | mapping_table_ue = new MAPPING_TABLE <MAPPING_TABLE_UE_TEMPLATE> (name_mapping_table_ue.str().c_str()); |
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| 282 | |
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| 283 | // MAPPING_TABLE (DISPATCH) |
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| 284 | std::ostringstream name_mapping_table_dispatch; |
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| 285 | name_mapping_table_dispatch << "mapping_table_dispatch"; |
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| 286 | mapping_table_dispatch = new MAPPING_TABLE <MAPPING_TABLE_DISPATCH_TEMPLATE> (name_mapping_table_dispatch.str().c_str()); |
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| 287 | |
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| 288 | std::ostringstream name_type_table_inst_l; |
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| 289 | name_type_table_inst_l << "type_table_inst_l"; |
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| 290 | |
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| 291 | type_table_inst_l = new TYPE_TABLE <TYPE_TABLE_INST_L_TEMPLATE> (name_type_table_inst_l.str().c_str()); |
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| 292 | |
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| 293 | // initialisation of internal structure |
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| 294 | ini_ue_configuration (ue_configuration); |
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| 295 | ini_mapping_table_cluster (mapping_table_cluster); |
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| 296 | ini_mapping_table_ue (mapping_table_ue); |
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| 297 | ini_mapping_table_dispatch (mapping_table_dispatch); |
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| 298 | ini_type_table_inst_l (type_table_inst_l); |
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| 299 | |
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| 300 | // ----- SYSTEM MEMORY ----- |
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| 301 | |
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| 302 | char * name_tty [NB_CONTEXT]; |
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| 303 | |
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| 304 | for (uint32_t num_context = 0; num_context < NB_CONTEXT; num_context ++) |
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| 305 | { |
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| 306 | std::ostringstream name_one_tty; |
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| 307 | name_one_tty << "tty_" << num_context; |
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| 308 | |
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| 309 | unsigned int size_name = strlen(name_one_tty.str().c_str())+1; |
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| 310 | name_tty [num_context] = new char [size_name]; |
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| 311 | strncpy(name_tty [num_context],name_one_tty.str().c_str(),size_name); |
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| 312 | } |
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| 313 | |
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| 314 | param_entity_t<tty::param_t> param_tty [1] = {param_entity_t<tty::param_t> (TTY_BASE , TTY_SIZE , tty::param_t ("tty" , NB_CONTEXT, name_tty,WITH_XTTY))}; |
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| 315 | param_entity_t<ramlock::param_t> param_ramlock [1] = {param_entity_t<ramlock::param_t> (RAMLOCK_BASE, RAMLOCK_SIZE, ramlock::param_t("ramlock", RAMLOCK_SIZE))}; |
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| 316 | param_entity_t<sim2os::param_t> param_sim2os = param_entity_t<sim2os::param_t> (SIM2OS_BASE, SIM2OS_SIZE, sim2os::param_t("sim2os",&segtable)); |
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| 317 | |
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| 318 | param_cache_t param_icache [1] = { param_cache_t (L1_ICACHE) }; |
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| 319 | param_cache_t param_dcache [1] = { param_cache_t (L1_DCACHE) }; |
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| 320 | param_cache_t param_scache [1] = { param_cache_t (L2_CACHE)}; |
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| 321 | |
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| 322 | cache::cache_multilevel::param_t param_icache_dedicated [M_CPU_NB_CLUSTER]; |
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| 323 | cache::cache_multilevel::param_t param_dcache_dedicated [M_CPU_NB_CLUSTER]; |
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| 324 | |
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| 325 | for (uint32_t num_cluster = 0; num_cluster < M_CPU_NB_CLUSTER; num_cluster ++) |
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| 326 | { |
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| 327 | std::ostringstream name_icache_dedicated; |
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| 328 | name_icache_dedicated << "icache_dedicated[" << num_cluster << "]"; |
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| 329 | |
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| 330 | param_icache_dedicated [num_cluster] = cache::cache_multilevel::param_t (name_icache_dedicated.str().c_str(),1, NB_IPORT, param_icache); |
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| 331 | |
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| 332 | std::ostringstream name_dcache_dedicated; |
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| 333 | name_dcache_dedicated << "dcache_dedicated[" << num_cluster << "]"; |
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| 334 | param_dcache_dedicated [num_cluster] = cache::cache_multilevel::param_t (name_dcache_dedicated.str().c_str(),1, NB_DPORT, param_dcache); |
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| 335 | } |
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| 336 | |
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| 337 | cache::cache_multilevel::param_t param_cache_shared ("param_cache_shared",1, M_CPU_NB_CLUSTER*(NB_IPORT+NB_DPORT), param_scache); |
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| 338 | |
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| 339 | cache::param_t param_cache ("cache" , |
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| 340 | M_CPU_NB_CLUSTER , |
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| 341 | param_icache_dedicated, |
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| 342 | param_dcache_dedicated, |
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| 343 | param_cache_shared ); |
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| 344 | |
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| 345 | std::ostringstream name_memory; |
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| 346 | name_memory << basename(argv[0]) << "_memory"; |
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| 347 | memory = new HIERARCHY_MEMORY <HIERARCHY_MEMORY_TEMPLATE> (name_memory.str().c_str() , |
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| 348 | 0 , |
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| 349 | 0 , |
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| 350 | &segtable , |
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| 351 | M_CPU_NB_CLUSTER, |
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| 352 | NB_CONTEXT , |
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| 353 | SIZE_BUFFER_IRSP, |
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| 354 | SIZE_BUFFER_DRSP, |
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| 355 | hierarchy_memory::param_t(1,param_tty, |
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| 356 | 1,param_ramlock, |
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| 357 | param_sim2os, |
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| 358 | param_cache) |
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| 359 | ); |
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| 360 | |
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| 361 | std::ostringstream name_m_cpu; |
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| 362 | name_m_cpu << basename(argv[0]) << "_m_cpu"; |
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| 363 | m_cpu = new M_CPU <M_CPU_CONFIGURATION> (name_m_cpu.str().c_str() , |
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| 364 | ue_configuration , |
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| 365 | mapping_table_cluster , |
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| 366 | mapping_table_ue , |
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| 367 | mapping_table_dispatch , |
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| 368 | type_table_inst_l , |
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| 369 | M_CPU_PARAMETER_USE |
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| 370 | ); |
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| 371 | ////////////////////////////////////////////////////////// |
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| 372 | // Segments Initialisation |
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| 373 | ////////////////////////////////////////////////////////// |
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| 374 | |
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| 375 | log_printf(INFO,"<sc_main> Table des segments : initialisation\n"); |
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| 376 | |
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| 377 | const char *sections_text [] = {".text",NULL}; |
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| 378 | const char *sections_data [] = {".data",".rodata",".bss",".sdata",".sbss", NULL}; |
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| 379 | const char *sections_stack [] = {".stack",NULL}; |
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| 380 | |
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| 381 | memory->init("text" , filename, sections_text); |
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| 382 | memory->init("stack" , filename, sections_stack); |
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| 383 | memory->init("data" , filename, sections_data); |
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| 384 | |
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| 385 | segtable.print(); |
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| 386 | |
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| 387 | /******************************************************** |
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| 388 | * Instanciation |
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| 389 | ********************************************************/ |
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| 390 | |
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| 391 | log_printf(INFO,"<sc_main> Instanciation des composants\n"); |
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| 392 | |
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| 393 | log_printf(INFO,"<sc_main> Instanciation de l'élément \"memory\"\n"); |
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| 394 | memory->CLK (CLK); |
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| 395 | memory->NRESET (NRESET); |
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| 396 | |
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| 397 | for (uint32_t x = 0; x < M_CPU_NB_CLUSTER; x ++) |
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| 398 | { |
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| 399 | for (uint32_t y = 0; y < NB_IPORT; y ++) |
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| 400 | memory->ICACHE[x][y] (icache_signals [x][y]); |
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| 401 | for (uint32_t y = 0; y < NB_DPORT; y ++) |
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| 402 | memory->DCACHE[x][y] (dcache_signals [x][y]); |
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| 403 | } |
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| 404 | |
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| 405 | log_printf(INFO,"<sc_main> Instanciation de l'élément \"m_cpu\"\n"); |
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| 406 | m_cpu->CLK (CLK); |
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| 407 | m_cpu->NRESET (NRESET); |
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| 408 | for (unsigned int it_m_cpu_nb_cluster = 0; it_m_cpu_nb_cluster < M_CPU_NB_CLUSTER; it_m_cpu_nb_cluster++) |
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| 409 | { |
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| 410 | m_cpu->ICACHE[it_m_cpu_nb_cluster] (icache_signals[it_m_cpu_nb_cluster][0]); |
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| 411 | |
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| 412 | for (unsigned int it_nb_dport = 0; it_nb_dport < NB_DPORT; it_nb_dport++) |
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| 413 | m_cpu->DCACHE[it_m_cpu_nb_cluster][it_nb_dport] (dcache_signals[it_m_cpu_nb_cluster][it_nb_dport]); |
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| 414 | }//end it_m_cpu_nb_cluster |
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| 415 | |
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| 416 | log_printf(NONE,"<sc_main> Successful Instanciation\n"); |
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| 417 | |
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| 418 | /******************************************************** |
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| 419 | * Simulation - Begin |
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| 420 | ********************************************************/ |
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| 421 | |
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| 422 | // Initialisation |
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| 423 | sc_start(0); |
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| 424 | |
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| 425 | // Reset |
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| 426 | NRESET.write(false); |
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| 427 | sc_start(5); |
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| 428 | NRESET.write(true); |
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| 429 | |
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| 430 | // Lunch the simulation |
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| 431 | cout << "\n<" << argv[0] << "> Simulation : Begin\n\n" << endl; |
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| 432 | |
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| 433 | nb_cycles_simulated = 0; |
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| 434 | |
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| 435 | while (1) |
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| 436 | { |
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| 437 | unsigned int nb_cycles_simulation; |
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| 438 | |
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| 439 | if (nb_cycles_define == true) |
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| 440 | { |
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| 441 | nb_cycles_simulation = nb_cycles; |
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| 442 | nb_cycles = 0; // to stop at the next loop :D |
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| 443 | } |
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| 444 | else |
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| 445 | nb_cycles_simulation = simulation(); |
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| 446 | |
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| 447 | if (nb_cycles_simulation == 0) |
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| 448 | break; |
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| 449 | |
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| 450 | gettimeofday(&time_begin ,NULL); |
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| 451 | sc_start (nb_cycles_simulation); |
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| 452 | gettimeofday(&time_end ,NULL); |
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| 453 | |
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| 454 | nb_cycles_simulated += nb_cycles_simulation; |
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| 455 | |
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| 456 | print_time(time_begin,time_end,nb_cycles_simulation,(unsigned int)sc_simulation_time()); |
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| 457 | } |
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| 458 | |
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| 459 | cout << "\n<" << argv[0] << "> Simulation : End\n\n" << endl; |
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| 460 | |
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| 461 | /******************************************************** |
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| 462 | * Simulation - End |
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| 463 | ********************************************************/ |
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| 464 | clean_exit (); |
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| 465 | |
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| 466 | return 0; |
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| 467 | } |
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