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source: trunk/Platforms/Generic/src/main_sc.cpp @ 72

Last change on this file since 72 was 2, checked in by kane, 18 years ago
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1	#include <stdio.h>
2	#include <stdarg.h>
3	#include <stdlib.h>
4	#include <signal.h>
5	#include <sys/time.h>
6	#include <libgen.h>
7	#include <systemc.h>
8	#include <cmath>
9
10	/*********************************************************************
11	* Inclusion des modèles
12	*********************************************************************/
13	#include "shared/macro.h"
14	#include "shared/soclib_caches_interfaces.h"
15	#include "shared/soclib_segment_table.h"
16	#include "shared/mapping_memory.h"
17	/*********************************************************************
18	* Inclusion et parametrage du processeur
19	*********************************************************************/
20	#include "m_cpu_configuration.h"
21	#include "processor/M_CPU/Configuration/m_cpu_configuration.h"
22	#include "processor/M_CPU/M_CPU.h"
23
24	#include "hierarchy_memory/hierarchy_memory.h"
25
26	using namespace hierarchy_memory;
27	using namespace std;
28	/*********************************************************************
29	* Définitions des paramètres des composants
30	*********************************************************************/
31
32	#define WITH_XTTY false
33	#define NB_CONTEXT (M_CPU_NB_CLUSTER * M_CPU_NB_UL * M_CPU_NB_THREAD)
34
35	// Parametre du CPU dans un fichier externe
36	#define ICACHE_TEMPLATE LOG2_M_CPU_NB_CLUSTER + LOG2_M_CPU_NB_UL + LOG2_M_CPU_NB_THREAD+1, (LOG2_M_CPU_SIZE_IFETCH_QUEUE)+1 , M_CPU_SIZE_ADDR_INST, M_CPU_SIZE_INST,M_CPU_NB_INST_FETCH
37	#define DCACHE_TEMPLATE LOG2_M_CPU_NB_CLUSTER + LOG2_M_CPU_NB_UL + LOG2_M_CPU_NB_THREAD+1, (LOG2_M_CPU_SIZE_LOAD_STORE_QUEUE)+1, M_CPU_SIZE_ADDR_DATA, M_CPU_SIZE_DATA
38
39	//#define OFFSET_NB_LINE (power2(NB_CONTEXT)/power2(M_CPU_NB_CLUSTER))
40	#define OFFSET_NB_LINE 1
41
42	// nb_line, size_line, size_word, associativity, hit_latence, miss_penality
43	#define L1_ICACHE "L1_ICACHE",(128*OFFSET_NB_LINE), 16, 4, 4, 2, 4
44	#define L1_DCACHE "L1_DCACHE",(128*OFFSET_NB_LINE), 16, 4, 4, 2, 4
45	#define L2_CACHE "L2_CACHE" , 16384, 32, 4, 8, 6, 100
46
47	#define NB_IPORT 1
48	#define NB_DPORT M_CPU_NB_DATA_ACCESS
49
50	#define SIZE_BUFFER_IRSP 4
51	#define SIZE_BUFFER_DRSP 4
52
53	#define HIERARCHY_MEMORY_TEMPLATE LOG2_M_CPU_NB_CLUSTER + LOG2_M_CPU_NB_UL + LOG2_M_CPU_NB_THREAD+1, (LOG2_M_CPU_SIZE_IFETCH_QUEUE)+1 , M_CPU_SIZE_ADDR_INST, M_CPU_SIZE_INST,M_CPU_NB_INST_FETCH, (LOG2_M_CPU_SIZE_LOAD_STORE_QUEUE)+1, M_CPU_SIZE_ADDR_DATA, M_CPU_SIZE_DATA
54	#define MAPPING_TABLE_CLUSTER_TEMPLATE LOG2_M_CPU_NB_UL, M_CPU_NB_UL, LOG2_M_CPU_NB_INST_SELECT, M_CPU_NB_INST_SELECT
55	#define MAPPING_TABLE_UE_TEMPLATE LOG2_M_CPU_NB_CLUSTER, M_CPU_NB_CLUSTER, LOG2_M_CPU_NB_INST_SELECT, M_CPU_NB_INST_SELECT
56	#define MAPPING_TABLE_DISPATCH_TEMPLATE LOG2_M_CPU_NB_INST_SELECT, M_CPU_NB_INST_SELECT, LOG2_M_CPU_NB_UE, M_CPU_NB_UE
57	#define TYPE_TABLE_INST_L_TEMPLATE LOG2_NB_INST_L, NB_INST_L
58
59
60	/*********************************************************************
61	* Variable global
62	*********************************************************************/
63	timeval time_begin;
64	timeval time_end;
65	unsigned int nb_cycles_simulated = 0;
66
67	/********************************************************
68	* Déclarations des composants
69	********************************************************/
70
71	UE_CONFIGURATION ** ue_configuration;
72	MAPPING_TABLE <MAPPING_TABLE_CLUSTER_TEMPLATE> ** mapping_table_cluster;
73	MAPPING_TABLE <MAPPING_TABLE_UE_TEMPLATE> * mapping_table_ue;
74	MAPPING_TABLE <MAPPING_TABLE_DISPATCH_TEMPLATE> * mapping_table_dispatch;
75
76	TYPE_TABLE <TYPE_TABLE_INST_L_TEMPLATE> * type_table_inst_l;
77
78	HIERARCHY_MEMORY<HIERARCHY_MEMORY_TEMPLATE> * memory;
79	M_CPU <M_CPU_CONFIGURATION> * m_cpu;
80
81	/*********************************************************************
82	* print_time
83	*********************************************************************/
84	void print_time (timeval time_begin, timeval time_end, unsigned int nb_cycles_simulated, unsigned int nb_cycles_current)
85	{
86	double average = (double)(nb_cycles_simulated) / (double)(time_end.tv_sec-time_begin.tv_sec);
87
88	cout << nb_cycles_current << "\t(" << average << " cycles / seconds )" << endl;
89	}
90
91	/*********************************************************************
92	* clean_exit
93	*********************************************************************/
94	void clean_exit ()
95	{
96	sc_stop();
97
98	gettimeofday(&time_end ,NULL);
99	print_time(time_begin,time_end,(unsigned int)sc_simulation_time()-nb_cycles_simulated,(unsigned int)sc_simulation_time());
100
101	delete memory;
102
103	for (unsigned int i = 0; i < M_CPU_NB_CLUSTER; i ++)
104	delete mapping_table_cluster[i];
105	for (unsigned int i = 0; i < M_CPU_NB_UE; i ++)
106	delete ue_configuration[i];
107
108	delete mapping_table_ue;
109	delete mapping_table_dispatch;
110	delete type_table_inst_l;
111
112	delete m_cpu;
113	}
114
115	/*********************************************************************
116	* handler_signal
117	*********************************************************************/
118	void handler_signal(int signum)
119	{
120	switch (signum)
121	{
122	case SIGTERM :
123	case SIGINT :
124	{
125	perror("Stop of simulation\n");
126	clean_exit();
127	exit(2);
128	break;
129	}
130	default :
131	{
132	break;
133	}
134	}//end switch signum
135	}
136
137	/*********************************************************************
138	* simulation
139	*********************************************************************/
140	unsigned int simulation ()
141	{
142	// Test if can continue the simulation (all thread have not send the stop signal)
143	if (memory->stop() == true)
144	return 0;
145
146	cout << "How many cycle to simulate ? (0 to stop the simulation)" << endl;
147
148	int nb_cycle;
149	cin >> nb_cycle;
150
151	cout << " ... again " << nb_cycle << " cycles" << endl;
152	return nb_cycle;
153	}
154
155	/*********************************************************************
156	* power2
157	*********************************************************************/
158	// return the Y=2^n with 2^(n-1) < X <= 2^n
159	// Warning : possible bug if X > 0x80000000
160	uint32_t power2 (uint32_t x)
161	{
162	uint32_t mask;
163
164	for (mask = 1; mask < x; mask <<= 1);
165
166	return mask;
167	}
168
169	/*********************************************************************
170	* usage
171	*********************************************************************/
172
173	void usage(char * name_fct)
174	{
175	cerr << "usage : " << name_fct << " filename [nb_cycle]" << endl;
176	cerr << " * filename : name of binary" << endl;
177	cerr << " * nb_cycle : number of cycle to simulate" << endl;
178	exit(1);
179	}
180
181	/*********************************************************************
182	* sc_main
183	*********************************************************************/
184
185	int sc_main(int argc, char* argv[])
186	{
187	// Trap signal
188	signal(SIGTERM, handler_signal);
189	signal(SIGINT , handler_signal);
190
191	if ( (argc != 2) &&
192	(argc != 3))
193	usage(argv[0]);
194
195	unsigned int nb_cycles = 0;
196	bool nb_cycles_define = false;
197	const char * filename = argv[1];
198
199	if (argc >= 3)
200	{
201	nb_cycles_define = true;
202	nb_cycles = atoi(argv[2]);
203	}
204
205	/*********************************************************************
206	* Déclarations des variables pour la simulation
207	*********************************************************************/
208
209	/*********************************************************************
210	* Déclarations des signaux
211	*********************************************************************/
212	sc_clock CLK ("clock",1,0.5);
213	sc_signal<bool> NRESET;
214
215	ICACHE_SIGNALS <ICACHE_TEMPLATE> ** icache_signals;
216	DCACHE_SIGNALS <DCACHE_TEMPLATE> ** dcache_signals;
217
218	/********************************************************
219	* Segment table
220	********************************************************/
221
222	log_printf(INFO,"<sc_main> Table des segments\n");
223	SOCLIB_SEGMENT_TABLE segtable;
224	segtable.setMSBNumber (8);
225	segtable.setDefaultTarget(0,0);
226
227	//shared data segment
228
229	// Add a segment :name , address of base , size , global index , local index, uncache
230	segtable.addSegment("text" , TEXT_BASE , TEXT_SIZE , 0 ,0 , false);
231	segtable.addSegment("data" , DATA_CACHED_BASE , DATA_CACHED_SIZE , 0 ,0 , false);
232	segtable.addSegment("data_unc" , DATA_UNCACHED_BASE , DATA_UNCACHED_SIZE , 0 ,0 , true );
233	segtable.addSegment("stack" , STACK_BASE , STACK_SIZE , 0 ,0 , false);
234	segtable.addSegment("tty" , TTY_BASE , TTY_SIZE , 0 ,0 , true );
235	segtable.addSegment("sim2os" , SIM2OS_BASE , SIM2OS_SIZE , 0 ,0 , true );
236	segtable.addSegment("ramlock" , RAMLOCK_BASE , RAMLOCK_SIZE , 0 ,0 , true );
237
238	/********************************************************
239	* Déclaration des signaux
240	********************************************************/
241	log_printf(INFO,"<sc_main> Déclaration des signaux\n");
242	icache_signals = new ICACHE_SIGNALS <ICACHE_TEMPLATE> * [M_CPU_NB_CLUSTER];
243	dcache_signals = new DCACHE_SIGNALS <DCACHE_TEMPLATE> * [M_CPU_NB_CLUSTER];
244
245
246	for (unsigned int it_m_cpu_nb_cluster = 0; it_m_cpu_nb_cluster < M_CPU_NB_CLUSTER; it_m_cpu_nb_cluster ++)
247	{
248	icache_signals [it_m_cpu_nb_cluster] = new ICACHE_SIGNALS <ICACHE_TEMPLATE> [NB_IPORT];
249	dcache_signals [it_m_cpu_nb_cluster] = new DCACHE_SIGNALS <DCACHE_TEMPLATE> [NB_DPORT];
250	}
251
252	/********************************************************
253	* Déclaration des composants
254	********************************************************/
255
256	log_printf(INFO,"<sc_main> Déclaration des composants\n");
257
258	// UE_CONFIGURATION
259
260	ue_configuration = new UE_CONFIGURATION * [M_CPU_NB_UE];
261	for (unsigned int i = 0; i < M_CPU_NB_UE; i ++)
262	{
263	std::ostringstream name_ue_configuration;
264	name_ue_configuration << "ue_configuration[" << i << "]";
265	ue_configuration[i] = new UE_CONFIGURATION (name_ue_configuration.str().c_str());
266	}
267
268	// MAPPING_TABLE (CLUSTER)
269
270	mapping_table_cluster = new MAPPING_TABLE <MAPPING_TABLE_CLUSTER_TEMPLATE> * [M_CPU_NB_CLUSTER];
271	for (unsigned int i = 0; i < (M_CPU_NB_CLUSTER); i ++)
272	{
273	std::ostringstream name_mapping_table_cluster;
274	name_mapping_table_cluster << "mapping_table_cluster[" << i << "]";
275	mapping_table_cluster[i] = new MAPPING_TABLE <MAPPING_TABLE_CLUSTER_TEMPLATE> (name_mapping_table_cluster.str().c_str());
276	}
277
278	// MAPPING_TABLE (UE)
279	std::ostringstream name_mapping_table_ue;
280	name_mapping_table_ue << "mapping_table_ue";
281	mapping_table_ue = new MAPPING_TABLE <MAPPING_TABLE_UE_TEMPLATE> (name_mapping_table_ue.str().c_str());
282
283	// MAPPING_TABLE (DISPATCH)
284	std::ostringstream name_mapping_table_dispatch;
285	name_mapping_table_dispatch << "mapping_table_dispatch";
286	mapping_table_dispatch = new MAPPING_TABLE <MAPPING_TABLE_DISPATCH_TEMPLATE> (name_mapping_table_dispatch.str().c_str());
287
288	std::ostringstream name_type_table_inst_l;
289	name_type_table_inst_l << "type_table_inst_l";
290
291	type_table_inst_l = new TYPE_TABLE <TYPE_TABLE_INST_L_TEMPLATE> (name_type_table_inst_l.str().c_str());
292
293	// initialisation of internal structure
294	ini_ue_configuration (ue_configuration);
295	ini_mapping_table_cluster (mapping_table_cluster);
296	ini_mapping_table_ue (mapping_table_ue);
297	ini_mapping_table_dispatch (mapping_table_dispatch);
298	ini_type_table_inst_l (type_table_inst_l);
299
300	// ----- SYSTEM MEMORY -----
301
302	char * name_tty [NB_CONTEXT];
303
304	for (uint32_t num_context = 0; num_context < NB_CONTEXT; num_context ++)
305	{
306	std::ostringstream name_one_tty;
307	name_one_tty << "tty_" << num_context;
308
309	unsigned int size_name = strlen(name_one_tty.str().c_str())+1;
310	name_tty [num_context] = new char [size_name];
311	strncpy(name_tty [num_context],name_one_tty.str().c_str(),size_name);
312	}
313
314	param_entity_t<tty::param_t> param_tty [1] = {param_entity_t<tty::param_t> (TTY_BASE , TTY_SIZE , tty::param_t ("tty" , NB_CONTEXT, name_tty,WITH_XTTY))};
315	param_entity_t<ramlock::param_t> param_ramlock [1] = {param_entity_t<ramlock::param_t> (RAMLOCK_BASE, RAMLOCK_SIZE, ramlock::param_t("ramlock", RAMLOCK_SIZE))};
316	param_entity_t<sim2os::param_t> param_sim2os = param_entity_t<sim2os::param_t> (SIM2OS_BASE, SIM2OS_SIZE, sim2os::param_t("sim2os",&segtable));
317
318	param_cache_t param_icache [1] = { param_cache_t (L1_ICACHE) };
319	param_cache_t param_dcache [1] = { param_cache_t (L1_DCACHE) };
320	param_cache_t param_scache [1] = { param_cache_t (L2_CACHE)};
321
322	cache::cache_multilevel::param_t param_icache_dedicated [M_CPU_NB_CLUSTER];
323	cache::cache_multilevel::param_t param_dcache_dedicated [M_CPU_NB_CLUSTER];
324
325	for (uint32_t num_cluster = 0; num_cluster < M_CPU_NB_CLUSTER; num_cluster ++)
326	{
327	std::ostringstream name_icache_dedicated;
328	name_icache_dedicated << "icache_dedicated[" << num_cluster << "]";
329
330	param_icache_dedicated [num_cluster] = cache::cache_multilevel::param_t (name_icache_dedicated.str().c_str(),1, NB_IPORT, param_icache);
331
332	std::ostringstream name_dcache_dedicated;
333	name_dcache_dedicated << "dcache_dedicated[" << num_cluster << "]";
334	param_dcache_dedicated [num_cluster] = cache::cache_multilevel::param_t (name_dcache_dedicated.str().c_str(),1, NB_DPORT, param_dcache);
335	}
336
337	cache::cache_multilevel::param_t param_cache_shared ("param_cache_shared",1, M_CPU_NB_CLUSTER*(NB_IPORT+NB_DPORT), param_scache);
338
339	cache::param_t param_cache ("cache" ,
340	M_CPU_NB_CLUSTER ,
341	param_icache_dedicated,
342	param_dcache_dedicated,
343	param_cache_shared );
344
345	std::ostringstream name_memory;
346	name_memory << basename(argv[0]) << "_memory";
347	memory = new HIERARCHY_MEMORY <HIERARCHY_MEMORY_TEMPLATE> (name_memory.str().c_str() ,
348	0 ,
349	0 ,
350	&segtable ,
351	M_CPU_NB_CLUSTER,
352	NB_CONTEXT ,
353	SIZE_BUFFER_IRSP,
354	SIZE_BUFFER_DRSP,
355	hierarchy_memory::param_t(1,param_tty,
356	1,param_ramlock,
357	param_sim2os,
358	param_cache)
359	);
360
361	std::ostringstream name_m_cpu;
362	name_m_cpu << basename(argv[0]) << "_m_cpu";
363	m_cpu = new M_CPU <M_CPU_CONFIGURATION> (name_m_cpu.str().c_str() ,
364	ue_configuration ,
365	mapping_table_cluster ,
366	mapping_table_ue ,
367	mapping_table_dispatch ,
368	type_table_inst_l ,
369	M_CPU_PARAMETER_USE
370	);
371	//////////////////////////////////////////////////////////
372	// Segments Initialisation
373	//////////////////////////////////////////////////////////
374
375	log_printf(INFO,"<sc_main> Table des segments : initialisation\n");
376
377	const char *sections_text [] = {".text",NULL};
378	const char *sections_data [] = {".data",".rodata",".bss",".sdata",".sbss", NULL};
379	const char *sections_stack [] = {".stack",NULL};
380
381	memory->init("text" , filename, sections_text);
382	memory->init("stack" , filename, sections_stack);
383	memory->init("data" , filename, sections_data);
384
385	segtable.print();
386
387	/********************************************************
388	* Instanciation
389	********************************************************/
390
391	log_printf(INFO,"<sc_main> Instanciation des composants\n");
392
393	log_printf(INFO,"<sc_main> Instanciation de l'élément \"memory\"\n");
394	memory->CLK (CLK);
395	memory->NRESET (NRESET);
396
397	for (uint32_t x = 0; x < M_CPU_NB_CLUSTER; x ++)
398	{
399	for (uint32_t y = 0; y < NB_IPORT; y ++)
400	memory->ICACHE[x][y] (icache_signals [x][y]);
401	for (uint32_t y = 0; y < NB_DPORT; y ++)
402	memory->DCACHE[x][y] (dcache_signals [x][y]);
403	}
404
405	log_printf(INFO,"<sc_main> Instanciation de l'élément \"m_cpu\"\n");
406	m_cpu->CLK (CLK);
407	m_cpu->NRESET (NRESET);
408	for (unsigned int it_m_cpu_nb_cluster = 0; it_m_cpu_nb_cluster < M_CPU_NB_CLUSTER; it_m_cpu_nb_cluster++)
409	{
410	m_cpu->ICACHE[it_m_cpu_nb_cluster] (icache_signals[it_m_cpu_nb_cluster][0]);
411
412	for (unsigned int it_nb_dport = 0; it_nb_dport < NB_DPORT; it_nb_dport++)
413	m_cpu->DCACHE[it_m_cpu_nb_cluster][it_nb_dport] (dcache_signals[it_m_cpu_nb_cluster][it_nb_dport]);
414	}//end it_m_cpu_nb_cluster
415
416	log_printf(NONE,"<sc_main> Successful Instanciation\n");
417
418	/********************************************************
419	* Simulation - Begin
420	********************************************************/
421
422	// Initialisation
423	sc_start(0);
424
425	// Reset
426	NRESET.write(false);
427	sc_start(5);
428	NRESET.write(true);
429
430	// Lunch the simulation
431	cout << "\n<" << argv[0] << "> Simulation : Begin\n\n" << endl;
432
433	nb_cycles_simulated = 0;
434
435	while (1)
436	{
437	unsigned int nb_cycles_simulation;
438
439	if (nb_cycles_define == true)
440	{
441	nb_cycles_simulation = nb_cycles;
442	nb_cycles = 0; // to stop at the next loop :D
443	}
444	else
445	nb_cycles_simulation = simulation();
446
447	if (nb_cycles_simulation == 0)
448	break;
449
450	gettimeofday(&time_begin ,NULL);
451	sc_start (nb_cycles_simulation);
452	gettimeofday(&time_end ,NULL);
453
454	nb_cycles_simulated += nb_cycles_simulation;
455
456	print_time(time_begin,time_end,nb_cycles_simulation,(unsigned int)sc_simulation_time());
457	}
458
459	cout << "\n<" << argv[0] << "> Simulation : End\n\n" << endl;
460
461	/********************************************************
462	* Simulation - End
463	********************************************************/
464	clean_exit ();
465
466	return 0;
467	}

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