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source: trunk/Platforms/Test/src/test.cpp @ 141

Last change on this file since 141 was 138, checked in by rosiere, 14 years ago
1) add counters_t type for interface 2) fix in check load in load_store_unit 3) add parameters (but not yet implemented) 4) change environment and add script (distcc_env.sh ...) 5) add warning if an unser change rename flag with l.mtspr instruction 6) ...
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File size: 30.6 KB

Rev	Line
[88]	1	/*
	2	* $Id: test.cpp 138 2010-05-12 17:34:01Z rosiere $
	3	*
	4	* [ Description ]
	5	*
	6	* Platforms : Morpheo + Environment
	7	*/
	8
	9	#define CYCLE_MAX 0
	10
	11	#include "../include/test.h"
	12
	13	#include "Environment.h"
	14	#include "Behavioural/include/Allocation.h"
	15	#include "Common/include/Time.h"
	16	#include "../../../IPs/systemC/shared/mapping_memory.h"
	17	#include "../../../IPs/systemC/processor/Morpheo/Common/include/Test.h"
	18
	19	using namespace std;
	20	using namespace environment;
	21	using namespace morpheo;
	22
	23	int test(string filename_simulator,
	24	string filename_generator,
	25	string filename_instance ,
	26	string filename_software ,
	27	uint32_t nb_cache_dedicated,
	28	uint32_t nb_cache_shared ,
	29	uint32_t cache_size ,
	30	uint32_t cache_ratio ,
	31	morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void)
	32	)
	33	{
	34	//==============================================================================
	35	//===== [ DECLARATION ]=========================================================
	36	//==============================================================================
	37
	38
	39	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	40	//~~~~~ [ Morpheo ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	41	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	42
	43	// 1) Translation
	44	if (setlocale (LC_ALL, "") == NULL)
	45	{
[138]	46	msgError("Error setlocale.\n");
[88]	47	exit (EXIT_FAILURE);
	48	}
	49
	50	// 2) Morpheo Construction
[138]	51	Morpheo * morpheo;
	52	try
	53	{
	54	morpheo = new Morpheo
	55	("morpheo",
	56	filename_simulator,
	57	filename_generator,
	58	filename_instance ,
	59	get_custom_information
	60	);
	61	}
	62	catch (morpheo::ErrorMorpheo & error)
	63	{
	64	std::cerr << error.what() << std::endl;
[88]	65
[138]	66	msgError("%s\n",STR_KO);
	67
	68	return EXIT_FAILURE;
	69	}
	70
[88]	71	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	72	//~~~~~ [ Environment ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	73	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[117]	74
	75	uint32_t nb_thread = morpheo->_nb_thread;
[88]	76	uint32_t nb_entity = 1;
	77
	78	// Cache access
	79	uint32_t * iaccess_nb_context = new uint32_t [nb_entity];
	80	uint32_t * iaccess_nb_instruction= new uint32_t [nb_entity];
	81	uint32_t * iaccess_nb_packet = new uint32_t [nb_entity];
	82	uint32_t * iaccess_size_address = new uint32_t [nb_entity];
	83	uint32_t * iaccess_size_data = new uint32_t [nb_entity];
	84
	85	uint32_t * daccess_nb_context = new uint32_t [nb_entity];
	86	uint32_t * daccess_nb_packet = new uint32_t [nb_entity];
	87	uint32_t * daccess_size_address = new uint32_t [nb_entity];
	88	uint32_t * daccess_size_data = new uint32_t [nb_entity];
	89
	90	uint32_t * buffer_irsp_size = new uint32_t [nb_entity];
	91	uint32_t * buffer_drsp_size = new uint32_t [nb_entity];
	92
	93	for (uint32_t i=0; i<nb_entity; i++)
	94	{
	95	iaccess_nb_context [i] = morpheo->_nb_thread;
	96	iaccess_nb_instruction [i] = max<uint32_t>(morpheo->_icache_nb_instruction,morpheo->_nb_icache_port);
	97	iaccess_nb_packet [i] = 1<<morpheo->_size_icache_packet_id;
	98	iaccess_size_address [i] = morpheo->_size_icache_address;
	99	iaccess_size_data [i] = morpheo->_size_icache_instruction;
	100
	101	daccess_nb_context [i] = morpheo->_nb_thread;
	102	daccess_nb_packet [i] = 1<<morpheo->_size_dcache_packet_id;
	103	daccess_size_address [i] = morpheo->_size_dcache_address;
	104	daccess_size_data [i] = morpheo->_size_dcache_data;
[138]	105
[88]	106	buffer_irsp_size [i] = 8;
	107	buffer_drsp_size [i] = 8;
	108	}
	109
	110	uint32_t cache_nb_line ;
	111	uint32_t cache_size_line ;
	112	uint32_t cache_size_word ;
	113	uint32_t cache_associativity ;
	114	uint32_t cache_hit_latence ;
	115	uint32_t cache_miss_penality ;
	116
	117	// Instruction/Data cache
	118	uint32_t * icache_nb_level = new uint32_t [nb_entity];
	119	uint32_t * icache_nb_port = new uint32_t [nb_entity];
	120	uint32_t ** icache_nb_line = new uint32_t * [nb_entity];
	121	uint32_t ** icache_size_line = new uint32_t * [nb_entity];
	122	uint32_t ** icache_size_word = new uint32_t * [nb_entity];
	123	uint32_t ** icache_associativity = new uint32_t * [nb_entity];
	124	uint32_t ** icache_hit_latence = new uint32_t * [nb_entity];
	125	uint32_t ** icache_miss_penality = new uint32_t * [nb_entity];
	126
	127	uint32_t * dcache_nb_level = new uint32_t [nb_entity];
	128	uint32_t * dcache_nb_port = new uint32_t [nb_entity];
	129	uint32_t ** dcache_nb_line = new uint32_t * [nb_entity];
	130	uint32_t ** dcache_size_line = new uint32_t * [nb_entity];
	131	uint32_t ** dcache_size_word = new uint32_t * [nb_entity];
	132	uint32_t ** dcache_associativity = new uint32_t * [nb_entity];
	133	uint32_t ** dcache_hit_latence = new uint32_t * [nb_entity];
	134	uint32_t ** dcache_miss_penality = new uint32_t * [nb_entity];
	135
	136	for (uint32_t i=0; i<nb_entity; i++)
	137	{
	138	cache_size_word = max(max<uint32_t>(morpheo->_icache_nb_instruction,morpheo->_nb_icache_port)*morpheo->_size_icache_instruction,morpheo->_size_dcache_data)/8;
	139	cache_size_line = 8;
	140
	141	if (cache_size<(cache_size_line*cache_size_word))
	142	{
[138]	143	msgError("cache is too small\n");
[88]	144	exit(EXIT_FAILURE);
	145	}
	146
	147	cache_nb_line = cache_size/(cache_size_line*cache_size_word);
	148	cache_associativity = 1;
	149	cache_hit_latence = 1;
	150	cache_miss_penality = 5;
	151
	152	icache_nb_level [i] = nb_cache_dedicated;
	153	icache_nb_port [i] = morpheo->_nb_icache_port;
	154	icache_nb_line [i] = new uint32_t [icache_nb_level[i]];
	155	icache_size_line [i] = new uint32_t [icache_nb_level[i]];
	156	icache_size_word [i] = new uint32_t [icache_nb_level[i]];
	157	icache_associativity [i] = new uint32_t [icache_nb_level[i]];
	158	icache_hit_latence [i] = new uint32_t [icache_nb_level[i]];
	159	icache_miss_penality [i] = new uint32_t [icache_nb_level[i]];
	160
	161	dcache_nb_level [i] = icache_nb_level [i];
	162	dcache_nb_port [i] = morpheo->_nb_dcache_port;
	163	dcache_nb_line [i] = new uint32_t [dcache_nb_level[i]];
	164	dcache_size_line [i] = new uint32_t [dcache_nb_level[i]];
	165	dcache_size_word [i] = new uint32_t [dcache_nb_level[i]];
	166	dcache_associativity [i] = new uint32_t [dcache_nb_level[i]];
	167	dcache_hit_latence [i] = new uint32_t [dcache_nb_level[i]];
	168	dcache_miss_penality [i] = new uint32_t [dcache_nb_level[i]];
	169
	170	for (uint32_t j=0; j<icache_nb_level[i]; ++j)
	171	{
	172	icache_nb_line [i][j] = cache_nb_line ;
	173	icache_size_line [i][j] = cache_size_line ;
	174	icache_size_word [i][j] = cache_size_word ;
	175	icache_associativity [i][j] = cache_associativity;
	176	icache_hit_latence [i][j] = cache_hit_latence ;
	177	icache_miss_penality [i][j] = cache_miss_penality;
	178
	179	dcache_nb_line [i][j] = cache_nb_line ;
	180	dcache_size_line [i][j] = cache_size_line ;
	181	dcache_size_word [i][j] = cache_size_word ;
	182	dcache_associativity [i][j] = cache_associativity;
	183	dcache_hit_latence [i][j] = cache_hit_latence ;
	184	dcache_miss_penality [i][j] = cache_miss_penality;
	185
	186	cache_nb_line *= cache_ratio;
	187	cache_size_line *= cache_ratio;
	188	// cache_size_word *= cache_ratio;
	189	cache_associativity *= cache_ratio;
	190	cache_hit_latence *= cache_ratio;
	191	cache_miss_penality *= cache_ratio;
	192	}
	193	}
	194
	195	// Cache shared
	196	uint32_t * cache_shared_nb_line = new uint32_t [nb_cache_shared];
	197	uint32_t * cache_shared_size_line = new uint32_t [nb_cache_shared];
	198	uint32_t * cache_shared_size_word = new uint32_t [nb_cache_shared];
	199	uint32_t * cache_shared_associativity = new uint32_t [nb_cache_shared];
	200	uint32_t * cache_shared_hit_latence = new uint32_t [nb_cache_shared];
	201	uint32_t * cache_shared_miss_penality = new uint32_t [nb_cache_shared];
	202
	203	for (uint32_t i=0; i<nb_cache_shared; ++i)
	204	{
	205	cache_shared_nb_line [i] = cache_nb_line ;
	206	cache_shared_size_line [i] = cache_size_line ;
	207	cache_shared_size_word [i] = cache_size_word ;
	208	cache_shared_associativity [i] = cache_associativity;
	209	cache_shared_hit_latence [i] = cache_hit_latence ;
	210	cache_shared_miss_penality [i] = cache_miss_penality;
	211
	212	cache_nb_line *= cache_ratio;
	213	cache_size_line *= cache_ratio;
	214	// cache_size_word *= cache_ratio;
	215	cache_associativity *= cache_ratio;
	216	cache_hit_latence *= cache_ratio;
	217	cache_miss_penality *= cache_ratio;
	218	}
	219
	220	// TTY
	221	uint32_t nb_component_tty = 1;
	222	uint32_t * tty_address = new uint32_t [nb_component_tty];
	223	uint32_t * nb_tty = new uint32_t [nb_component_tty];
	224	for (uint32_t i=0; i<nb_component_tty; ++i)
	225	{
	226	tty_address [i] = TTY_BASE;
[117]	227	nb_tty [i] = nb_thread;
[88]	228	}
	229	string ** name_tty = new string * [nb_component_tty];
	230	for (uint32_t i=0; i<nb_component_tty; ++i)
	231	{
	232	name_tty [i] = new string [nb_tty[i]];
	233	for (uint32_t j=0; j<nb_tty[i]; ++j)
	234	name_tty [i][j] = "tty_"+toString(i)+"_"+toString(j);
	235	}
	236
	237	// Ramlock
	238	uint32_t nb_component_ramlock = 1;
	239	uint32_t * ramlock_address = new uint32_t [nb_component_ramlock];
	240	uint32_t * nb_lock = new uint32_t [nb_component_ramlock];
	241	for (uint32_t i=0; i<nb_component_ramlock; ++i)
	242	{
	243	ramlock_address [i] = RAMLOCK_BASE;
[117]	244	nb_lock [i] = 100*nb_thread;
[88]	245	}
	246
	247	// Sim2OS
	248	uint32_t sim2os_address = SIM2OS_BASE;
	249	uint32_t sim2os_size = SIM2OS_SIZE;
	250
	251	SOCLIB_SEGMENT_TABLE * segtable = new SOCLIB_SEGMENT_TABLE;
	252	segtable->setMSBNumber (8);
	253	segtable->setDefaultTarget(0,0);
[123]	254
[101]	255	// Add a segment ,name ,address of base ,size ,global index,local index,uncache
	256	segtable->addSegment("text" ,TEXT_BASE ,TEXT_SIZE ,0 ,0 ,false);
	257	segtable->addSegment("data" ,DATA_CACHED_BASE ,DATA_CACHED_SIZE ,0 ,0 ,false);
	258	segtable->addSegment("data_stack" ,DATA_STACK_BASE ,DATA_STACK_SIZE ,0 ,0 ,false);
	259	segtable->addSegment("data_unc" ,DATA_UNCACHED_BASE,DATA_UNCACHED_SIZE,0 ,0 ,true );
[88]	260
	261	Parameters * param_environment = new Parameters
[117]	262	(nb_thread,
	263	nb_entity,
[88]	264
	265	iaccess_nb_context,
	266	iaccess_nb_instruction,
	267	iaccess_nb_packet,
	268	iaccess_size_address,
	269	iaccess_size_data,
	270
	271	daccess_nb_context,
	272	daccess_nb_packet,
	273	daccess_size_address,
	274	daccess_size_data,
	275
	276	buffer_irsp_size,
	277	buffer_drsp_size,
	278
	279	icache_nb_level ,
	280	icache_nb_port ,
	281	icache_nb_line ,
	282	icache_size_line ,
	283	icache_size_word ,
	284	icache_associativity,
	285	icache_hit_latence ,
	286	icache_miss_penality,
	287	dcache_nb_level ,
	288	dcache_nb_port ,
	289	dcache_nb_line ,
	290	dcache_size_line ,
	291	dcache_size_word ,
	292	dcache_associativity,
	293	dcache_hit_latence ,
	294	dcache_miss_penality,
	295
	296	nb_cache_shared ,
	297	// cache_shared_nb_port ,
	298	cache_shared_nb_line ,
	299	cache_shared_size_line ,
	300	cache_shared_size_word ,
	301	cache_shared_associativity ,
	302	cache_shared_hit_latence ,
	303	cache_shared_miss_penality ,
	304
	305	nb_component_tty,
	306	tty_address,
	307	nb_tty,
	308	name_tty,
[118]	309	false,
[88]	310
	311	nb_component_ramlock,
	312	ramlock_address,
	313	nb_lock,
	314
	315	sim2os_address,
	316	sim2os_size,
	317	segtable
	318	);
	319
[123]	320	// cout << param_environment->print(0) << endl;
[88]	321
	322	Environment * environment = new Environment ("environment",param_environment);
	323
	324	const char * sections_text [] = {".text",NULL};
	325	const char * sections_data [] = {".data",".rodata",".bss",".sdata",".sbss", NULL};
	326
[138]	327	if (environment->init("text", filename_software.c_str(), sections_text) == false) exit (EXIT_FAILURE);
	328	if (environment->init("data", filename_software.c_str(), sections_data) == false) exit (EXIT_FAILURE);
	329
	330	// segtable->print();
	331
[88]	332	//==============================================================================
	333	//===== [ SIGNAL ]==============================================================
	334	//==============================================================================
[132]	335	#ifdef SYSTEMCASS_SPECIFIC
[138]	336	sc_clock * CLOCK = new sc_clock ("CLOCK__________________", 1.0, 0.5);
[132]	337	#else
[131]	338	sc_time period (TIME_PERIOD, TIME_UNIT);
[138]	339	sc_clock * CLOCK = new sc_clock ("CLOCK__________________", period);
[132]	340	#endif
[138]	341	sc_signal<Tcontrol_t> * NRESET = new sc_signal<Tcontrol_t> ("NRESET_________________");
[88]	342
[114]	343	sc_signal<Tcontrol_t > ** ICACHE_REQ_VAL ;
	344	sc_signal<Tcontrol_t > ** ICACHE_REQ_ACK ;
	345	sc_signal<Ticache_context_t > ** ICACHE_REQ_THREAD_ID ;
	346	sc_signal<Ticache_packet_t > ** ICACHE_REQ_PACKET_ID ;
	347	sc_signal<Ticache_address_t > ** ICACHE_REQ_ADDRESS ;
	348	sc_signal<Ticache_type_t > ** ICACHE_REQ_TYPE ;
	349
	350	sc_signal<Tcontrol_t > ** ICACHE_RSP_VAL ;
	351	sc_signal<Tcontrol_t > ** ICACHE_RSP_ACK ;
	352	sc_signal<Ticache_context_t > ** ICACHE_RSP_THREAD_ID ;
	353	sc_signal<Ticache_packet_t > ** ICACHE_RSP_PACKET_ID ;
	354	sc_signal<Ticache_instruction_t> *** ICACHE_RSP_INSTRUCTION;
	355	sc_signal<Ticache_error_t > ** ICACHE_RSP_ERROR ;
	356
	357	sc_signal<Tcontrol_t > ** DCACHE_REQ_VAL ;
	358	sc_signal<Tcontrol_t > ** DCACHE_REQ_ACK ;
	359	sc_signal<Tdcache_context_t > ** DCACHE_REQ_THREAD_ID ;
	360	sc_signal<Tdcache_packet_t > ** DCACHE_REQ_PACKET_ID ;
	361	sc_signal<Tdcache_address_t > ** DCACHE_REQ_ADDRESS ;
	362	sc_signal<Tdcache_data_t > ** DCACHE_REQ_WDATA ;
	363	sc_signal<Tdcache_type_t > ** DCACHE_REQ_TYPE ;
	364
	365	sc_signal<Tcontrol_t > ** DCACHE_RSP_VAL ;
	366	sc_signal<Tcontrol_t > ** DCACHE_RSP_ACK ;
	367	sc_signal<Tdcache_context_t > ** DCACHE_RSP_THREAD_ID ;
	368	sc_signal<Tdcache_packet_t > ** DCACHE_RSP_PACKET_ID ;
	369	sc_signal<Tdcache_data_t > ** DCACHE_RSP_RDATA ;
	370	sc_signal<Tdcache_error_t > ** DCACHE_RSP_ERROR ;
	371
	372	sc_signal<Tcontrol_t > ** INTERRUPT_ENABLE ;
	373
[138]	374	ALLOC1_SC_SIGNAL(ICACHE_REQ_VAL ,"ICACHE_REQ_VAL_________",Tcontrol_t ,morpheo->_nb_icache_port);
	375	ALLOC1_SC_SIGNAL(ICACHE_REQ_ACK ,"ICACHE_REQ_ACK_________",Tcontrol_t ,morpheo->_nb_icache_port);
	376	ALLOC1_SC_SIGNAL(ICACHE_REQ_THREAD_ID ,"ICACHE_REQ_THREAD_ID___",Ticache_context_t ,morpheo->_nb_icache_port);
	377	ALLOC1_SC_SIGNAL(ICACHE_REQ_PACKET_ID ,"ICACHE_REQ_PACKET_ID___",Ticache_packet_t ,morpheo->_nb_icache_port);
	378	ALLOC1_SC_SIGNAL(ICACHE_REQ_ADDRESS ,"ICACHE_REQ_ADDRESS_____",Ticache_address_t ,morpheo->_nb_icache_port);
	379	ALLOC1_SC_SIGNAL(ICACHE_REQ_TYPE ,"ICACHE_REQ_TYPE________",Ticache_type_t ,morpheo->_nb_icache_port);
[88]	380
[138]	381	ALLOC1_SC_SIGNAL(ICACHE_RSP_VAL ,"ICACHE_RSP_VAL_________",Tcontrol_t ,morpheo->_nb_icache_port);
	382	ALLOC1_SC_SIGNAL(ICACHE_RSP_ACK ,"ICACHE_RSP_ACK_________",Tcontrol_t ,morpheo->_nb_icache_port);
	383	ALLOC1_SC_SIGNAL(ICACHE_RSP_THREAD_ID ,"ICACHE_RSP_THREAD_ID___",Ticache_context_t ,morpheo->_nb_icache_port);
	384	ALLOC1_SC_SIGNAL(ICACHE_RSP_PACKET_ID ,"ICACHE_RSP_PACKET_ID___",Ticache_packet_t ,morpheo->_nb_icache_port);
	385	ALLOC2_SC_SIGNAL(ICACHE_RSP_INSTRUCTION ,"ICACHE_RSP_INSTRUCTION_",Ticache_instruction_t,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]);
	386	ALLOC1_SC_SIGNAL(ICACHE_RSP_ERROR ,"ICACHE_RSP_ERROR_______",Ticache_error_t ,morpheo->_nb_icache_port);
[88]	387
[138]	388	ALLOC1_SC_SIGNAL(DCACHE_REQ_VAL ,"DCACHE_REQ_VAL_________",Tcontrol_t ,morpheo->_nb_dcache_port);
	389	ALLOC1_SC_SIGNAL(DCACHE_REQ_ACK ,"DCACHE_REQ_ACK_________",Tcontrol_t ,morpheo->_nb_dcache_port);
	390	ALLOC1_SC_SIGNAL(DCACHE_REQ_THREAD_ID ,"DCACHE_REQ_THREAD_ID___",Tdcache_context_t ,morpheo->_nb_dcache_port);
	391	ALLOC1_SC_SIGNAL(DCACHE_REQ_PACKET_ID ,"DCACHE_REQ_PACKET_ID___",Tdcache_packet_t ,morpheo->_nb_dcache_port);
	392	ALLOC1_SC_SIGNAL(DCACHE_REQ_ADDRESS ,"DCACHE_REQ_ADDRESS_____",Tdcache_address_t ,morpheo->_nb_dcache_port);
	393	ALLOC1_SC_SIGNAL(DCACHE_REQ_WDATA ,"DCACHE_REQ_WDATA_______",Tdcache_data_t ,morpheo->_nb_dcache_port);
	394	ALLOC1_SC_SIGNAL(DCACHE_REQ_TYPE ,"DCACHE_REQ_TYPE________",Tdcache_type_t ,morpheo->_nb_dcache_port);
[88]	395
[138]	396	ALLOC1_SC_SIGNAL(DCACHE_RSP_VAL ,"DCACHE_RSP_VAL_________",Tcontrol_t ,morpheo->_nb_dcache_port);
	397	ALLOC1_SC_SIGNAL(DCACHE_RSP_ACK ,"DCACHE_RSP_ACK_________",Tcontrol_t ,morpheo->_nb_dcache_port);
	398	ALLOC1_SC_SIGNAL(DCACHE_RSP_THREAD_ID ,"DCACHE_RSP_THREAD_ID___",Tdcache_context_t ,morpheo->_nb_dcache_port);
	399	ALLOC1_SC_SIGNAL(DCACHE_RSP_PACKET_ID ,"DCACHE_RSP_PACKET_ID___",Tdcache_packet_t ,morpheo->_nb_dcache_port);
	400	ALLOC1_SC_SIGNAL(DCACHE_RSP_RDATA ,"DCACHE_RSP_RDATA_______",Tdcache_data_t ,morpheo->_nb_dcache_port);
	401	ALLOC1_SC_SIGNAL(DCACHE_RSP_ERROR ,"DCACHE_RSP_ERROR_______",Tdcache_error_t ,morpheo->_nb_dcache_port);
	402
	403	ALLOC1_SC_SIGNAL(INTERRUPT_ENABLE ,"INTERRUPT_ENABLE_______",Tcontrol_t ,morpheo->_nb_thread);
	404
[88]	405	//==============================================================================
	406	//===== [ INSTANCE ]============================================================
	407	//==============================================================================
	408
	409	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	410	//~~~~~ [ Morpheo ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	411	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	412
	413	((morpheo->in_CLOCK)) ((CLOCK));
	414	((morpheo->in_NRESET)) ((NRESET));
	415
	416	_INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_VAL ,ICACHE_REQ_VAL ,morpheo->_nb_icache_port);
	417	_INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_REQ_ACK ,ICACHE_REQ_ACK ,morpheo->_nb_icache_port);
	418	if (morpheo->_have_port_icache_thread_id)
	419	_INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_THREAD_ID ,ICACHE_REQ_THREAD_ID ,morpheo->_nb_icache_port);
	420	if (morpheo->_have_port_icache_packet_id)
	421	_INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_PACKET_ID ,ICACHE_REQ_PACKET_ID ,morpheo->_nb_icache_port);
	422	_INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_ADDRESS ,ICACHE_REQ_ADDRESS ,morpheo->_nb_icache_port);
	423	_INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_TYPE ,ICACHE_REQ_TYPE ,morpheo->_nb_icache_port);
	424
	425	_INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_VAL ,ICACHE_RSP_VAL ,morpheo->_nb_icache_port);
	426	_INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_RSP_ACK ,ICACHE_RSP_ACK ,morpheo->_nb_icache_port);
	427	if (morpheo->_have_port_icache_thread_id)
	428	_INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_THREAD_ID ,ICACHE_RSP_THREAD_ID ,morpheo->_nb_icache_port);
	429	if (morpheo->_have_port_icache_packet_id)
	430	_INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_PACKET_ID ,ICACHE_RSP_PACKET_ID ,morpheo->_nb_icache_port);
	431	_INSTANCE2_SC_SIGNAL(morpheo, in_ICACHE_RSP_INSTRUCTION ,ICACHE_RSP_INSTRUCTION ,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]);
	432	_INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_ERROR ,ICACHE_RSP_ERROR ,morpheo->_nb_icache_port);
	433
	434	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_VAL ,DCACHE_REQ_VAL ,morpheo->_nb_dcache_port);
	435	_INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_REQ_ACK ,DCACHE_REQ_ACK ,morpheo->_nb_dcache_port);
	436	if (morpheo->_have_port_dcache_thread_id)
	437	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_THREAD_ID ,DCACHE_REQ_THREAD_ID ,morpheo->_nb_dcache_port);
	438	if (morpheo->_have_port_dcache_packet_id)
	439	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_PACKET_ID ,DCACHE_REQ_PACKET_ID ,morpheo->_nb_dcache_port);
	440	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_ADDRESS ,DCACHE_REQ_ADDRESS ,morpheo->_nb_dcache_port);
	441	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_WDATA ,DCACHE_REQ_WDATA ,morpheo->_nb_dcache_port);
	442	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_TYPE ,DCACHE_REQ_TYPE ,morpheo->_nb_dcache_port);
	443
	444	_INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_VAL ,DCACHE_RSP_VAL ,morpheo->_nb_dcache_port);
	445	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_RSP_ACK ,DCACHE_RSP_ACK ,morpheo->_nb_dcache_port);
	446	if (morpheo->_have_port_dcache_thread_id)
	447	_INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_THREAD_ID ,DCACHE_RSP_THREAD_ID ,morpheo->_nb_dcache_port);
	448	if (morpheo->_have_port_dcache_packet_id)
	449	_INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_PACKET_ID ,DCACHE_RSP_PACKET_ID ,morpheo->_nb_dcache_port);
	450	_INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_RDATA ,DCACHE_RSP_RDATA ,morpheo->_nb_dcache_port);
	451	_INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_ERROR ,DCACHE_RSP_ERROR ,morpheo->_nb_dcache_port);
	452
	453	_INSTANCE1_SC_SIGNAL(morpheo, in_INTERRUPT_ENABLE ,INTERRUPT_ENABLE ,morpheo->_nb_thread);
	454
	455	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	456	//~~~~~ [ Environment ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	457	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	458
	459	((environment->CLOCK)) ((CLOCK));
	460	((environment->NRESET)) ((NRESET));
	461
	462	for (uint32_t i=0; i<morpheo->_nb_icache_port; ++i)
	463	{
	464	((environment->ICACHE_REQ_VAL [0][i] )) ((ICACHE_REQ_VAL [i] ));
	465	((environment->ICACHE_REQ_ACK [0][i] )) ((ICACHE_REQ_ACK [i] ));
	466	((environment->ICACHE_REQ_CONTEXT_ID [0][i] )) ((ICACHE_REQ_THREAD_ID [i] ));
	467	((environment->ICACHE_REQ_PACKET_ID [0][i] )) ((ICACHE_REQ_PACKET_ID [i] ));
	468	((environment->ICACHE_REQ_ADDRESS [0][i] )) ((ICACHE_REQ_ADDRESS [i] ));
	469	((environment->ICACHE_REQ_TYPE [0][i] )) ((ICACHE_REQ_TYPE [i] ));
	470
	471	((environment->ICACHE_RSP_VAL [0][i] )) ((ICACHE_RSP_VAL [i] ));
	472	((environment->ICACHE_RSP_ACK [0][i] )) ((ICACHE_RSP_ACK [i] ));
	473	((environment->ICACHE_RSP_CONTEXT_ID [0][i] )) ((ICACHE_RSP_THREAD_ID [i] ));
	474	((environment->ICACHE_RSP_PACKET_ID [0][i] )) ((ICACHE_RSP_PACKET_ID [i] ));
	475	((environment->ICACHE_RSP_ERROR [0][i] )) ((ICACHE_RSP_ERROR [i] ));
	476
	477	for (uint32_t j=0; j<morpheo->_icache_nb_instruction[i]; ++j)
	478	((environment->ICACHE_RSP_INSTRUCTION [0][i][j])) ((ICACHE_RSP_INSTRUCTION [i][j]));
	479	}
	480	for (uint32_t i=0; i<morpheo->_nb_dcache_port; ++i)
	481	{
	482	((environment->DCACHE_REQ_VAL [0][i] )) ((DCACHE_REQ_VAL [i] ));
	483	((environment->DCACHE_REQ_ACK [0][i] )) ((DCACHE_REQ_ACK [i] ));
	484	((environment->DCACHE_REQ_CONTEXT_ID [0][i] )) ((DCACHE_REQ_THREAD_ID [i] ));
	485	((environment->DCACHE_REQ_PACKET_ID [0][i] )) ((DCACHE_REQ_PACKET_ID [i] ));
	486	((environment->DCACHE_REQ_ADDRESS [0][i] )) ((DCACHE_REQ_ADDRESS [i] ));
	487	((environment->DCACHE_REQ_WDATA [0][i] )) ((DCACHE_REQ_WDATA [i] ));
	488	((environment->DCACHE_REQ_TYPE [0][i] )) ((DCACHE_REQ_TYPE [i] ));
	489
	490	((environment->DCACHE_RSP_VAL [0][i] )) ((DCACHE_RSP_VAL [i] ));
	491	((environment->DCACHE_RSP_ACK [0][i] )) ((DCACHE_RSP_ACK [i] ));
	492	((environment->DCACHE_RSP_CONTEXT_ID [0][i] )) ((DCACHE_RSP_THREAD_ID [i] ));
	493	((environment->DCACHE_RSP_PACKET_ID [0][i] )) ((DCACHE_RSP_PACKET_ID [i] ));
	494	((environment->DCACHE_RSP_RDATA [0][i] )) ((DCACHE_RSP_RDATA [i] ));
	495	((environment->DCACHE_RSP_ERROR [0][i] )) ((DCACHE_RSP_ERROR [i] ));
	496	}
	497
	498	//_INSTANCE2_SC_SIGNAL(environment,INTERRUPT_ENABLE ,1,morpheo->_nb_thread);
	499
	500	//==============================================================================
	501	//===== [ SIMULATION ]==========================================================
	502	//==============================================================================
	503
	504	// initialisation
[131]	505
[138]	506	msgInformation("<test> Simulation Init\n");
[88]	507
[132]	508	sc_time t (0, TIME_UNIT);
	509	sc_start(t);
[88]	510
[138]	511	msgInformation("<test> Simulation Start\n");
[88]	512
[124]	513	bool morpheo_error = false;
	514	try
	515	{
	516	Time * _time_global = new Time();
	517
	518	for (uint32_t i=0; i<morpheo->_nb_thread; ++i)
	519	INTERRUPT_ENABLE[i]->write(0);
	520
	521	NRESET->write(0);
	522	SC_START(5);
	523	NRESET->write(1);
	524
	525	// Infinite loop
	526	do
	527	{
	528	// Time * _time_local = new Time();
	529	SC_START(100000);
	530	// delete _time_local;
	531	} while (not morpheo ->simulation_end() and // morpheo condition stop
	532	not environment->simulation_end()); // test ok
	533	delete _time_global;
	534	}
	535	catch (morpheo::ErrorMorpheo & error)
	536	{
[138]	537	std::cerr << error.what() << std::endl;
[88]	538
[138]	539	msgError("%s\n",STR_KO);
	540
[124]	541	morpheo_error = true;
	542	}
[88]	543
	544	bool morpheo_end = morpheo->simulation_end();
	545	bool environment_end = environment->simulation_end();
	546
	547
	548	//==============================================================================
	549	//===== [ DESTRUCTION ]=========================================================
	550	//==============================================================================
	551
	552	delete CLOCK;
	553	delete NRESET;
	554
	555	DELETE1_SC_SIGNAL(ICACHE_REQ_VAL ,morpheo->_nb_icache_port);
	556	DELETE1_SC_SIGNAL(ICACHE_REQ_ACK ,morpheo->_nb_icache_port);
	557	DELETE1_SC_SIGNAL(ICACHE_REQ_THREAD_ID ,morpheo->_nb_icache_port);
	558	DELETE1_SC_SIGNAL(ICACHE_REQ_PACKET_ID ,morpheo->_nb_icache_port);
	559	DELETE1_SC_SIGNAL(ICACHE_REQ_ADDRESS ,morpheo->_nb_icache_port);
	560	DELETE1_SC_SIGNAL(ICACHE_REQ_TYPE ,morpheo->_nb_icache_port);
	561
	562	DELETE1_SC_SIGNAL(ICACHE_RSP_VAL ,morpheo->_nb_icache_port);
	563	DELETE1_SC_SIGNAL(ICACHE_RSP_ACK ,morpheo->_nb_icache_port);
	564	DELETE1_SC_SIGNAL(ICACHE_RSP_THREAD_ID ,morpheo->_nb_icache_port);
	565	DELETE1_SC_SIGNAL(ICACHE_RSP_PACKET_ID ,morpheo->_nb_icache_port);
	566	DELETE1_SC_SIGNAL(ICACHE_RSP_ERROR ,morpheo->_nb_icache_port);
	567	DELETE2_SC_SIGNAL(ICACHE_RSP_INSTRUCTION ,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]);
	568
	569	DELETE1_SC_SIGNAL(DCACHE_REQ_VAL ,morpheo->_nb_dcache_port);
	570	DELETE1_SC_SIGNAL(DCACHE_REQ_ACK ,morpheo->_nb_dcache_port);
	571	DELETE1_SC_SIGNAL(DCACHE_REQ_THREAD_ID ,morpheo->_nb_dcache_port);
	572	DELETE1_SC_SIGNAL(DCACHE_REQ_PACKET_ID ,morpheo->_nb_dcache_port);
	573	DELETE1_SC_SIGNAL(DCACHE_REQ_ADDRESS ,morpheo->_nb_dcache_port);
	574	DELETE1_SC_SIGNAL(DCACHE_REQ_WDATA ,morpheo->_nb_dcache_port);
	575	DELETE1_SC_SIGNAL(DCACHE_REQ_TYPE ,morpheo->_nb_dcache_port);
	576
	577	DELETE1_SC_SIGNAL(DCACHE_RSP_VAL ,morpheo->_nb_dcache_port);
	578	DELETE1_SC_SIGNAL(DCACHE_RSP_ACK ,morpheo->_nb_dcache_port);
	579	DELETE1_SC_SIGNAL(DCACHE_RSP_THREAD_ID ,morpheo->_nb_dcache_port);
	580	DELETE1_SC_SIGNAL(DCACHE_RSP_PACKET_ID ,morpheo->_nb_dcache_port);
	581	DELETE1_SC_SIGNAL(DCACHE_RSP_RDATA ,morpheo->_nb_dcache_port);
	582	DELETE1_SC_SIGNAL(DCACHE_RSP_ERROR ,morpheo->_nb_dcache_port);
	583
	584	DELETE1_SC_SIGNAL(INTERRUPT_ENABLE ,morpheo->_nb_thread);
	585
	586	delete environment;
	587
	588	delete param_environment;
	589	delete segtable;
	590
	591	delete [] nb_lock ;
	592	delete [] ramlock_address;
[112]	593
[88]	594	for (uint32_t i=0;i<nb_component_tty;++i)
	595	delete [] name_tty [i];
	596	delete [] name_tty;
[112]	597	delete [] nb_tty;
[88]	598	delete [] tty_address;
	599
	600	delete [] cache_shared_miss_penality;
	601	delete [] cache_shared_hit_latence ;
	602	delete [] cache_shared_associativity;
	603	delete [] cache_shared_size_word ;
	604	delete [] cache_shared_size_line ;
	605	delete [] cache_shared_nb_line ;
	606
	607	for (uint32_t i=0; i<nb_entity; i++)
	608	{
[112]	609	delete [] dcache_miss_penality [i];
	610	delete [] dcache_hit_latence [i];
	611	delete [] dcache_associativity [i];
	612	delete [] dcache_size_word [i];
	613	delete [] dcache_size_line [i];
	614	delete [] dcache_nb_line [i];
	615	}
	616	delete [] dcache_miss_penality ;
	617	delete [] dcache_hit_latence ;
	618	delete [] dcache_associativity ;
	619	delete [] dcache_size_word ;
	620	delete [] dcache_size_line ;
	621	delete [] dcache_nb_line ;
	622	delete [] dcache_nb_level ;
	623	delete [] dcache_nb_port ;
	624
	625	for (uint32_t i=0; i<nb_entity; i++)
	626	{
[88]	627	delete [] icache_miss_penality [i];
	628	delete [] icache_hit_latence [i];
	629	delete [] icache_associativity [i];
	630	delete [] icache_size_word [i];
	631	delete [] icache_size_line [i];
	632	delete [] icache_nb_line [i];
	633	}
	634	delete [] icache_miss_penality;
	635	delete [] icache_hit_latence ;
	636	delete [] icache_associativity;
	637	delete [] icache_size_word ;
	638	delete [] icache_size_line ;
	639	delete [] icache_nb_line ;
[112]	640	delete [] icache_nb_level ;
	641	delete [] icache_nb_port ;
[88]	642
	643	delete [] buffer_drsp_size ;
	644	delete [] buffer_irsp_size ;
	645	delete [] daccess_size_data ;
	646	delete [] daccess_size_address ;
	647	delete [] daccess_nb_packet ;
	648	delete [] daccess_nb_context ;
	649	delete [] iaccess_size_data ;
	650	delete [] iaccess_size_address ;
	651	delete [] iaccess_nb_packet ;
	652	delete [] iaccess_nb_instruction;
	653	delete [] iaccess_nb_context ;
	654
[112]	655	delete morpheo;
	656
[88]	657	bool test_ok = false;
[124]	658	if (not morpheo_error)
[88]	659	{
[124]	660	if (not morpheo_end and not environment_end)
[88]	661	{
[138]	662	msgError("<test> Simulation End : Unknow\n");
[88]	663	}
[124]	664	else
	665	{
	666	if (morpheo_end)
	667	{
[138]	668	msgInformation("<test> Simulation End : MORPHEO\n");
[124]	669	test_ok = true;
	670	}
	671	if (environment_end)
	672	{
[138]	673	msgInformation("<test> Simulation End : ENVIRONMENT\n");
[124]	674	test_ok = true;
	675	}
	676	}
[88]	677	}
[124]	678
[88]	679	if (test_ok)
	680	{
[138]	681	msgInformation("%s\n",STR_OK);
[88]	682	return EXIT_SUCCESS;
	683	}
	684	else
	685	{
[138]	686	msgInformation("%s\n",STR_KO);
[88]	687	return EXIT_FAILURE;
	688	}
	689	}

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