source: trunk/Platforms/Test/src/test.cpp@ 114

Last change on this file since 114 was 114, checked in by rosiere, 17 years ago

1) Fix bug with previous commit
2) Add test libc
3) Change Dhrystone
  • Property svn:keywords set to Id
File size: 29.8 KB
Line 
1/*
2 * $Id: test.cpp 114 2009-04-16 22:35:37Z rosiere $
3 *
4 * [ Description ]
5 *
6 * Platforms : Morpheo + Environment
7 */
8
9#define CYCLE_MAX 0
10
11#include "../include/test.h"
12
13#include "Environment.h"
14#include "Behavioural/include/Allocation.h"
15#include "Common/include/Time.h"
16#include "../../../IPs/systemC/shared/mapping_memory.h"
17#include "../../../IPs/systemC/processor/Morpheo/Common/include/Test.h"
18
19using namespace std;
20using namespace environment;
21using namespace morpheo;
22
23int test(string filename_simulator,
24 string filename_generator,
25 string filename_instance ,
26 string filename_software ,
27 uint32_t nb_cache_dedicated,
28 uint32_t nb_cache_shared ,
29 uint32_t cache_size ,
30 uint32_t cache_ratio ,
31 morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void)
32 )
33{
34 //==============================================================================
35 //===== [ DECLARATION ]=========================================================
36 //==============================================================================
37
38
39 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
40 //~~~~~ [ Morpheo ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
41 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
42
43 // 1) Translation
44 if (setlocale (LC_ALL, "") == NULL)
45 {
46 cerr << "Error setlocale." << endl;
47 exit (EXIT_FAILURE);
48 }
49
50 // 2) Morpheo Construction
51 Morpheo * morpheo = new Morpheo
52 ("morpheo",
53 filename_simulator,
54 filename_generator,
55 filename_instance ,
56 get_custom_information
57 );
58
59 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
60 //~~~~~ [ Environment ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
61 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
62
63 uint32_t nb_entity = 1;
64
65 // Cache access
66 uint32_t * iaccess_nb_context = new uint32_t [nb_entity];
67 uint32_t * iaccess_nb_instruction= new uint32_t [nb_entity];
68 uint32_t * iaccess_nb_packet = new uint32_t [nb_entity];
69 uint32_t * iaccess_size_address = new uint32_t [nb_entity];
70 uint32_t * iaccess_size_data = new uint32_t [nb_entity];
71
72 uint32_t * daccess_nb_context = new uint32_t [nb_entity];
73 uint32_t * daccess_nb_packet = new uint32_t [nb_entity];
74 uint32_t * daccess_size_address = new uint32_t [nb_entity];
75 uint32_t * daccess_size_data = new uint32_t [nb_entity];
76
77 uint32_t * buffer_irsp_size = new uint32_t [nb_entity];
78 uint32_t * buffer_drsp_size = new uint32_t [nb_entity];
79
80 for (uint32_t i=0; i<nb_entity; i++)
81 {
82 iaccess_nb_context [i] = morpheo->_nb_thread;
83 iaccess_nb_instruction [i] = max<uint32_t>(morpheo->_icache_nb_instruction,morpheo->_nb_icache_port);
84 iaccess_nb_packet [i] = 1<<morpheo->_size_icache_packet_id;
85 iaccess_size_address [i] = morpheo->_size_icache_address;
86 iaccess_size_data [i] = morpheo->_size_icache_instruction;
87
88 daccess_nb_context [i] = morpheo->_nb_thread;
89 daccess_nb_packet [i] = 1<<morpheo->_size_dcache_packet_id;
90 daccess_size_address [i] = morpheo->_size_dcache_address;
91 daccess_size_data [i] = morpheo->_size_dcache_data;
92
93 buffer_irsp_size [i] = 8;
94 buffer_drsp_size [i] = 8;
95 }
96
97 uint32_t cache_nb_line ;
98 uint32_t cache_size_line ;
99 uint32_t cache_size_word ;
100 uint32_t cache_associativity ;
101 uint32_t cache_hit_latence ;
102 uint32_t cache_miss_penality ;
103
104 // Instruction/Data cache
105 uint32_t * icache_nb_level = new uint32_t [nb_entity];
106 uint32_t * icache_nb_port = new uint32_t [nb_entity];
107 uint32_t ** icache_nb_line = new uint32_t * [nb_entity];
108 uint32_t ** icache_size_line = new uint32_t * [nb_entity];
109 uint32_t ** icache_size_word = new uint32_t * [nb_entity];
110 uint32_t ** icache_associativity = new uint32_t * [nb_entity];
111 uint32_t ** icache_hit_latence = new uint32_t * [nb_entity];
112 uint32_t ** icache_miss_penality = new uint32_t * [nb_entity];
113
114 uint32_t * dcache_nb_level = new uint32_t [nb_entity];
115 uint32_t * dcache_nb_port = new uint32_t [nb_entity];
116 uint32_t ** dcache_nb_line = new uint32_t * [nb_entity];
117 uint32_t ** dcache_size_line = new uint32_t * [nb_entity];
118 uint32_t ** dcache_size_word = new uint32_t * [nb_entity];
119 uint32_t ** dcache_associativity = new uint32_t * [nb_entity];
120 uint32_t ** dcache_hit_latence = new uint32_t * [nb_entity];
121 uint32_t ** dcache_miss_penality = new uint32_t * [nb_entity];
122
123 for (uint32_t i=0; i<nb_entity; i++)
124 {
125 cache_size_word = max(max<uint32_t>(morpheo->_icache_nb_instruction,morpheo->_nb_icache_port)*morpheo->_size_icache_instruction,morpheo->_size_dcache_data)/8;
126 cache_size_line = 8;
127
128 if (cache_size<(cache_size_line*cache_size_word))
129 {
130 cerr << "cache is too small" << endl;
131 exit(EXIT_FAILURE);
132 }
133
134 cache_nb_line = cache_size/(cache_size_line*cache_size_word);
135 cache_associativity = 1;
136 cache_hit_latence = 1;
137 cache_miss_penality = 5;
138
139 icache_nb_level [i] = nb_cache_dedicated;
140 icache_nb_port [i] = morpheo->_nb_icache_port;
141 icache_nb_line [i] = new uint32_t [icache_nb_level[i]];
142 icache_size_line [i] = new uint32_t [icache_nb_level[i]];
143 icache_size_word [i] = new uint32_t [icache_nb_level[i]];
144 icache_associativity [i] = new uint32_t [icache_nb_level[i]];
145 icache_hit_latence [i] = new uint32_t [icache_nb_level[i]];
146 icache_miss_penality [i] = new uint32_t [icache_nb_level[i]];
147
148 dcache_nb_level [i] = icache_nb_level [i];
149 dcache_nb_port [i] = morpheo->_nb_dcache_port;
150 dcache_nb_line [i] = new uint32_t [dcache_nb_level[i]];
151 dcache_size_line [i] = new uint32_t [dcache_nb_level[i]];
152 dcache_size_word [i] = new uint32_t [dcache_nb_level[i]];
153 dcache_associativity [i] = new uint32_t [dcache_nb_level[i]];
154 dcache_hit_latence [i] = new uint32_t [dcache_nb_level[i]];
155 dcache_miss_penality [i] = new uint32_t [dcache_nb_level[i]];
156
157 for (uint32_t j=0; j<icache_nb_level[i]; ++j)
158 {
159 icache_nb_line [i][j] = cache_nb_line ;
160 icache_size_line [i][j] = cache_size_line ;
161 icache_size_word [i][j] = cache_size_word ;
162 icache_associativity [i][j] = cache_associativity;
163 icache_hit_latence [i][j] = cache_hit_latence ;
164 icache_miss_penality [i][j] = cache_miss_penality;
165
166 dcache_nb_line [i][j] = cache_nb_line ;
167 dcache_size_line [i][j] = cache_size_line ;
168 dcache_size_word [i][j] = cache_size_word ;
169 dcache_associativity [i][j] = cache_associativity;
170 dcache_hit_latence [i][j] = cache_hit_latence ;
171 dcache_miss_penality [i][j] = cache_miss_penality;
172
173 cache_nb_line *= cache_ratio;
174 cache_size_line *= cache_ratio;
175// cache_size_word *= cache_ratio;
176 cache_associativity *= cache_ratio;
177 cache_hit_latence *= cache_ratio;
178 cache_miss_penality *= cache_ratio;
179 }
180 }
181
182 // Cache shared
183 uint32_t * cache_shared_nb_line = new uint32_t [nb_cache_shared];
184 uint32_t * cache_shared_size_line = new uint32_t [nb_cache_shared];
185 uint32_t * cache_shared_size_word = new uint32_t [nb_cache_shared];
186 uint32_t * cache_shared_associativity = new uint32_t [nb_cache_shared];
187 uint32_t * cache_shared_hit_latence = new uint32_t [nb_cache_shared];
188 uint32_t * cache_shared_miss_penality = new uint32_t [nb_cache_shared];
189
190 for (uint32_t i=0; i<nb_cache_shared; ++i)
191 {
192 cache_shared_nb_line [i] = cache_nb_line ;
193 cache_shared_size_line [i] = cache_size_line ;
194 cache_shared_size_word [i] = cache_size_word ;
195 cache_shared_associativity [i] = cache_associativity;
196 cache_shared_hit_latence [i] = cache_hit_latence ;
197 cache_shared_miss_penality [i] = cache_miss_penality;
198
199 cache_nb_line *= cache_ratio;
200 cache_size_line *= cache_ratio;
201// cache_size_word *= cache_ratio;
202 cache_associativity *= cache_ratio;
203 cache_hit_latence *= cache_ratio;
204 cache_miss_penality *= cache_ratio;
205 }
206
207 // TTY
208 uint32_t nb_component_tty = 1;
209 uint32_t * tty_address = new uint32_t [nb_component_tty];
210 uint32_t * nb_tty = new uint32_t [nb_component_tty];
211 for (uint32_t i=0; i<nb_component_tty; ++i)
212 {
213 tty_address [i] = TTY_BASE;
214 nb_tty [i] = 4;
215 }
216 string ** name_tty = new string * [nb_component_tty];
217 for (uint32_t i=0; i<nb_component_tty; ++i)
218 {
219 name_tty [i] = new string [nb_tty[i]];
220 for (uint32_t j=0; j<nb_tty[i]; ++j)
221 name_tty [i][j] = "tty_"+toString(i)+"_"+toString(j);
222 }
223
224 // Ramlock
225 uint32_t nb_component_ramlock = 1;
226 uint32_t * ramlock_address = new uint32_t [nb_component_ramlock];
227 uint32_t * nb_lock = new uint32_t [nb_component_ramlock];
228 for (uint32_t i=0; i<nb_component_ramlock; ++i)
229 {
230 ramlock_address [i] = RAMLOCK_BASE;
231 nb_lock [i] = 10;
232 }
233
234 // Sim2OS
235 uint32_t sim2os_address = SIM2OS_BASE;
236 uint32_t sim2os_size = SIM2OS_SIZE;
237
238 SOCLIB_SEGMENT_TABLE * segtable = new SOCLIB_SEGMENT_TABLE;
239 segtable->setMSBNumber (8);
240 segtable->setDefaultTarget(0,0);
241
242 // Add a segment ,name ,address of base ,size ,global index,local index,uncache
243 segtable->addSegment("text" ,TEXT_BASE ,TEXT_SIZE ,0 ,0 ,false);
244 segtable->addSegment("data" ,DATA_CACHED_BASE ,DATA_CACHED_SIZE ,0 ,0 ,false);
245 segtable->addSegment("data_stack" ,DATA_STACK_BASE ,DATA_STACK_SIZE ,0 ,0 ,false);
246 segtable->addSegment("data_unc" ,DATA_UNCACHED_BASE,DATA_UNCACHED_SIZE,0 ,0 ,true );
247
248 Parameters * param_environment = new Parameters
249 (nb_entity,
250
251 iaccess_nb_context,
252 iaccess_nb_instruction,
253 iaccess_nb_packet,
254 iaccess_size_address,
255 iaccess_size_data,
256
257 daccess_nb_context,
258 daccess_nb_packet,
259 daccess_size_address,
260 daccess_size_data,
261
262 buffer_irsp_size,
263 buffer_drsp_size,
264
265 icache_nb_level ,
266 icache_nb_port ,
267 icache_nb_line ,
268 icache_size_line ,
269 icache_size_word ,
270 icache_associativity,
271 icache_hit_latence ,
272 icache_miss_penality,
273 dcache_nb_level ,
274 dcache_nb_port ,
275 dcache_nb_line ,
276 dcache_size_line ,
277 dcache_size_word ,
278 dcache_associativity,
279 dcache_hit_latence ,
280 dcache_miss_penality,
281
282 nb_cache_shared ,
283// cache_shared_nb_port ,
284 cache_shared_nb_line ,
285 cache_shared_size_line ,
286 cache_shared_size_word ,
287 cache_shared_associativity ,
288 cache_shared_hit_latence ,
289 cache_shared_miss_penality ,
290
291 nb_component_tty,
292 tty_address,
293 nb_tty,
294 name_tty,
295 false,
296
297 nb_component_ramlock,
298 ramlock_address,
299 nb_lock,
300
301 sim2os_address,
302 sim2os_size,
303 segtable
304 );
305
306 cout << param_environment->print(0) << endl;
307
308 segtable->print();
309
310 Environment * environment = new Environment ("environment",param_environment);
311
312 const char * sections_text [] = {".text",NULL};
313 const char * sections_data [] = {".data",".rodata",".bss",".sdata",".sbss", NULL};
314
315 if (environment->init("text" , filename_software.c_str(), sections_text) == false) exit (EXIT_FAILURE);
316 if (environment->init("data" , filename_software.c_str(), sections_data) == false) exit (EXIT_FAILURE);
317
318 //==============================================================================
319 //===== [ SIGNAL ]==============================================================
320 //==============================================================================
321
322 sc_clock * CLOCK = new sc_clock ("clock", 1.0, 0.5);
323 sc_signal<Tcontrol_t> * NRESET = new sc_signal<Tcontrol_t> ("NRESET");
324
325 sc_signal<Tcontrol_t > ** ICACHE_REQ_VAL ;
326 sc_signal<Tcontrol_t > ** ICACHE_REQ_ACK ;
327 sc_signal<Ticache_context_t > ** ICACHE_REQ_THREAD_ID ;
328 sc_signal<Ticache_packet_t > ** ICACHE_REQ_PACKET_ID ;
329 sc_signal<Ticache_address_t > ** ICACHE_REQ_ADDRESS ;
330 sc_signal<Ticache_type_t > ** ICACHE_REQ_TYPE ;
331
332 sc_signal<Tcontrol_t > ** ICACHE_RSP_VAL ;
333 sc_signal<Tcontrol_t > ** ICACHE_RSP_ACK ;
334 sc_signal<Ticache_context_t > ** ICACHE_RSP_THREAD_ID ;
335 sc_signal<Ticache_packet_t > ** ICACHE_RSP_PACKET_ID ;
336 sc_signal<Ticache_instruction_t> *** ICACHE_RSP_INSTRUCTION;
337 sc_signal<Ticache_error_t > ** ICACHE_RSP_ERROR ;
338
339 sc_signal<Tcontrol_t > ** DCACHE_REQ_VAL ;
340 sc_signal<Tcontrol_t > ** DCACHE_REQ_ACK ;
341 sc_signal<Tdcache_context_t > ** DCACHE_REQ_THREAD_ID ;
342 sc_signal<Tdcache_packet_t > ** DCACHE_REQ_PACKET_ID ;
343 sc_signal<Tdcache_address_t > ** DCACHE_REQ_ADDRESS ;
344 sc_signal<Tdcache_data_t > ** DCACHE_REQ_WDATA ;
345 sc_signal<Tdcache_type_t > ** DCACHE_REQ_TYPE ;
346
347 sc_signal<Tcontrol_t > ** DCACHE_RSP_VAL ;
348 sc_signal<Tcontrol_t > ** DCACHE_RSP_ACK ;
349 sc_signal<Tdcache_context_t > ** DCACHE_RSP_THREAD_ID ;
350 sc_signal<Tdcache_packet_t > ** DCACHE_RSP_PACKET_ID ;
351 sc_signal<Tdcache_data_t > ** DCACHE_RSP_RDATA ;
352 sc_signal<Tdcache_error_t > ** DCACHE_RSP_ERROR ;
353
354 sc_signal<Tcontrol_t > ** INTERRUPT_ENABLE ;
355
356 ALLOC1_SC_SIGNAL(ICACHE_REQ_VAL ,"ICACHE_REQ_VAL ",Tcontrol_t ,morpheo->_nb_icache_port);
357 ALLOC1_SC_SIGNAL(ICACHE_REQ_ACK ,"ICACHE_REQ_ACK ",Tcontrol_t ,morpheo->_nb_icache_port);
358 ALLOC1_SC_SIGNAL(ICACHE_REQ_THREAD_ID ,"ICACHE_REQ_THREAD_ID ",Ticache_context_t ,morpheo->_nb_icache_port);
359 ALLOC1_SC_SIGNAL(ICACHE_REQ_PACKET_ID ,"ICACHE_REQ_PACKET_ID ",Ticache_packet_t ,morpheo->_nb_icache_port);
360 ALLOC1_SC_SIGNAL(ICACHE_REQ_ADDRESS ,"ICACHE_REQ_ADDRESS ",Ticache_address_t ,morpheo->_nb_icache_port);
361 ALLOC1_SC_SIGNAL(ICACHE_REQ_TYPE ,"ICACHE_REQ_TYPE ",Ticache_type_t ,morpheo->_nb_icache_port);
362
363 ALLOC1_SC_SIGNAL(ICACHE_RSP_VAL ,"ICACHE_RSP_VAL ",Tcontrol_t ,morpheo->_nb_icache_port);
364 ALLOC1_SC_SIGNAL(ICACHE_RSP_ACK ,"ICACHE_RSP_ACK ",Tcontrol_t ,morpheo->_nb_icache_port);
365 ALLOC1_SC_SIGNAL(ICACHE_RSP_THREAD_ID ,"ICACHE_RSP_THREAD_ID ",Ticache_context_t ,morpheo->_nb_icache_port);
366 ALLOC1_SC_SIGNAL(ICACHE_RSP_PACKET_ID ,"ICACHE_RSP_PACKET_ID ",Ticache_packet_t ,morpheo->_nb_icache_port);
367 ALLOC2_SC_SIGNAL(ICACHE_RSP_INSTRUCTION ,"ICACHE_RSP_INSTRUCTION",Ticache_instruction_t,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]);
368 ALLOC1_SC_SIGNAL(ICACHE_RSP_ERROR ,"ICACHE_RSP_ERROR ",Ticache_error_t ,morpheo->_nb_icache_port);
369
370 ALLOC1_SC_SIGNAL(DCACHE_REQ_VAL ,"DCACHE_REQ_VAL ",Tcontrol_t ,morpheo->_nb_dcache_port);
371 ALLOC1_SC_SIGNAL(DCACHE_REQ_ACK ,"DCACHE_REQ_ACK ",Tcontrol_t ,morpheo->_nb_dcache_port);
372 ALLOC1_SC_SIGNAL(DCACHE_REQ_THREAD_ID ,"DCACHE_REQ_THREAD_ID ",Tdcache_context_t ,morpheo->_nb_dcache_port);
373 ALLOC1_SC_SIGNAL(DCACHE_REQ_PACKET_ID ,"DCACHE_REQ_PACKET_ID ",Tdcache_packet_t ,morpheo->_nb_dcache_port);
374 ALLOC1_SC_SIGNAL(DCACHE_REQ_ADDRESS ,"DCACHE_REQ_ADDRESS ",Tdcache_address_t ,morpheo->_nb_dcache_port);
375 ALLOC1_SC_SIGNAL(DCACHE_REQ_WDATA ,"DCACHE_REQ_WDATA ",Tdcache_data_t ,morpheo->_nb_dcache_port);
376 ALLOC1_SC_SIGNAL(DCACHE_REQ_TYPE ,"DCACHE_REQ_TYPE ",Tdcache_type_t ,morpheo->_nb_dcache_port);
377
378 ALLOC1_SC_SIGNAL(DCACHE_RSP_VAL ,"DCACHE_RSP_VAL ",Tcontrol_t ,morpheo->_nb_dcache_port);
379 ALLOC1_SC_SIGNAL(DCACHE_RSP_ACK ,"DCACHE_RSP_ACK ",Tcontrol_t ,morpheo->_nb_dcache_port);
380 ALLOC1_SC_SIGNAL(DCACHE_RSP_THREAD_ID ,"DCACHE_RSP_THREAD_ID ",Tdcache_context_t ,morpheo->_nb_dcache_port);
381 ALLOC1_SC_SIGNAL(DCACHE_RSP_PACKET_ID ,"DCACHE_RSP_PACKET_ID ",Tdcache_packet_t ,morpheo->_nb_dcache_port);
382 ALLOC1_SC_SIGNAL(DCACHE_RSP_RDATA ,"DCACHE_RSP_RDATA ",Tdcache_data_t ,morpheo->_nb_dcache_port);
383 ALLOC1_SC_SIGNAL(DCACHE_RSP_ERROR ,"DCACHE_RSP_ERROR ",Tdcache_error_t ,morpheo->_nb_dcache_port);
384
385 ALLOC1_SC_SIGNAL(INTERRUPT_ENABLE ,"INTERRUPT_ENABLE ",Tcontrol_t ,morpheo->_nb_thread);
386
387 //==============================================================================
388 //===== [ INSTANCE ]============================================================
389 //==============================================================================
390
391 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
392 //~~~~~ [ Morpheo ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
393 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
394
395 (*(morpheo->in_CLOCK)) (*(CLOCK));
396 (*(morpheo->in_NRESET)) (*(NRESET));
397
398 _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_VAL ,ICACHE_REQ_VAL ,morpheo->_nb_icache_port);
399 _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_REQ_ACK ,ICACHE_REQ_ACK ,morpheo->_nb_icache_port);
400 if (morpheo->_have_port_icache_thread_id)
401 _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_THREAD_ID ,ICACHE_REQ_THREAD_ID ,morpheo->_nb_icache_port);
402 if (morpheo->_have_port_icache_packet_id)
403 _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_PACKET_ID ,ICACHE_REQ_PACKET_ID ,morpheo->_nb_icache_port);
404 _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_ADDRESS ,ICACHE_REQ_ADDRESS ,morpheo->_nb_icache_port);
405 _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_TYPE ,ICACHE_REQ_TYPE ,morpheo->_nb_icache_port);
406
407 _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_VAL ,ICACHE_RSP_VAL ,morpheo->_nb_icache_port);
408 _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_RSP_ACK ,ICACHE_RSP_ACK ,morpheo->_nb_icache_port);
409 if (morpheo->_have_port_icache_thread_id)
410 _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_THREAD_ID ,ICACHE_RSP_THREAD_ID ,morpheo->_nb_icache_port);
411 if (morpheo->_have_port_icache_packet_id)
412 _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_PACKET_ID ,ICACHE_RSP_PACKET_ID ,morpheo->_nb_icache_port);
413 _INSTANCE2_SC_SIGNAL(morpheo, in_ICACHE_RSP_INSTRUCTION ,ICACHE_RSP_INSTRUCTION ,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]);
414 _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_ERROR ,ICACHE_RSP_ERROR ,morpheo->_nb_icache_port);
415
416 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_VAL ,DCACHE_REQ_VAL ,morpheo->_nb_dcache_port);
417 _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_REQ_ACK ,DCACHE_REQ_ACK ,morpheo->_nb_dcache_port);
418 if (morpheo->_have_port_dcache_thread_id)
419 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_THREAD_ID ,DCACHE_REQ_THREAD_ID ,morpheo->_nb_dcache_port);
420 if (morpheo->_have_port_dcache_packet_id)
421 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_PACKET_ID ,DCACHE_REQ_PACKET_ID ,morpheo->_nb_dcache_port);
422 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_ADDRESS ,DCACHE_REQ_ADDRESS ,morpheo->_nb_dcache_port);
423 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_WDATA ,DCACHE_REQ_WDATA ,morpheo->_nb_dcache_port);
424 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_TYPE ,DCACHE_REQ_TYPE ,morpheo->_nb_dcache_port);
425
426 _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_VAL ,DCACHE_RSP_VAL ,morpheo->_nb_dcache_port);
427 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_RSP_ACK ,DCACHE_RSP_ACK ,morpheo->_nb_dcache_port);
428 if (morpheo->_have_port_dcache_thread_id)
429 _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_THREAD_ID ,DCACHE_RSP_THREAD_ID ,morpheo->_nb_dcache_port);
430 if (morpheo->_have_port_dcache_packet_id)
431 _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_PACKET_ID ,DCACHE_RSP_PACKET_ID ,morpheo->_nb_dcache_port);
432 _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_RDATA ,DCACHE_RSP_RDATA ,morpheo->_nb_dcache_port);
433 _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_ERROR ,DCACHE_RSP_ERROR ,morpheo->_nb_dcache_port);
434
435 _INSTANCE1_SC_SIGNAL(morpheo, in_INTERRUPT_ENABLE ,INTERRUPT_ENABLE ,morpheo->_nb_thread);
436
437 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
438 //~~~~~ [ Environment ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
439 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
440
441 (*(environment->CLOCK)) (*(CLOCK));
442 (*(environment->NRESET)) (*(NRESET));
443
444 for (uint32_t i=0; i<morpheo->_nb_icache_port; ++i)
445 {
446 (*(environment->ICACHE_REQ_VAL [0][i] )) (*(ICACHE_REQ_VAL [i] ));
447 (*(environment->ICACHE_REQ_ACK [0][i] )) (*(ICACHE_REQ_ACK [i] ));
448 (*(environment->ICACHE_REQ_CONTEXT_ID [0][i] )) (*(ICACHE_REQ_THREAD_ID [i] ));
449 (*(environment->ICACHE_REQ_PACKET_ID [0][i] )) (*(ICACHE_REQ_PACKET_ID [i] ));
450 (*(environment->ICACHE_REQ_ADDRESS [0][i] )) (*(ICACHE_REQ_ADDRESS [i] ));
451 (*(environment->ICACHE_REQ_TYPE [0][i] )) (*(ICACHE_REQ_TYPE [i] ));
452
453 (*(environment->ICACHE_RSP_VAL [0][i] )) (*(ICACHE_RSP_VAL [i] ));
454 (*(environment->ICACHE_RSP_ACK [0][i] )) (*(ICACHE_RSP_ACK [i] ));
455 (*(environment->ICACHE_RSP_CONTEXT_ID [0][i] )) (*(ICACHE_RSP_THREAD_ID [i] ));
456 (*(environment->ICACHE_RSP_PACKET_ID [0][i] )) (*(ICACHE_RSP_PACKET_ID [i] ));
457 (*(environment->ICACHE_RSP_ERROR [0][i] )) (*(ICACHE_RSP_ERROR [i] ));
458
459 for (uint32_t j=0; j<morpheo->_icache_nb_instruction[i]; ++j)
460 (*(environment->ICACHE_RSP_INSTRUCTION [0][i][j])) (*(ICACHE_RSP_INSTRUCTION [i][j]));
461 }
462 for (uint32_t i=0; i<morpheo->_nb_dcache_port; ++i)
463 {
464 (*(environment->DCACHE_REQ_VAL [0][i] )) (*(DCACHE_REQ_VAL [i] ));
465 (*(environment->DCACHE_REQ_ACK [0][i] )) (*(DCACHE_REQ_ACK [i] ));
466 (*(environment->DCACHE_REQ_CONTEXT_ID [0][i] )) (*(DCACHE_REQ_THREAD_ID [i] ));
467 (*(environment->DCACHE_REQ_PACKET_ID [0][i] )) (*(DCACHE_REQ_PACKET_ID [i] ));
468 (*(environment->DCACHE_REQ_ADDRESS [0][i] )) (*(DCACHE_REQ_ADDRESS [i] ));
469 (*(environment->DCACHE_REQ_WDATA [0][i] )) (*(DCACHE_REQ_WDATA [i] ));
470 (*(environment->DCACHE_REQ_TYPE [0][i] )) (*(DCACHE_REQ_TYPE [i] ));
471
472 (*(environment->DCACHE_RSP_VAL [0][i] )) (*(DCACHE_RSP_VAL [i] ));
473 (*(environment->DCACHE_RSP_ACK [0][i] )) (*(DCACHE_RSP_ACK [i] ));
474 (*(environment->DCACHE_RSP_CONTEXT_ID [0][i] )) (*(DCACHE_RSP_THREAD_ID [i] ));
475 (*(environment->DCACHE_RSP_PACKET_ID [0][i] )) (*(DCACHE_RSP_PACKET_ID [i] ));
476 (*(environment->DCACHE_RSP_RDATA [0][i] )) (*(DCACHE_RSP_RDATA [i] ));
477 (*(environment->DCACHE_RSP_ERROR [0][i] )) (*(DCACHE_RSP_ERROR [i] ));
478 }
479
480//_INSTANCE2_SC_SIGNAL(environment,INTERRUPT_ENABLE ,1,morpheo->_nb_thread);
481
482 //==============================================================================
483 //===== [ SIMULATION ]==========================================================
484 //==============================================================================
485
486 // initialisation
487 cerr << "<test> Simulation Init" << endl;
488
489 sc_start(0);
490
491 cerr << "<test> Simulation Start" << endl;
492
493 Time * _time_global = new Time();
494
495 for (uint32_t i=0; i<morpheo->_nb_thread; ++i)
496 INTERRUPT_ENABLE[i]->write(0);
497
498 NRESET->write(0);
499 SC_START(5);
500 NRESET->write(1);
501
502 // Infinite loop
503 do
504 {
505// Time * _time_local = new Time();
506 SC_START(100000);
507// delete _time_local;
508 } while (not morpheo ->simulation_end() and // morpheo condition stop
509 not environment->simulation_end()); // test ok
510 delete _time_global;
511
512 bool morpheo_end = morpheo->simulation_end();
513 bool environment_end = environment->simulation_end();
514
515
516 //==============================================================================
517 //===== [ DESTRUCTION ]=========================================================
518 //==============================================================================
519
520 delete CLOCK;
521 delete NRESET;
522
523 DELETE1_SC_SIGNAL(ICACHE_REQ_VAL ,morpheo->_nb_icache_port);
524 DELETE1_SC_SIGNAL(ICACHE_REQ_ACK ,morpheo->_nb_icache_port);
525 DELETE1_SC_SIGNAL(ICACHE_REQ_THREAD_ID ,morpheo->_nb_icache_port);
526 DELETE1_SC_SIGNAL(ICACHE_REQ_PACKET_ID ,morpheo->_nb_icache_port);
527 DELETE1_SC_SIGNAL(ICACHE_REQ_ADDRESS ,morpheo->_nb_icache_port);
528 DELETE1_SC_SIGNAL(ICACHE_REQ_TYPE ,morpheo->_nb_icache_port);
529
530 DELETE1_SC_SIGNAL(ICACHE_RSP_VAL ,morpheo->_nb_icache_port);
531 DELETE1_SC_SIGNAL(ICACHE_RSP_ACK ,morpheo->_nb_icache_port);
532 DELETE1_SC_SIGNAL(ICACHE_RSP_THREAD_ID ,morpheo->_nb_icache_port);
533 DELETE1_SC_SIGNAL(ICACHE_RSP_PACKET_ID ,morpheo->_nb_icache_port);
534 DELETE1_SC_SIGNAL(ICACHE_RSP_ERROR ,morpheo->_nb_icache_port);
535 DELETE2_SC_SIGNAL(ICACHE_RSP_INSTRUCTION ,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]);
536
537 DELETE1_SC_SIGNAL(DCACHE_REQ_VAL ,morpheo->_nb_dcache_port);
538 DELETE1_SC_SIGNAL(DCACHE_REQ_ACK ,morpheo->_nb_dcache_port);
539 DELETE1_SC_SIGNAL(DCACHE_REQ_THREAD_ID ,morpheo->_nb_dcache_port);
540 DELETE1_SC_SIGNAL(DCACHE_REQ_PACKET_ID ,morpheo->_nb_dcache_port);
541 DELETE1_SC_SIGNAL(DCACHE_REQ_ADDRESS ,morpheo->_nb_dcache_port);
542 DELETE1_SC_SIGNAL(DCACHE_REQ_WDATA ,morpheo->_nb_dcache_port);
543 DELETE1_SC_SIGNAL(DCACHE_REQ_TYPE ,morpheo->_nb_dcache_port);
544
545 DELETE1_SC_SIGNAL(DCACHE_RSP_VAL ,morpheo->_nb_dcache_port);
546 DELETE1_SC_SIGNAL(DCACHE_RSP_ACK ,morpheo->_nb_dcache_port);
547 DELETE1_SC_SIGNAL(DCACHE_RSP_THREAD_ID ,morpheo->_nb_dcache_port);
548 DELETE1_SC_SIGNAL(DCACHE_RSP_PACKET_ID ,morpheo->_nb_dcache_port);
549 DELETE1_SC_SIGNAL(DCACHE_RSP_RDATA ,morpheo->_nb_dcache_port);
550 DELETE1_SC_SIGNAL(DCACHE_RSP_ERROR ,morpheo->_nb_dcache_port);
551
552 DELETE1_SC_SIGNAL(INTERRUPT_ENABLE ,morpheo->_nb_thread);
553
554 delete environment;
555
556 delete param_environment;
557 delete segtable;
558
559 delete [] nb_lock ;
560 delete [] ramlock_address;
561
562 for (uint32_t i=0;i<nb_component_tty;++i)
563 delete [] name_tty [i];
564 delete [] name_tty;
565 delete [] nb_tty;
566 delete [] tty_address;
567
568 delete [] cache_shared_miss_penality;
569 delete [] cache_shared_hit_latence ;
570 delete [] cache_shared_associativity;
571 delete [] cache_shared_size_word ;
572 delete [] cache_shared_size_line ;
573 delete [] cache_shared_nb_line ;
574
575 for (uint32_t i=0; i<nb_entity; i++)
576 {
577 delete [] dcache_miss_penality [i];
578 delete [] dcache_hit_latence [i];
579 delete [] dcache_associativity [i];
580 delete [] dcache_size_word [i];
581 delete [] dcache_size_line [i];
582 delete [] dcache_nb_line [i];
583 }
584 delete [] dcache_miss_penality ;
585 delete [] dcache_hit_latence ;
586 delete [] dcache_associativity ;
587 delete [] dcache_size_word ;
588 delete [] dcache_size_line ;
589 delete [] dcache_nb_line ;
590 delete [] dcache_nb_level ;
591 delete [] dcache_nb_port ;
592
593 for (uint32_t i=0; i<nb_entity; i++)
594 {
595 delete [] icache_miss_penality [i];
596 delete [] icache_hit_latence [i];
597 delete [] icache_associativity [i];
598 delete [] icache_size_word [i];
599 delete [] icache_size_line [i];
600 delete [] icache_nb_line [i];
601 }
602 delete [] icache_miss_penality;
603 delete [] icache_hit_latence ;
604 delete [] icache_associativity;
605 delete [] icache_size_word ;
606 delete [] icache_size_line ;
607 delete [] icache_nb_line ;
608 delete [] icache_nb_level ;
609 delete [] icache_nb_port ;
610
611 delete [] buffer_drsp_size ;
612 delete [] buffer_irsp_size ;
613 delete [] daccess_size_data ;
614 delete [] daccess_size_address ;
615 delete [] daccess_nb_packet ;
616 delete [] daccess_nb_context ;
617 delete [] iaccess_size_data ;
618 delete [] iaccess_size_address ;
619 delete [] iaccess_nb_packet ;
620 delete [] iaccess_nb_instruction;
621 delete [] iaccess_nb_context ;
622
623 delete morpheo;
624
625 bool test_ok = false;
626 if (not morpheo_end and not environment_end)
627 {
628 cerr << "<test> Simulation End : Unknow" << endl;
629 }
630 else
631 {
632 if (morpheo_end)
633 cout << "<test> Simulation End : MORPHEO" << endl;
634 if (environment_end)
635 {
636 cout << "<test> Simulation End : ENVIRONMENT" << endl;
637 test_ok = true;
638 }
639 }
640
641 if (test_ok)
642 {
643 cout << STR_OK << endl;
644 return EXIT_SUCCESS;
645 }
646 else
647 {
648 cout << STR_KO << endl;
649 return EXIT_FAILURE;
650 }
651}
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