source: trunk/Platforms/Test/src/test.cpp@ 131

Last change on this file since 131 was 131, checked in by rosiere, 17 years ago

1) add constant method
2) test with systemc 2.2.0
  • Property svn:keywords set to Id
File size: 30.4 KB
Line 
1/*
2 * $Id: test.cpp 131 2009-07-08 18:40:08Z rosiere $
3 *
4 * [ Description ]
5 *
6 * Platforms : Morpheo + Environment
7 */
8
9#define CYCLE_MAX 0
10
11#include "../include/test.h"
12
13#include "Environment.h"
14#include "Behavioural/include/Allocation.h"
15#include "Common/include/Time.h"
16#include "../../../IPs/systemC/shared/mapping_memory.h"
17#include "../../../IPs/systemC/processor/Morpheo/Common/include/Test.h"
18
19using namespace std;
20using namespace environment;
21using namespace morpheo;
22
23int test(string filename_simulator,
24 string filename_generator,
25 string filename_instance ,
26 string filename_software ,
27 uint32_t nb_cache_dedicated,
28 uint32_t nb_cache_shared ,
29 uint32_t cache_size ,
30 uint32_t cache_ratio ,
31 morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void)
32 )
33{
34 //==============================================================================
35 //===== [ DECLARATION ]=========================================================
36 //==============================================================================
37
38
39 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
40 //~~~~~ [ Morpheo ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
41 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
42
43 // 1) Translation
44 if (setlocale (LC_ALL, "") == NULL)
45 {
46 cerr << "Error setlocale." << endl;
47 exit (EXIT_FAILURE);
48 }
49
50 // 2) Morpheo Construction
51 Morpheo * morpheo = new Morpheo
52 ("morpheo",
53 filename_simulator,
54 filename_generator,
55 filename_instance ,
56 get_custom_information
57 );
58
59 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
60 //~~~~~ [ Environment ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
61 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
62
63 uint32_t nb_thread = morpheo->_nb_thread;
64 uint32_t nb_entity = 1;
65
66 // Cache access
67 uint32_t * iaccess_nb_context = new uint32_t [nb_entity];
68 uint32_t * iaccess_nb_instruction= new uint32_t [nb_entity];
69 uint32_t * iaccess_nb_packet = new uint32_t [nb_entity];
70 uint32_t * iaccess_size_address = new uint32_t [nb_entity];
71 uint32_t * iaccess_size_data = new uint32_t [nb_entity];
72
73 uint32_t * daccess_nb_context = new uint32_t [nb_entity];
74 uint32_t * daccess_nb_packet = new uint32_t [nb_entity];
75 uint32_t * daccess_size_address = new uint32_t [nb_entity];
76 uint32_t * daccess_size_data = new uint32_t [nb_entity];
77
78 uint32_t * buffer_irsp_size = new uint32_t [nb_entity];
79 uint32_t * buffer_drsp_size = new uint32_t [nb_entity];
80
81 for (uint32_t i=0; i<nb_entity; i++)
82 {
83 iaccess_nb_context [i] = morpheo->_nb_thread;
84 iaccess_nb_instruction [i] = max<uint32_t>(morpheo->_icache_nb_instruction,morpheo->_nb_icache_port);
85 iaccess_nb_packet [i] = 1<<morpheo->_size_icache_packet_id;
86 iaccess_size_address [i] = morpheo->_size_icache_address;
87 iaccess_size_data [i] = morpheo->_size_icache_instruction;
88
89 daccess_nb_context [i] = morpheo->_nb_thread;
90 daccess_nb_packet [i] = 1<<morpheo->_size_dcache_packet_id;
91 daccess_size_address [i] = morpheo->_size_dcache_address;
92 daccess_size_data [i] = morpheo->_size_dcache_data;
93
94 buffer_irsp_size [i] = 8;
95 buffer_drsp_size [i] = 8;
96 }
97
98 uint32_t cache_nb_line ;
99 uint32_t cache_size_line ;
100 uint32_t cache_size_word ;
101 uint32_t cache_associativity ;
102 uint32_t cache_hit_latence ;
103 uint32_t cache_miss_penality ;
104
105 // Instruction/Data cache
106 uint32_t * icache_nb_level = new uint32_t [nb_entity];
107 uint32_t * icache_nb_port = new uint32_t [nb_entity];
108 uint32_t ** icache_nb_line = new uint32_t * [nb_entity];
109 uint32_t ** icache_size_line = new uint32_t * [nb_entity];
110 uint32_t ** icache_size_word = new uint32_t * [nb_entity];
111 uint32_t ** icache_associativity = new uint32_t * [nb_entity];
112 uint32_t ** icache_hit_latence = new uint32_t * [nb_entity];
113 uint32_t ** icache_miss_penality = new uint32_t * [nb_entity];
114
115 uint32_t * dcache_nb_level = new uint32_t [nb_entity];
116 uint32_t * dcache_nb_port = new uint32_t [nb_entity];
117 uint32_t ** dcache_nb_line = new uint32_t * [nb_entity];
118 uint32_t ** dcache_size_line = new uint32_t * [nb_entity];
119 uint32_t ** dcache_size_word = new uint32_t * [nb_entity];
120 uint32_t ** dcache_associativity = new uint32_t * [nb_entity];
121 uint32_t ** dcache_hit_latence = new uint32_t * [nb_entity];
122 uint32_t ** dcache_miss_penality = new uint32_t * [nb_entity];
123
124 for (uint32_t i=0; i<nb_entity; i++)
125 {
126 cache_size_word = max(max<uint32_t>(morpheo->_icache_nb_instruction,morpheo->_nb_icache_port)*morpheo->_size_icache_instruction,morpheo->_size_dcache_data)/8;
127 cache_size_line = 8;
128
129 if (cache_size<(cache_size_line*cache_size_word))
130 {
131 cerr << "cache is too small" << endl;
132 exit(EXIT_FAILURE);
133 }
134
135 cache_nb_line = cache_size/(cache_size_line*cache_size_word);
136 cache_associativity = 1;
137 cache_hit_latence = 1;
138 cache_miss_penality = 5;
139
140 icache_nb_level [i] = nb_cache_dedicated;
141 icache_nb_port [i] = morpheo->_nb_icache_port;
142 icache_nb_line [i] = new uint32_t [icache_nb_level[i]];
143 icache_size_line [i] = new uint32_t [icache_nb_level[i]];
144 icache_size_word [i] = new uint32_t [icache_nb_level[i]];
145 icache_associativity [i] = new uint32_t [icache_nb_level[i]];
146 icache_hit_latence [i] = new uint32_t [icache_nb_level[i]];
147 icache_miss_penality [i] = new uint32_t [icache_nb_level[i]];
148
149 dcache_nb_level [i] = icache_nb_level [i];
150 dcache_nb_port [i] = morpheo->_nb_dcache_port;
151 dcache_nb_line [i] = new uint32_t [dcache_nb_level[i]];
152 dcache_size_line [i] = new uint32_t [dcache_nb_level[i]];
153 dcache_size_word [i] = new uint32_t [dcache_nb_level[i]];
154 dcache_associativity [i] = new uint32_t [dcache_nb_level[i]];
155 dcache_hit_latence [i] = new uint32_t [dcache_nb_level[i]];
156 dcache_miss_penality [i] = new uint32_t [dcache_nb_level[i]];
157
158 for (uint32_t j=0; j<icache_nb_level[i]; ++j)
159 {
160 icache_nb_line [i][j] = cache_nb_line ;
161 icache_size_line [i][j] = cache_size_line ;
162 icache_size_word [i][j] = cache_size_word ;
163 icache_associativity [i][j] = cache_associativity;
164 icache_hit_latence [i][j] = cache_hit_latence ;
165 icache_miss_penality [i][j] = cache_miss_penality;
166
167 dcache_nb_line [i][j] = cache_nb_line ;
168 dcache_size_line [i][j] = cache_size_line ;
169 dcache_size_word [i][j] = cache_size_word ;
170 dcache_associativity [i][j] = cache_associativity;
171 dcache_hit_latence [i][j] = cache_hit_latence ;
172 dcache_miss_penality [i][j] = cache_miss_penality;
173
174 cache_nb_line *= cache_ratio;
175 cache_size_line *= cache_ratio;
176// cache_size_word *= cache_ratio;
177 cache_associativity *= cache_ratio;
178 cache_hit_latence *= cache_ratio;
179 cache_miss_penality *= cache_ratio;
180 }
181 }
182
183 // Cache shared
184 uint32_t * cache_shared_nb_line = new uint32_t [nb_cache_shared];
185 uint32_t * cache_shared_size_line = new uint32_t [nb_cache_shared];
186 uint32_t * cache_shared_size_word = new uint32_t [nb_cache_shared];
187 uint32_t * cache_shared_associativity = new uint32_t [nb_cache_shared];
188 uint32_t * cache_shared_hit_latence = new uint32_t [nb_cache_shared];
189 uint32_t * cache_shared_miss_penality = new uint32_t [nb_cache_shared];
190
191 for (uint32_t i=0; i<nb_cache_shared; ++i)
192 {
193 cache_shared_nb_line [i] = cache_nb_line ;
194 cache_shared_size_line [i] = cache_size_line ;
195 cache_shared_size_word [i] = cache_size_word ;
196 cache_shared_associativity [i] = cache_associativity;
197 cache_shared_hit_latence [i] = cache_hit_latence ;
198 cache_shared_miss_penality [i] = cache_miss_penality;
199
200 cache_nb_line *= cache_ratio;
201 cache_size_line *= cache_ratio;
202// cache_size_word *= cache_ratio;
203 cache_associativity *= cache_ratio;
204 cache_hit_latence *= cache_ratio;
205 cache_miss_penality *= cache_ratio;
206 }
207
208 // TTY
209 uint32_t nb_component_tty = 1;
210 uint32_t * tty_address = new uint32_t [nb_component_tty];
211 uint32_t * nb_tty = new uint32_t [nb_component_tty];
212 for (uint32_t i=0; i<nb_component_tty; ++i)
213 {
214 tty_address [i] = TTY_BASE;
215 nb_tty [i] = nb_thread;
216 }
217 string ** name_tty = new string * [nb_component_tty];
218 for (uint32_t i=0; i<nb_component_tty; ++i)
219 {
220 name_tty [i] = new string [nb_tty[i]];
221 for (uint32_t j=0; j<nb_tty[i]; ++j)
222 name_tty [i][j] = "tty_"+toString(i)+"_"+toString(j);
223 }
224
225 // Ramlock
226 uint32_t nb_component_ramlock = 1;
227 uint32_t * ramlock_address = new uint32_t [nb_component_ramlock];
228 uint32_t * nb_lock = new uint32_t [nb_component_ramlock];
229 for (uint32_t i=0; i<nb_component_ramlock; ++i)
230 {
231 ramlock_address [i] = RAMLOCK_BASE;
232 nb_lock [i] = 100*nb_thread;
233 }
234
235 // Sim2OS
236 uint32_t sim2os_address = SIM2OS_BASE;
237 uint32_t sim2os_size = SIM2OS_SIZE;
238
239 SOCLIB_SEGMENT_TABLE * segtable = new SOCLIB_SEGMENT_TABLE;
240 segtable->setMSBNumber (8);
241 segtable->setDefaultTarget(0,0);
242
243 // Add a segment ,name ,address of base ,size ,global index,local index,uncache
244 segtable->addSegment("text" ,TEXT_BASE ,TEXT_SIZE ,0 ,0 ,false);
245 segtable->addSegment("data" ,DATA_CACHED_BASE ,DATA_CACHED_SIZE ,0 ,0 ,false);
246 segtable->addSegment("data_stack" ,DATA_STACK_BASE ,DATA_STACK_SIZE ,0 ,0 ,false);
247 segtable->addSegment("data_unc" ,DATA_UNCACHED_BASE,DATA_UNCACHED_SIZE,0 ,0 ,true );
248
249 Parameters * param_environment = new Parameters
250 (nb_thread,
251 nb_entity,
252
253 iaccess_nb_context,
254 iaccess_nb_instruction,
255 iaccess_nb_packet,
256 iaccess_size_address,
257 iaccess_size_data,
258
259 daccess_nb_context,
260 daccess_nb_packet,
261 daccess_size_address,
262 daccess_size_data,
263
264 buffer_irsp_size,
265 buffer_drsp_size,
266
267 icache_nb_level ,
268 icache_nb_port ,
269 icache_nb_line ,
270 icache_size_line ,
271 icache_size_word ,
272 icache_associativity,
273 icache_hit_latence ,
274 icache_miss_penality,
275 dcache_nb_level ,
276 dcache_nb_port ,
277 dcache_nb_line ,
278 dcache_size_line ,
279 dcache_size_word ,
280 dcache_associativity,
281 dcache_hit_latence ,
282 dcache_miss_penality,
283
284 nb_cache_shared ,
285// cache_shared_nb_port ,
286 cache_shared_nb_line ,
287 cache_shared_size_line ,
288 cache_shared_size_word ,
289 cache_shared_associativity ,
290 cache_shared_hit_latence ,
291 cache_shared_miss_penality ,
292
293 nb_component_tty,
294 tty_address,
295 nb_tty,
296 name_tty,
297 false,
298
299 nb_component_ramlock,
300 ramlock_address,
301 nb_lock,
302
303 sim2os_address,
304 sim2os_size,
305 segtable
306 );
307
308// cout << param_environment->print(0) << endl;
309
310 segtable->print();
311
312 Environment * environment = new Environment ("environment",param_environment);
313
314 const char * sections_text [] = {".text",NULL};
315 const char * sections_data [] = {".data",".rodata",".bss",".sdata",".sbss", NULL};
316
317 if (environment->init("text" , filename_software.c_str(), sections_text) == false) exit (EXIT_FAILURE);
318 if (environment->init("data" , filename_software.c_str(), sections_data) == false) exit (EXIT_FAILURE);
319
320 //==============================================================================
321 //===== [ SIGNAL ]==============================================================
322 //==============================================================================
323
324 sc_time period (TIME_PERIOD, TIME_UNIT);
325 sc_clock * CLOCK = new sc_clock ("clock", period);
326 sc_signal<Tcontrol_t> * NRESET = new sc_signal<Tcontrol_t> ("NRESET");
327
328 sc_signal<Tcontrol_t > ** ICACHE_REQ_VAL ;
329 sc_signal<Tcontrol_t > ** ICACHE_REQ_ACK ;
330 sc_signal<Ticache_context_t > ** ICACHE_REQ_THREAD_ID ;
331 sc_signal<Ticache_packet_t > ** ICACHE_REQ_PACKET_ID ;
332 sc_signal<Ticache_address_t > ** ICACHE_REQ_ADDRESS ;
333 sc_signal<Ticache_type_t > ** ICACHE_REQ_TYPE ;
334
335 sc_signal<Tcontrol_t > ** ICACHE_RSP_VAL ;
336 sc_signal<Tcontrol_t > ** ICACHE_RSP_ACK ;
337 sc_signal<Ticache_context_t > ** ICACHE_RSP_THREAD_ID ;
338 sc_signal<Ticache_packet_t > ** ICACHE_RSP_PACKET_ID ;
339 sc_signal<Ticache_instruction_t> *** ICACHE_RSP_INSTRUCTION;
340 sc_signal<Ticache_error_t > ** ICACHE_RSP_ERROR ;
341
342 sc_signal<Tcontrol_t > ** DCACHE_REQ_VAL ;
343 sc_signal<Tcontrol_t > ** DCACHE_REQ_ACK ;
344 sc_signal<Tdcache_context_t > ** DCACHE_REQ_THREAD_ID ;
345 sc_signal<Tdcache_packet_t > ** DCACHE_REQ_PACKET_ID ;
346 sc_signal<Tdcache_address_t > ** DCACHE_REQ_ADDRESS ;
347 sc_signal<Tdcache_data_t > ** DCACHE_REQ_WDATA ;
348 sc_signal<Tdcache_type_t > ** DCACHE_REQ_TYPE ;
349
350 sc_signal<Tcontrol_t > ** DCACHE_RSP_VAL ;
351 sc_signal<Tcontrol_t > ** DCACHE_RSP_ACK ;
352 sc_signal<Tdcache_context_t > ** DCACHE_RSP_THREAD_ID ;
353 sc_signal<Tdcache_packet_t > ** DCACHE_RSP_PACKET_ID ;
354 sc_signal<Tdcache_data_t > ** DCACHE_RSP_RDATA ;
355 sc_signal<Tdcache_error_t > ** DCACHE_RSP_ERROR ;
356
357 sc_signal<Tcontrol_t > ** INTERRUPT_ENABLE ;
358
359 ALLOC1_SC_SIGNAL(ICACHE_REQ_VAL ,"ICACHE_REQ_VAL ",Tcontrol_t ,morpheo->_nb_icache_port);
360 ALLOC1_SC_SIGNAL(ICACHE_REQ_ACK ,"ICACHE_REQ_ACK ",Tcontrol_t ,morpheo->_nb_icache_port);
361 ALLOC1_SC_SIGNAL(ICACHE_REQ_THREAD_ID ,"ICACHE_REQ_THREAD_ID ",Ticache_context_t ,morpheo->_nb_icache_port);
362 ALLOC1_SC_SIGNAL(ICACHE_REQ_PACKET_ID ,"ICACHE_REQ_PACKET_ID ",Ticache_packet_t ,morpheo->_nb_icache_port);
363 ALLOC1_SC_SIGNAL(ICACHE_REQ_ADDRESS ,"ICACHE_REQ_ADDRESS ",Ticache_address_t ,morpheo->_nb_icache_port);
364 ALLOC1_SC_SIGNAL(ICACHE_REQ_TYPE ,"ICACHE_REQ_TYPE ",Ticache_type_t ,morpheo->_nb_icache_port);
365
366 ALLOC1_SC_SIGNAL(ICACHE_RSP_VAL ,"ICACHE_RSP_VAL ",Tcontrol_t ,morpheo->_nb_icache_port);
367 ALLOC1_SC_SIGNAL(ICACHE_RSP_ACK ,"ICACHE_RSP_ACK ",Tcontrol_t ,morpheo->_nb_icache_port);
368 ALLOC1_SC_SIGNAL(ICACHE_RSP_THREAD_ID ,"ICACHE_RSP_THREAD_ID ",Ticache_context_t ,morpheo->_nb_icache_port);
369 ALLOC1_SC_SIGNAL(ICACHE_RSP_PACKET_ID ,"ICACHE_RSP_PACKET_ID ",Ticache_packet_t ,morpheo->_nb_icache_port);
370 ALLOC2_SC_SIGNAL(ICACHE_RSP_INSTRUCTION ,"ICACHE_RSP_INSTRUCTION",Ticache_instruction_t,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]);
371 ALLOC1_SC_SIGNAL(ICACHE_RSP_ERROR ,"ICACHE_RSP_ERROR ",Ticache_error_t ,morpheo->_nb_icache_port);
372
373 ALLOC1_SC_SIGNAL(DCACHE_REQ_VAL ,"DCACHE_REQ_VAL ",Tcontrol_t ,morpheo->_nb_dcache_port);
374 ALLOC1_SC_SIGNAL(DCACHE_REQ_ACK ,"DCACHE_REQ_ACK ",Tcontrol_t ,morpheo->_nb_dcache_port);
375 ALLOC1_SC_SIGNAL(DCACHE_REQ_THREAD_ID ,"DCACHE_REQ_THREAD_ID ",Tdcache_context_t ,morpheo->_nb_dcache_port);
376 ALLOC1_SC_SIGNAL(DCACHE_REQ_PACKET_ID ,"DCACHE_REQ_PACKET_ID ",Tdcache_packet_t ,morpheo->_nb_dcache_port);
377 ALLOC1_SC_SIGNAL(DCACHE_REQ_ADDRESS ,"DCACHE_REQ_ADDRESS ",Tdcache_address_t ,morpheo->_nb_dcache_port);
378 ALLOC1_SC_SIGNAL(DCACHE_REQ_WDATA ,"DCACHE_REQ_WDATA ",Tdcache_data_t ,morpheo->_nb_dcache_port);
379 ALLOC1_SC_SIGNAL(DCACHE_REQ_TYPE ,"DCACHE_REQ_TYPE ",Tdcache_type_t ,morpheo->_nb_dcache_port);
380
381 ALLOC1_SC_SIGNAL(DCACHE_RSP_VAL ,"DCACHE_RSP_VAL ",Tcontrol_t ,morpheo->_nb_dcache_port);
382 ALLOC1_SC_SIGNAL(DCACHE_RSP_ACK ,"DCACHE_RSP_ACK ",Tcontrol_t ,morpheo->_nb_dcache_port);
383 ALLOC1_SC_SIGNAL(DCACHE_RSP_THREAD_ID ,"DCACHE_RSP_THREAD_ID ",Tdcache_context_t ,morpheo->_nb_dcache_port);
384 ALLOC1_SC_SIGNAL(DCACHE_RSP_PACKET_ID ,"DCACHE_RSP_PACKET_ID ",Tdcache_packet_t ,morpheo->_nb_dcache_port);
385 ALLOC1_SC_SIGNAL(DCACHE_RSP_RDATA ,"DCACHE_RSP_RDATA ",Tdcache_data_t ,morpheo->_nb_dcache_port);
386 ALLOC1_SC_SIGNAL(DCACHE_RSP_ERROR ,"DCACHE_RSP_ERROR ",Tdcache_error_t ,morpheo->_nb_dcache_port);
387
388 ALLOC1_SC_SIGNAL(INTERRUPT_ENABLE ,"INTERRUPT_ENABLE ",Tcontrol_t ,morpheo->_nb_thread);
389
390 //==============================================================================
391 //===== [ INSTANCE ]============================================================
392 //==============================================================================
393
394 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
395 //~~~~~ [ Morpheo ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
396 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
397
398 (*(morpheo->in_CLOCK)) (*(CLOCK));
399 (*(morpheo->in_NRESET)) (*(NRESET));
400
401 _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_VAL ,ICACHE_REQ_VAL ,morpheo->_nb_icache_port);
402 _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_REQ_ACK ,ICACHE_REQ_ACK ,morpheo->_nb_icache_port);
403 if (morpheo->_have_port_icache_thread_id)
404 _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_THREAD_ID ,ICACHE_REQ_THREAD_ID ,morpheo->_nb_icache_port);
405 if (morpheo->_have_port_icache_packet_id)
406 _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_PACKET_ID ,ICACHE_REQ_PACKET_ID ,morpheo->_nb_icache_port);
407 _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_ADDRESS ,ICACHE_REQ_ADDRESS ,morpheo->_nb_icache_port);
408 _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_TYPE ,ICACHE_REQ_TYPE ,morpheo->_nb_icache_port);
409
410 _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_VAL ,ICACHE_RSP_VAL ,morpheo->_nb_icache_port);
411 _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_RSP_ACK ,ICACHE_RSP_ACK ,morpheo->_nb_icache_port);
412 if (morpheo->_have_port_icache_thread_id)
413 _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_THREAD_ID ,ICACHE_RSP_THREAD_ID ,morpheo->_nb_icache_port);
414 if (morpheo->_have_port_icache_packet_id)
415 _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_PACKET_ID ,ICACHE_RSP_PACKET_ID ,morpheo->_nb_icache_port);
416 _INSTANCE2_SC_SIGNAL(morpheo, in_ICACHE_RSP_INSTRUCTION ,ICACHE_RSP_INSTRUCTION ,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]);
417 _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_ERROR ,ICACHE_RSP_ERROR ,morpheo->_nb_icache_port);
418
419 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_VAL ,DCACHE_REQ_VAL ,morpheo->_nb_dcache_port);
420 _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_REQ_ACK ,DCACHE_REQ_ACK ,morpheo->_nb_dcache_port);
421 if (morpheo->_have_port_dcache_thread_id)
422 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_THREAD_ID ,DCACHE_REQ_THREAD_ID ,morpheo->_nb_dcache_port);
423 if (morpheo->_have_port_dcache_packet_id)
424 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_PACKET_ID ,DCACHE_REQ_PACKET_ID ,morpheo->_nb_dcache_port);
425 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_ADDRESS ,DCACHE_REQ_ADDRESS ,morpheo->_nb_dcache_port);
426 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_WDATA ,DCACHE_REQ_WDATA ,morpheo->_nb_dcache_port);
427 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_TYPE ,DCACHE_REQ_TYPE ,morpheo->_nb_dcache_port);
428
429 _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_VAL ,DCACHE_RSP_VAL ,morpheo->_nb_dcache_port);
430 _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_RSP_ACK ,DCACHE_RSP_ACK ,morpheo->_nb_dcache_port);
431 if (morpheo->_have_port_dcache_thread_id)
432 _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_THREAD_ID ,DCACHE_RSP_THREAD_ID ,morpheo->_nb_dcache_port);
433 if (morpheo->_have_port_dcache_packet_id)
434 _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_PACKET_ID ,DCACHE_RSP_PACKET_ID ,morpheo->_nb_dcache_port);
435 _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_RDATA ,DCACHE_RSP_RDATA ,morpheo->_nb_dcache_port);
436 _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_ERROR ,DCACHE_RSP_ERROR ,morpheo->_nb_dcache_port);
437
438 _INSTANCE1_SC_SIGNAL(morpheo, in_INTERRUPT_ENABLE ,INTERRUPT_ENABLE ,morpheo->_nb_thread);
439
440 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
441 //~~~~~ [ Environment ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
442 //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
443
444 (*(environment->CLOCK)) (*(CLOCK));
445 (*(environment->NRESET)) (*(NRESET));
446
447 for (uint32_t i=0; i<morpheo->_nb_icache_port; ++i)
448 {
449 (*(environment->ICACHE_REQ_VAL [0][i] )) (*(ICACHE_REQ_VAL [i] ));
450 (*(environment->ICACHE_REQ_ACK [0][i] )) (*(ICACHE_REQ_ACK [i] ));
451 (*(environment->ICACHE_REQ_CONTEXT_ID [0][i] )) (*(ICACHE_REQ_THREAD_ID [i] ));
452 (*(environment->ICACHE_REQ_PACKET_ID [0][i] )) (*(ICACHE_REQ_PACKET_ID [i] ));
453 (*(environment->ICACHE_REQ_ADDRESS [0][i] )) (*(ICACHE_REQ_ADDRESS [i] ));
454 (*(environment->ICACHE_REQ_TYPE [0][i] )) (*(ICACHE_REQ_TYPE [i] ));
455
456 (*(environment->ICACHE_RSP_VAL [0][i] )) (*(ICACHE_RSP_VAL [i] ));
457 (*(environment->ICACHE_RSP_ACK [0][i] )) (*(ICACHE_RSP_ACK [i] ));
458 (*(environment->ICACHE_RSP_CONTEXT_ID [0][i] )) (*(ICACHE_RSP_THREAD_ID [i] ));
459 (*(environment->ICACHE_RSP_PACKET_ID [0][i] )) (*(ICACHE_RSP_PACKET_ID [i] ));
460 (*(environment->ICACHE_RSP_ERROR [0][i] )) (*(ICACHE_RSP_ERROR [i] ));
461
462 for (uint32_t j=0; j<morpheo->_icache_nb_instruction[i]; ++j)
463 (*(environment->ICACHE_RSP_INSTRUCTION [0][i][j])) (*(ICACHE_RSP_INSTRUCTION [i][j]));
464 }
465 for (uint32_t i=0; i<morpheo->_nb_dcache_port; ++i)
466 {
467 (*(environment->DCACHE_REQ_VAL [0][i] )) (*(DCACHE_REQ_VAL [i] ));
468 (*(environment->DCACHE_REQ_ACK [0][i] )) (*(DCACHE_REQ_ACK [i] ));
469 (*(environment->DCACHE_REQ_CONTEXT_ID [0][i] )) (*(DCACHE_REQ_THREAD_ID [i] ));
470 (*(environment->DCACHE_REQ_PACKET_ID [0][i] )) (*(DCACHE_REQ_PACKET_ID [i] ));
471 (*(environment->DCACHE_REQ_ADDRESS [0][i] )) (*(DCACHE_REQ_ADDRESS [i] ));
472 (*(environment->DCACHE_REQ_WDATA [0][i] )) (*(DCACHE_REQ_WDATA [i] ));
473 (*(environment->DCACHE_REQ_TYPE [0][i] )) (*(DCACHE_REQ_TYPE [i] ));
474
475 (*(environment->DCACHE_RSP_VAL [0][i] )) (*(DCACHE_RSP_VAL [i] ));
476 (*(environment->DCACHE_RSP_ACK [0][i] )) (*(DCACHE_RSP_ACK [i] ));
477 (*(environment->DCACHE_RSP_CONTEXT_ID [0][i] )) (*(DCACHE_RSP_THREAD_ID [i] ));
478 (*(environment->DCACHE_RSP_PACKET_ID [0][i] )) (*(DCACHE_RSP_PACKET_ID [i] ));
479 (*(environment->DCACHE_RSP_RDATA [0][i] )) (*(DCACHE_RSP_RDATA [i] ));
480 (*(environment->DCACHE_RSP_ERROR [0][i] )) (*(DCACHE_RSP_ERROR [i] ));
481 }
482
483//_INSTANCE2_SC_SIGNAL(environment,INTERRUPT_ENABLE ,1,morpheo->_nb_thread);
484
485 //==============================================================================
486 //===== [ SIMULATION ]==========================================================
487 //==============================================================================
488
489 // initialisation
490
491 cerr << "<test> Simulation Init" << endl;
492
493// sc_time t (0, TIME_UNIT);
494// sc_start(t);
495
496 cerr << "<test> Simulation Start" << endl;
497
498 bool morpheo_error = false;
499 try
500 {
501 Time * _time_global = new Time();
502
503 for (uint32_t i=0; i<morpheo->_nb_thread; ++i)
504 INTERRUPT_ENABLE[i]->write(0);
505
506 NRESET->write(0);
507 SC_START(5);
508 NRESET->write(1);
509
510 // Infinite loop
511 do
512 {
513 // Time * _time_local = new Time();
514 SC_START(100000);
515 // delete _time_local;
516 } while (not morpheo ->simulation_end() and // morpheo condition stop
517 not environment->simulation_end()); // test ok
518 delete _time_global;
519 }
520 catch (morpheo::ErrorMorpheo & error)
521 {
522 std::cerr << error.what() << std::endl
523 << STR_KO << std::endl;
524
525 morpheo_error = true;
526 }
527
528 bool morpheo_end = morpheo->simulation_end();
529 bool environment_end = environment->simulation_end();
530
531
532 //==============================================================================
533 //===== [ DESTRUCTION ]=========================================================
534 //==============================================================================
535
536 delete CLOCK;
537 delete NRESET;
538
539 DELETE1_SC_SIGNAL(ICACHE_REQ_VAL ,morpheo->_nb_icache_port);
540 DELETE1_SC_SIGNAL(ICACHE_REQ_ACK ,morpheo->_nb_icache_port);
541 DELETE1_SC_SIGNAL(ICACHE_REQ_THREAD_ID ,morpheo->_nb_icache_port);
542 DELETE1_SC_SIGNAL(ICACHE_REQ_PACKET_ID ,morpheo->_nb_icache_port);
543 DELETE1_SC_SIGNAL(ICACHE_REQ_ADDRESS ,morpheo->_nb_icache_port);
544 DELETE1_SC_SIGNAL(ICACHE_REQ_TYPE ,morpheo->_nb_icache_port);
545
546 DELETE1_SC_SIGNAL(ICACHE_RSP_VAL ,morpheo->_nb_icache_port);
547 DELETE1_SC_SIGNAL(ICACHE_RSP_ACK ,morpheo->_nb_icache_port);
548 DELETE1_SC_SIGNAL(ICACHE_RSP_THREAD_ID ,morpheo->_nb_icache_port);
549 DELETE1_SC_SIGNAL(ICACHE_RSP_PACKET_ID ,morpheo->_nb_icache_port);
550 DELETE1_SC_SIGNAL(ICACHE_RSP_ERROR ,morpheo->_nb_icache_port);
551 DELETE2_SC_SIGNAL(ICACHE_RSP_INSTRUCTION ,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]);
552
553 DELETE1_SC_SIGNAL(DCACHE_REQ_VAL ,morpheo->_nb_dcache_port);
554 DELETE1_SC_SIGNAL(DCACHE_REQ_ACK ,morpheo->_nb_dcache_port);
555 DELETE1_SC_SIGNAL(DCACHE_REQ_THREAD_ID ,morpheo->_nb_dcache_port);
556 DELETE1_SC_SIGNAL(DCACHE_REQ_PACKET_ID ,morpheo->_nb_dcache_port);
557 DELETE1_SC_SIGNAL(DCACHE_REQ_ADDRESS ,morpheo->_nb_dcache_port);
558 DELETE1_SC_SIGNAL(DCACHE_REQ_WDATA ,morpheo->_nb_dcache_port);
559 DELETE1_SC_SIGNAL(DCACHE_REQ_TYPE ,morpheo->_nb_dcache_port);
560
561 DELETE1_SC_SIGNAL(DCACHE_RSP_VAL ,morpheo->_nb_dcache_port);
562 DELETE1_SC_SIGNAL(DCACHE_RSP_ACK ,morpheo->_nb_dcache_port);
563 DELETE1_SC_SIGNAL(DCACHE_RSP_THREAD_ID ,morpheo->_nb_dcache_port);
564 DELETE1_SC_SIGNAL(DCACHE_RSP_PACKET_ID ,morpheo->_nb_dcache_port);
565 DELETE1_SC_SIGNAL(DCACHE_RSP_RDATA ,morpheo->_nb_dcache_port);
566 DELETE1_SC_SIGNAL(DCACHE_RSP_ERROR ,morpheo->_nb_dcache_port);
567
568 DELETE1_SC_SIGNAL(INTERRUPT_ENABLE ,morpheo->_nb_thread);
569
570 delete environment;
571
572 delete param_environment;
573 delete segtable;
574
575 delete [] nb_lock ;
576 delete [] ramlock_address;
577
578 for (uint32_t i=0;i<nb_component_tty;++i)
579 delete [] name_tty [i];
580 delete [] name_tty;
581 delete [] nb_tty;
582 delete [] tty_address;
583
584 delete [] cache_shared_miss_penality;
585 delete [] cache_shared_hit_latence ;
586 delete [] cache_shared_associativity;
587 delete [] cache_shared_size_word ;
588 delete [] cache_shared_size_line ;
589 delete [] cache_shared_nb_line ;
590
591 for (uint32_t i=0; i<nb_entity; i++)
592 {
593 delete [] dcache_miss_penality [i];
594 delete [] dcache_hit_latence [i];
595 delete [] dcache_associativity [i];
596 delete [] dcache_size_word [i];
597 delete [] dcache_size_line [i];
598 delete [] dcache_nb_line [i];
599 }
600 delete [] dcache_miss_penality ;
601 delete [] dcache_hit_latence ;
602 delete [] dcache_associativity ;
603 delete [] dcache_size_word ;
604 delete [] dcache_size_line ;
605 delete [] dcache_nb_line ;
606 delete [] dcache_nb_level ;
607 delete [] dcache_nb_port ;
608
609 for (uint32_t i=0; i<nb_entity; i++)
610 {
611 delete [] icache_miss_penality [i];
612 delete [] icache_hit_latence [i];
613 delete [] icache_associativity [i];
614 delete [] icache_size_word [i];
615 delete [] icache_size_line [i];
616 delete [] icache_nb_line [i];
617 }
618 delete [] icache_miss_penality;
619 delete [] icache_hit_latence ;
620 delete [] icache_associativity;
621 delete [] icache_size_word ;
622 delete [] icache_size_line ;
623 delete [] icache_nb_line ;
624 delete [] icache_nb_level ;
625 delete [] icache_nb_port ;
626
627 delete [] buffer_drsp_size ;
628 delete [] buffer_irsp_size ;
629 delete [] daccess_size_data ;
630 delete [] daccess_size_address ;
631 delete [] daccess_nb_packet ;
632 delete [] daccess_nb_context ;
633 delete [] iaccess_size_data ;
634 delete [] iaccess_size_address ;
635 delete [] iaccess_nb_packet ;
636 delete [] iaccess_nb_instruction;
637 delete [] iaccess_nb_context ;
638
639 delete morpheo;
640
641 bool test_ok = false;
642 if (not morpheo_error)
643 {
644 if (not morpheo_end and not environment_end)
645 {
646 cerr << "<test> Simulation End : Unknow" << endl;
647 }
648 else
649 {
650 if (morpheo_end)
651 {
652 cout << "<test> Simulation End : MORPHEO" << endl;
653 test_ok = true;
654 }
655 if (environment_end)
656 {
657 cout << "<test> Simulation End : ENVIRONMENT" << endl;
658 test_ok = true;
659 }
660 }
661 }
662
663 if (test_ok)
664 {
665 cout << STR_OK << endl;
666 return EXIT_SUCCESS;
667 }
668 else
669 {
670 cout << STR_KO << endl;
671 return EXIT_FAILURE;
672 }
673}
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