source: trunk/Softwares/Test/Test_012/src/sys/crt0.s @ 102

/*
 * Test_012
 *
 * end_ko : infinite_loop
 * end_ok : Write in R1 the stop address and stop an data
 *          The store in the destination of an jump
 * start  : Test l.addic
 */
        
        .file   "crt0.s"
        /*
        .section .vector
        */
        .section .text
        .align  4       

/* ---[ 0x0  : Print a error ]------------------------------------------- */

        .org 0x0
_end_ko        :        
        l.movhi r1,     hi(_tty)
        l.ori   r1, r1, lo(_tty)
        l.sw    4(r1), r1 /* stop address */
_infinite_loop :        
        l.j     _infinite_loop
        l.nop

_end_ok :
        l.movhi r1,     hi(_tty)
        l.ori   r1, r1, lo(_tty)
        l.sw    4(r1), r0 /* stop address */


/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        .global _start
_start:
        /*
             A (r1)     B (I)  - D (r3 wait)CY OV (SR = r6, mask SR = r5)
                                       (r4)                (r7)
          1) 0x00000000 0x0000 - 0x00000000 0  0
          2) 0x14011959 0x1959 - 0x140132b2 0  0
          3) 0xebfee6a7 0xe6a7 - 0xebfecd4e 1  0
          4) 0xebfee6a7 0x1959 - 0xebff0001 0  0
          5) 0x14011959 0xe6a7 - 0x14010000 1  0
          6) 0x87654321 0xabcd - 0x8764eeef 1  0
          7) 0x7fffffff 0x5432 - 0x80005432 0  1
          */

        /* Mask to read OV (SR[11]), CY (SR[10]) and not F (SR[9]) */
        l.movhi r5,     hi(0x00000c00)
        l.ori   r5, r5, lo(0x00000c00)
        
        /**********/
        /* Test 1 */
        /**********/
        l.movhi r1,     hi(0x00000000) /* RA */
        l.ori   r1, r1, lo(0x00000000)
        l.movhi r3,     hi(0x00000000) /* RD wait */
        l.ori   r3, r3, lo(0x00000000)
        l.movhi r6,     hi(0x00000000) /* SR wait */
        l.ori   r6, r6, lo(0x00000000)
        
        l.addic r4, r1, 0x0000

        /* Test flag */
        l.mfspr r7, r0, 17
        l.and   r7, r7, r5

        l.sfeq  r6, r7
        l.bnf   _end_ko
        l.nop

        /* Test result */
        l.sfeq  r3, r4
        l.bnf   _end_ko
        l.nop

        /**********/
        /* Test 2 */
        /**********/
        l.movhi r1,     hi(0x14011959) /* RA */
        l.ori   r1, r1, lo(0x14011959)
        l.movhi r3,     hi(0x140132b2) /* RD wait */
        l.ori   r3, r3, lo(0x140132b2)
        l.movhi r6,     hi(0x00000000) /* SR wait */
        l.ori   r6, r6, lo(0x00000000)
        
        l.addic r4, r1, 0x1959

        /* Test flag */
        l.mfspr r7, r0, 17
        l.and   r7, r7, r5

        l.sfeq  r6, r7
        l.bnf   _end_ko
        l.nop

        /* Test result */
        l.sfeq  r3, r4
        l.bnf   _end_ko
        l.nop

        /**********/
        /* Test 3 */
        /**********/
        l.movhi r1,     hi(0xebfee6a7) /* RA */
        l.ori   r1, r1, lo(0xebfee6a7)
        l.movhi r3,     hi(0xebfecd4e) /* RD wait */
        l.ori   r3, r3, lo(0xebfecd4e)
        l.movhi r6,     hi(0x00000400) /* SR wait */
        l.ori   r6, r6, lo(0x00000400)
        
        l.addic r4, r1, 0xe6a7

        /* Test flag */
        l.mfspr r7, r0, 17
        l.and   r7, r7, r5

        l.sfeq  r6, r7
        l.bnf   _end_ko
        l.nop

        /* Test result */
        l.sfeq  r3, r4
        l.bnf   _end_ko
        l.nop

        /**********/
        /* Test 4 */
        /**********/
        l.movhi r1,     hi(0xebfee6a7) /* RA */
        l.ori   r1, r1, lo(0xebfee6a7)
        l.movhi r3,     hi(0xebff0001) /* RD wait */
        l.ori   r3, r3, lo(0xebff0001)
        l.movhi r6,     hi(0x00000000) /* SR wait */
        l.ori   r6, r6, lo(0x00000000)
        
        l.addic r4, r1, 0x1959

        /* Test flag */
        l.mfspr r7, r0, 17
        l.and   r7, r7, r5

        l.sfeq  r6, r7
        l.bnf   _end_ko
        l.nop

        /* Test result */
        l.sfeq  r3, r4
        l.bnf   _end_ko
        l.nop

        /**********/
        /* Test 5 */
        /**********/
        l.movhi r1,     hi(0x14011959) /* RA */
        l.ori   r1, r1, lo(0x14011959)
        l.movhi r3,     hi(0x14010000) /* RD wait */
        l.ori   r3, r3, lo(0x14010000)
        l.movhi r6,     hi(0x00000400) /* SR wait */
        l.ori   r6, r6, lo(0x00000400)
        
        l.addic r4, r1, 0xe6a7

        /* Test flag */
        l.mfspr r7, r0, 17
        l.and   r7, r7, r5

        l.sfeq  r6, r7
        l.bnf   _end_ko
        l.nop

        /* Test result */
        l.sfeq  r3, r4
        l.bnf   _end_ko
        l.nop

        /**********/
        /* Test 6 */
        /**********/
        l.movhi r1,     hi(0x87654321) /* RA */
        l.ori   r1, r1, lo(0x87654321)
        l.movhi r3,     hi(0x8764eeef) /* RD wait */
        l.ori   r3, r3, lo(0x8764eeef)
        l.movhi r6,     hi(0x00000400) /* SR wait */
        l.ori   r6, r6, lo(0x00000400)
        
        l.addic r4, r1, 0xabcd

        /* Test flag */
        l.mfspr r7, r0, 17
        l.and   r7, r7, r5

        l.sfeq  r6, r7
        l.bnf   _end_ko
        l.nop

        /* Test result */
        l.sfeq  r3, r4
        l.bnf   _end_ko
        l.nop

        /**********/
        /* Test 7 */
        /**********/
        l.movhi r1,     hi(0x7fffffff) /* RA */
        l.ori   r1, r1, lo(0x7fffffff)
        l.movhi r3,     hi(0x80005432) /* RD wait */
        l.ori   r3, r3, lo(0x80005432)
        l.movhi r6,     hi(0x00000800) /* SR wait */
        l.ori   r6, r6, lo(0x00000800)
        
        l.addic r4, r1, 0x5432

        /* Test flag */
        l.mfspr r7, r0, 17
        l.and   r7, r7, r5

        l.sfeq  r6, r7
        l.bnf   _end_ko
        l.nop

        /* Test result */
        l.sfeq  r3, r4
        l.bnf   _end_ko
        l.nop

        /**********/
        /* End */
        /**********/

        l.j     _end_ok
        l.nop