
bin/soft.x:     file format elf32-or32

Disassembly of section .text:

00000000 <_exception_reset-0x100>:
       0:	15 00 00 00 	l.nop 0x0
       4:	15 00 ff ff 	l.nop 0xffff
       8:	15 00 ff fe 	l.nop 0xfffe
       c:	15 00 ff fd 	l.nop 0xfffd
      10:	15 00 ff fc 	l.nop 0xfffc
      14:	15 00 ff fb 	l.nop 0xfffb
      18:	15 00 ff fa 	l.nop 0xfffa
      1c:	15 00 ff f9 	l.nop 0xfff9
      20:	15 00 ff f8 	l.nop 0xfff8
      24:	15 00 ff f7 	l.nop 0xfff7
      28:	15 00 ff f6 	l.nop 0xfff6
      2c:	15 00 ff f5 	l.nop 0xfff5
      30:	15 00 ff f4 	l.nop 0xfff4
      34:	15 00 ff f3 	l.nop 0xfff3
      38:	15 00 ff f2 	l.nop 0xfff2
      3c:	15 00 ff f1 	l.nop 0xfff1
      40:	15 00 ff f0 	l.nop 0xfff0
      44:	15 00 ff ef 	l.nop 0xffef
      48:	15 00 ff ee 	l.nop 0xffee
      4c:	15 00 ff ed 	l.nop 0xffed
      50:	15 00 ff ec 	l.nop 0xffec
      54:	15 00 ff eb 	l.nop 0xffeb
      58:	15 00 ff ea 	l.nop 0xffea
      5c:	15 00 ff e9 	l.nop 0xffe9
      60:	15 00 ff e8 	l.nop 0xffe8
      64:	15 00 ff e7 	l.nop 0xffe7
      68:	15 00 ff e6 	l.nop 0xffe6
      6c:	15 00 ff e5 	l.nop 0xffe5
      70:	15 00 ff e4 	l.nop 0xffe4
      74:	15 00 ff e3 	l.nop 0xffe3
      78:	15 00 ff e2 	l.nop 0xffe2
      7c:	15 00 ff e1 	l.nop 0xffe1
      80:	15 00 ff e0 	l.nop 0xffe0
      84:	15 00 ff df 	l.nop 0xffdf
      88:	15 00 ff de 	l.nop 0xffde
      8c:	15 00 ff dd 	l.nop 0xffdd
      90:	15 00 ff dc 	l.nop 0xffdc
      94:	15 00 ff db 	l.nop 0xffdb
      98:	15 00 ff da 	l.nop 0xffda
      9c:	15 00 ff d9 	l.nop 0xffd9
      a0:	15 00 ff d8 	l.nop 0xffd8
      a4:	15 00 ff d7 	l.nop 0xffd7
      a8:	15 00 ff d6 	l.nop 0xffd6
      ac:	15 00 ff d5 	l.nop 0xffd5
      b0:	15 00 ff d4 	l.nop 0xffd4
      b4:	15 00 ff d3 	l.nop 0xffd3
      b8:	15 00 ff d2 	l.nop 0xffd2
      bc:	15 00 ff d1 	l.nop 0xffd1
      c0:	15 00 ff d0 	l.nop 0xffd0
      c4:	15 00 ff cf 	l.nop 0xffcf
      c8:	15 00 ff ce 	l.nop 0xffce
      cc:	15 00 ff cd 	l.nop 0xffcd
      d0:	15 00 ff cc 	l.nop 0xffcc
      d4:	15 00 ff cb 	l.nop 0xffcb
      d8:	15 00 ff ca 	l.nop 0xffca
      dc:	15 00 ff c9 	l.nop 0xffc9
      e0:	15 00 ff c8 	l.nop 0xffc8
      e4:	15 00 ff c7 	l.nop 0xffc7
      e8:	15 00 ff c6 	l.nop 0xffc6
      ec:	15 00 ff c5 	l.nop 0xffc5
      f0:	15 00 ff c4 	l.nop 0xffc4
      f4:	15 00 ff c3 	l.nop 0xffc3
      f8:	15 00 ff c2 	l.nop 0xffc2
      fc:	15 00 ff c1 	l.nop 0xffc1

00000100 <_exception_reset>:
     100:	18 40 00 00 	l.movhi r2,0x0
     104:	a8 42 20 00 	l.ori r2,r2,0x2000
     108:	44 00 10 00 	l.jr r2
     10c:	15 00 00 00 	l.nop 0x0
	...
     200:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     204:	d4 01 18 04 	l.sw 0x4(r1),r3
     208:	d4 01 20 08 	l.sw 0x8(r1),r4
     20c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     210:	b4 80 00 20 	l.mfspr r4,r0,0x20
     214:	00 00 07 88 	l.j 2034 <default_exception_handler>
     218:	15 00 00 00 	l.nop 0x0
	...
     300:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     304:	d4 01 18 04 	l.sw 0x4(r1),r3
     308:	d4 01 20 08 	l.sw 0x8(r1),r4
     30c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     310:	b4 80 00 20 	l.mfspr r4,r0,0x20
     314:	00 00 07 48 	l.j 2034 <default_exception_handler>
     318:	15 00 00 00 	l.nop 0x0
	...
     400:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     404:	d4 01 18 04 	l.sw 0x4(r1),r3
     408:	d4 01 20 08 	l.sw 0x8(r1),r4
     40c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     410:	b4 80 00 20 	l.mfspr r4,r0,0x20
     414:	00 00 07 08 	l.j 2034 <default_exception_handler>
     418:	15 00 00 00 	l.nop 0x0
	...
     500:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     504:	d4 01 18 04 	l.sw 0x4(r1),r3
     508:	d4 01 20 08 	l.sw 0x8(r1),r4
     50c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     510:	b4 80 00 20 	l.mfspr r4,r0,0x20
     514:	00 00 06 c8 	l.j 2034 <default_exception_handler>
     518:	15 00 00 00 	l.nop 0x0
	...
     600:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     604:	d4 01 18 04 	l.sw 0x4(r1),r3
     608:	d4 01 20 08 	l.sw 0x8(r1),r4
     60c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     610:	b4 80 00 20 	l.mfspr r4,r0,0x20
     614:	00 00 06 88 	l.j 2034 <default_exception_handler>
     618:	15 00 00 00 	l.nop 0x0
	...
     700:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     704:	d4 01 18 04 	l.sw 0x4(r1),r3
     708:	d4 01 20 08 	l.sw 0x8(r1),r4
     70c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     710:	b4 80 00 20 	l.mfspr r4,r0,0x20
     714:	00 00 06 48 	l.j 2034 <default_exception_handler>
     718:	15 00 00 00 	l.nop 0x0
	...
     800:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     804:	d4 01 18 04 	l.sw 0x4(r1),r3
     808:	d4 01 20 08 	l.sw 0x8(r1),r4
     80c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     810:	b4 80 00 20 	l.mfspr r4,r0,0x20
     814:	00 00 06 08 	l.j 2034 <default_exception_handler>
     818:	15 00 00 00 	l.nop 0x0
	...
     900:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     904:	d4 01 18 04 	l.sw 0x4(r1),r3
     908:	d4 01 20 08 	l.sw 0x8(r1),r4
     90c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     910:	b4 80 00 20 	l.mfspr r4,r0,0x20
     914:	00 00 05 c8 	l.j 2034 <default_exception_handler>
     918:	15 00 00 00 	l.nop 0x0
	...
     a00:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     a04:	d4 01 18 04 	l.sw 0x4(r1),r3
     a08:	d4 01 20 08 	l.sw 0x8(r1),r4
     a0c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     a10:	b4 80 00 20 	l.mfspr r4,r0,0x20
     a14:	00 00 05 88 	l.j 2034 <default_exception_handler>
     a18:	15 00 00 00 	l.nop 0x0
	...
     b00:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     b04:	d4 01 18 04 	l.sw 0x4(r1),r3
     b08:	d4 01 20 08 	l.sw 0x8(r1),r4
     b0c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     b10:	b4 80 00 20 	l.mfspr r4,r0,0x20
     b14:	00 00 05 48 	l.j 2034 <default_exception_handler>
     b18:	15 00 00 00 	l.nop 0x0
	...
     c00:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     c04:	d4 01 18 04 	l.sw 0x4(r1),r3
     c08:	d4 01 20 08 	l.sw 0x8(r1),r4
     c0c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     c10:	b4 80 00 20 	l.mfspr r4,r0,0x20
     c14:	00 00 05 08 	l.j 2034 <default_exception_handler>
     c18:	15 00 00 00 	l.nop 0x0
	...
     d00:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     d04:	d4 01 18 04 	l.sw 0x4(r1),r3
     d08:	d4 01 20 08 	l.sw 0x8(r1),r4
     d0c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     d10:	b4 80 00 20 	l.mfspr r4,r0,0x20
     d14:	00 00 04 c8 	l.j 2034 <default_exception_handler>
     d18:	15 00 00 00 	l.nop 0x0
	...
     e00:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     e04:	d4 01 18 04 	l.sw 0x4(r1),r3
     e08:	d4 01 20 08 	l.sw 0x8(r1),r4
     e0c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     e10:	b4 80 00 20 	l.mfspr r4,r0,0x20
     e14:	00 00 04 88 	l.j 2034 <default_exception_handler>
     e18:	15 00 00 00 	l.nop 0x0
	...
     f00:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
     f04:	d4 01 18 04 	l.sw 0x4(r1),r3
     f08:	d4 01 20 08 	l.sw 0x8(r1),r4
     f0c:	b4 60 00 10 	l.mfspr r3,r0,0x10
     f10:	b4 80 00 20 	l.mfspr r4,r0,0x20
     f14:	00 00 04 48 	l.j 2034 <default_exception_handler>
     f18:	15 00 00 00 	l.nop 0x0
	...
    1000:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1004:	d4 01 18 04 	l.sw 0x4(r1),r3
    1008:	d4 01 20 08 	l.sw 0x8(r1),r4
    100c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1010:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1014:	00 00 04 08 	l.j 2034 <default_exception_handler>
    1018:	15 00 00 00 	l.nop 0x0
	...
    1100:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1104:	d4 01 18 04 	l.sw 0x4(r1),r3
    1108:	d4 01 20 08 	l.sw 0x8(r1),r4
    110c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1110:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1114:	00 00 03 c8 	l.j 2034 <default_exception_handler>
    1118:	15 00 00 00 	l.nop 0x0
	...
    1200:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1204:	d4 01 18 04 	l.sw 0x4(r1),r3
    1208:	d4 01 20 08 	l.sw 0x8(r1),r4
    120c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1210:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1214:	00 00 03 88 	l.j 2034 <default_exception_handler>
    1218:	15 00 00 00 	l.nop 0x0
	...
    1300:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1304:	d4 01 18 04 	l.sw 0x4(r1),r3
    1308:	d4 01 20 08 	l.sw 0x8(r1),r4
    130c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1310:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1314:	00 00 03 48 	l.j 2034 <default_exception_handler>
    1318:	15 00 00 00 	l.nop 0x0
	...
    1400:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1404:	d4 01 18 04 	l.sw 0x4(r1),r3
    1408:	d4 01 20 08 	l.sw 0x8(r1),r4
    140c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1410:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1414:	00 00 03 08 	l.j 2034 <default_exception_handler>
    1418:	15 00 00 00 	l.nop 0x0
	...
    1500:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1504:	d4 01 18 04 	l.sw 0x4(r1),r3
    1508:	d4 01 20 08 	l.sw 0x8(r1),r4
    150c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1510:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1514:	00 00 02 c8 	l.j 2034 <default_exception_handler>
    1518:	15 00 00 00 	l.nop 0x0
	...
    1600:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1604:	d4 01 18 04 	l.sw 0x4(r1),r3
    1608:	d4 01 20 08 	l.sw 0x8(r1),r4
    160c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1610:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1614:	00 00 02 88 	l.j 2034 <default_exception_handler>
    1618:	15 00 00 00 	l.nop 0x0
	...
    1700:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1704:	d4 01 18 04 	l.sw 0x4(r1),r3
    1708:	d4 01 20 08 	l.sw 0x8(r1),r4
    170c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1710:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1714:	00 00 02 48 	l.j 2034 <default_exception_handler>
    1718:	15 00 00 00 	l.nop 0x0
	...
    1800:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1804:	d4 01 18 04 	l.sw 0x4(r1),r3
    1808:	d4 01 20 08 	l.sw 0x8(r1),r4
    180c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1810:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1814:	00 00 02 08 	l.j 2034 <default_exception_handler>
    1818:	15 00 00 00 	l.nop 0x0
	...
    1900:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1904:	d4 01 18 04 	l.sw 0x4(r1),r3
    1908:	d4 01 20 08 	l.sw 0x8(r1),r4
    190c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1910:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1914:	00 00 01 c8 	l.j 2034 <default_exception_handler>
    1918:	15 00 00 00 	l.nop 0x0
	...
    1a00:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1a04:	d4 01 18 04 	l.sw 0x4(r1),r3
    1a08:	d4 01 20 08 	l.sw 0x8(r1),r4
    1a0c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1a10:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1a14:	00 00 01 88 	l.j 2034 <default_exception_handler>
    1a18:	15 00 00 00 	l.nop 0x0
	...
    1b00:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1b04:	d4 01 18 04 	l.sw 0x4(r1),r3
    1b08:	d4 01 20 08 	l.sw 0x8(r1),r4
    1b0c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1b10:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1b14:	00 00 01 48 	l.j 2034 <default_exception_handler>
    1b18:	15 00 00 00 	l.nop 0x0
	...
    1c00:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1c04:	d4 01 18 04 	l.sw 0x4(r1),r3
    1c08:	d4 01 20 08 	l.sw 0x8(r1),r4
    1c0c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1c10:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1c14:	00 00 01 08 	l.j 2034 <default_exception_handler>
    1c18:	15 00 00 00 	l.nop 0x0
	...
    1d00:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1d04:	d4 01 18 04 	l.sw 0x4(r1),r3
    1d08:	d4 01 20 08 	l.sw 0x8(r1),r4
    1d0c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1d10:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1d14:	00 00 00 c8 	l.j 2034 <default_exception_handler>
    1d18:	15 00 00 00 	l.nop 0x0
	...
    1e00:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1e04:	d4 01 18 04 	l.sw 0x4(r1),r3
    1e08:	d4 01 20 08 	l.sw 0x8(r1),r4
    1e0c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1e10:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1e14:	00 00 00 88 	l.j 2034 <default_exception_handler>
    1e18:	15 00 00 00 	l.nop 0x0
	...
    1f00:	9c 21 ff 80 	l.addi r1,r1,0xffffff80
    1f04:	d4 01 18 04 	l.sw 0x4(r1),r3
    1f08:	d4 01 20 08 	l.sw 0x8(r1),r4
    1f0c:	b4 60 00 10 	l.mfspr r3,r0,0x10
    1f10:	b4 80 00 20 	l.mfspr r4,r0,0x20
    1f14:	00 00 00 48 	l.j 2034 <default_exception_handler>
    1f18:	15 00 00 00 	l.nop 0x0
	...

00002000 <_start>:
    2000:	18 20 51 ff 	l.movhi r1,0x51ff
    2004:	a8 21 ff fc 	l.ori r1,r1,0xfffc
    2008:	9c 40 ff fd 	l.addi r2,r0,0xfffffffd
    200c:	04 00 00 4b 	l.jal 2138 <_get_cpu_id>
    2010:	e0 21 10 03 	l.and r1,r1,r2
    2014:	18 80 00 50 	l.movhi r4,0x50
    2018:	a8 84 00 00 	l.ori r4,r4,0x0
    201c:	e0 8b 23 06 	l.mul r4,r11,r4
    2020:	e0 21 20 02 	l.sub r1,r1,r4
    2024:	e0 41 00 04 	l.or r2,r1,r0
    2028:	e0 60 00 03 	l.and r3,r0,r0
    202c:	04 00 00 51 	l.jal 2170 <_main>
    2030:	e0 80 00 03 	l.and r4,r0,r0

00002034 <default_exception_handler>:
    2034:	d4 01 10 00 	l.sw 0x0(r1),r2
    2038:	d4 01 28 0c 	l.sw 0xc(r1),r5
    203c:	d4 01 30 10 	l.sw 0x10(r1),r6
    2040:	d4 01 38 14 	l.sw 0x14(r1),r7
    2044:	d4 01 40 18 	l.sw 0x18(r1),r8
    2048:	d4 01 48 1c 	l.sw 0x1c(r1),r9
    204c:	d4 01 50 20 	l.sw 0x20(r1),r10
    2050:	d4 01 58 24 	l.sw 0x24(r1),r11
    2054:	d4 01 60 28 	l.sw 0x28(r1),r12
    2058:	d4 01 68 2c 	l.sw 0x2c(r1),r13
    205c:	d4 01 70 30 	l.sw 0x30(r1),r14
    2060:	d4 01 78 34 	l.sw 0x34(r1),r15
    2064:	d4 01 80 38 	l.sw 0x38(r1),r16
    2068:	d4 01 88 3c 	l.sw 0x3c(r1),r17
    206c:	d4 01 90 40 	l.sw 0x40(r1),r18
    2070:	d4 01 98 44 	l.sw 0x44(r1),r19
    2074:	d4 01 a0 48 	l.sw 0x48(r1),r20
    2078:	d4 01 a8 4c 	l.sw 0x4c(r1),r21
    207c:	d4 01 b0 50 	l.sw 0x50(r1),r22
    2080:	d4 01 b8 54 	l.sw 0x54(r1),r23
    2084:	d4 01 c0 58 	l.sw 0x58(r1),r24
    2088:	d4 01 c8 5c 	l.sw 0x5c(r1),r25
    208c:	d4 01 d0 60 	l.sw 0x60(r1),r26
    2090:	d4 01 d8 64 	l.sw 0x64(r1),r27
    2094:	d4 01 e0 68 	l.sw 0x68(r1),r28
    2098:	d4 01 e8 6c 	l.sw 0x6c(r1),r29
    209c:	d4 01 f0 70 	l.sw 0x70(r1),r30
    20a0:	d4 01 f8 74 	l.sw 0x74(r1),r31
    20a4:	d4 01 00 78 	l.sw 0x78(r1),r0
    20a8:	07 ff f7 d6 	l.jal 0 <_exception_reset-0x100>
    20ac:	15 00 00 00 	l.nop 0x0
    20b0:	84 41 00 00 	l.lwz r2,0x0(r1)
    20b4:	84 61 00 04 	l.lwz r3,0x4(r1)
    20b8:	84 81 00 08 	l.lwz r4,0x8(r1)
    20bc:	84 a1 00 0c 	l.lwz r5,0xc(r1)
    20c0:	84 c1 00 10 	l.lwz r6,0x10(r1)
    20c4:	84 e1 00 14 	l.lwz r7,0x14(r1)
    20c8:	85 01 00 18 	l.lwz r8,0x18(r1)
    20cc:	85 21 00 1c 	l.lwz r9,0x1c(r1)
    20d0:	85 41 00 20 	l.lwz r10,0x20(r1)
    20d4:	85 61 00 24 	l.lwz r11,0x24(r1)
    20d8:	85 81 00 28 	l.lwz r12,0x28(r1)
    20dc:	85 a1 00 2c 	l.lwz r13,0x2c(r1)
    20e0:	85 c1 00 30 	l.lwz r14,0x30(r1)
    20e4:	85 e1 00 34 	l.lwz r15,0x34(r1)
    20e8:	86 01 00 38 	l.lwz r16,0x38(r1)
    20ec:	86 21 00 3c 	l.lwz r17,0x3c(r1)
    20f0:	86 41 00 40 	l.lwz r18,0x40(r1)
    20f4:	86 61 00 44 	l.lwz r19,0x44(r1)
    20f8:	86 81 00 48 	l.lwz r20,0x48(r1)
    20fc:	86 a1 00 4c 	l.lwz r21,0x4c(r1)
    2100:	86 c1 00 50 	l.lwz r22,0x50(r1)
    2104:	86 e1 00 54 	l.lwz r23,0x54(r1)
    2108:	87 01 00 58 	l.lwz r24,0x58(r1)
    210c:	87 21 00 5c 	l.lwz r25,0x5c(r1)
    2110:	87 41 00 60 	l.lwz r26,0x60(r1)
    2114:	87 61 00 64 	l.lwz r27,0x64(r1)
    2118:	87 81 00 68 	l.lwz r28,0x68(r1)
    211c:	87 a1 00 6c 	l.lwz r29,0x6c(r1)
    2120:	87 c1 00 70 	l.lwz r30,0x70(r1)
    2124:	87 e1 00 74 	l.lwz r31,0x74(r1)
    2128:	84 01 00 78 	l.lwz r0,0x78(r1)
    212c:	9c 21 00 80 	l.addi r1,r1,0x80
    2130:	24 00 00 00 	l.rfe 
    2134:	15 00 00 00 	l.nop 0x0

00002138 <_get_cpu_id>:
    2138:	44 00 48 00 	l.jr r9
    213c:	b5 60 f8 00 	l.mfspr r11,r0,0xf800

00002140 <_set_cpu_id>:
    2140:	44 00 48 00 	l.jr r9
    2144:	c3 e0 18 00 	l.mtspr r0,r3,0xf800

00002148 <_find_first_one>:
    2148:	44 00 48 00 	l.jr r9
    214c:	e1 63 00 0f 	l.ff1 r11,r3

00002150 <_get_thread_id>:
    2150:	44 00 48 00 	l.jr r9
    2154:	b5 60 f8 01 	l.mfspr r11,r0,0xf801

00002158 <_set_thread_id>:
    2158:	44 00 48 00 	l.jr r9
    215c:	c3 e0 18 01 	l.mtspr r0,r3,0xf801

00002160 <_get_thread_priority>:
    2160:	44 00 48 00 	l.jr r9
    2164:	b5 60 f8 02 	l.mfspr r11,r0,0xf802

00002168 <_set_thread_priority>:
    2168:	44 00 48 00 	l.jr r9
    216c:	c3 e0 18 02 	l.mtspr r0,r3,0xf802

00002170 <_main>:
    2170:	00 00 00 00 	l.j 2170 <_main>
    2174:	15 00 00 00 	l.nop 0x0
    2178:	44 00 48 00 	l.jr r9
    217c:	15 00 00 00 	l.nop 0x0
