<?xml version="1.0" encoding="ISO-8859-1" ?>

<cpu name="my_name" >

  <!-- **************************** -->
  <!-- * Définition du processeur * -->
  <!-- **************************** -->

  <type>
    <definition id="0">
      <allow id="0" />
    </definition>

    <definition id="1">
      <allow id="0" />
      <allow id="2" />
    </definition>

    <affectation name="INST_L_ADD"                   />
    <affectation name="INST_L_SUB" type="0"          />
    <affectation type="1"          name="INST_L_AND" />
  </type>

  <!-- defaut : delay = 1 et latence = 1 -->
  <latence id="0">

  </latence>

  <latence id="1">
    <operation name="inst1"                           />
    <operation name="inst2" delay="8"                 />
    <operation name="inst3" delay="1"    latence="2"  />
    <operation name="inst4" latence="1"  delay="2"    />
    <operation name="inst5"              latence="2"  />
    <operation latence="1"  name="inst6" delay="2"    />
    <operation latence="1"  delay="2"    name="inst7" />
  </latence>

  <internal>

    <global>
      <size_data     value="32"     />
      <scheme_bypass algo ="complet"/>
      <isa> 
        <ORFPX  type="1"      value="1" />
        <ORBIS  value="true"            />
        <ORVDX  value="false" type="2"  />
      </isa>
    </global>

    <cache>
      <icache id="0">
        <arbiter                              algo ="roundrobin" />
        <nb_port                              value="2"     />
      </icache>
      <icache id="1">
        <nb_port                              value="2"     />
        <arbiter                              algo ="roundrobin" />
      </icache>
      <icache id="2">
        <nb_port                              value="2"     />
      </icache>
      <icache id="3">
        <arbiter                              algo ="roundrobin" />
      </icache>
      <icache id="4">
      </icache>

      <dcache id="0">
         <arbiter                              algo ="roundrobin" />
         <nb_port                              value="2"     />
      </dcache>
    </cache>

    <!-- Etage 1 : Ifetch -->
    <ifetch id="0">
         <link_icache                            id="0"        />
         <link_predictor                         id="0"        />
         <link_decod                             id="0"        />
    </ifetch>			                 	           

    <ifetch id="1">
         <nb_inst_fetch                          value="4"     />
         <size_fetch_queue                       value="3"     />

         <link_icache                            id="0"        />
         <link_decod                             id="0"        />
         <link_predictor                         id="0"        />
    </ifetch>			                 	           

    <ifetch id="2">

         <link_decod                             id="0"        />
         <link_icache                            id="0"        />

         <size_fetch_queue                       value="3"     />

         <link_predictor                         id="0"        />
    </ifetch>			                 	           

    <ifetch id="3">
         <nb_inst_fetch                          value="4"     />

         <link_decod                             id="0"        />
         <link_predictor                         id="0"        />
         <link_icache                            id="0"        />
    </ifetch>			                 	           


    <!-- Predicteur de branchement -->				                 	       
    <prediction id="0">		                 	       

      <arbiter                                algo ="roundrobin" />
      <scheme_predictor                       algo ="all"   />
      <size_return_address_stack              value="8"     />
      <size_update_prediction                 value="4"     />

      <branch_target_buffer>
        <size_branch_target_buffer            value="32"    />
        <associativity_branch_target_buffer   value="4"     />
      </branch_target_buffer>

      <meta_predictor>						       
        <size_prediction                      value="32"    />
        <nb_bit_counter                       value="2"     />
      </meta_predictor>		

      <global_predictor>				       
        <size_prediction_history_table        value="4"     />
        <size_prediction                      value="16"    />
        <nb_bit_counter                       value="2"     />
      </global_predictor>
      
      <local_predictor>
        <size_prediction_history_table        value="4"     />
        <size_prediction_l1                   value="8"     />
        <size_prediction_l2                   value="16"    />
        <nb_bit_counter                       value="2"     />
        <xor                                  value="false" />
      </local_predictor>

    </prediction>					       





    <branch_queue id="0">
<!--
      <arbiter                                algo ="roundrobin" />
      <nb_branch_speculated                   value="4"     />
      <nb_branch_complete                     value="1"     />
-->
    </branch_queue>




	
    <!-- Etage 2 : Décodage -->				     	       
    <decod id="0">
<!--
         <arbiter                                algo ="roundrobin" />
         <link_rename                            id="0"        />
         <link_branch_queue                      id="0"        />
         <nb_inst_decod                          value="3"     />
         <nb_inst_rename                         value="3"     />
         <size_decod_queue                       value="4"     />
-->
    </decod>			                 	       



				                 	       
    <!-- Etage 3 : Renommage -->
    <rename id="0">
<!--
         <arbiter                                algo ="roundrobin" />

         <slot>
           <route                                id="0"        />
         </slot>

         <link_commit                            id="0"        />
         <link_load_store_queue                  id="0"        />
         <link_special_register_file             id="0"        />

         <nb_inst_rename                         value="5"     />
         <nb_inst_select_windows                 value="9"     />
         <size_rename_queue                      value="15"    />
         <nb_gpr_phy                             value="128"   />
         <nb_gpr_free                            value="4"     />
         <nb_spr_phy                             value="32"    />
         <nb_spr_free                            value="2"     />
-->
    </rename>





    <!-- Etage 4   Selection/Issue -->
    <select_issue>
      <!-- lien entre un slot est un cluster -->
      <slot id="0">
        <!-- lien entre un cluster et une waitunit -->
        <cluster id="0">
          <route                                 id="0"        />
        </cluster>
      </slot>
    </select_issue>





    <!-- Etage 5 : Execution -->
    <execute>

      <!-- Clusterisation des unités d'éxecution -->
      <cluster id="0">
         <!-- bypass intra cluster -->
         <bypass_register                        value="false" />
         <bypass_status                          value="false" />
         
         <!-- Wait Unit (Selection queue - Reservation Station) -->
         <waitunit id="0">
              <size_select_queue                 value="4"     />
              <size_reservation_station          value="4"     />
              <dispatch>
                <route                           id="0"        />
              </dispatch>
         </waitunit>

         <!-- Executive Unit (Ue (type des opérations accepté et latence des opérations) - Execute queue) -->
         <executiveunit id="0">
              <arbiter                           algo ="roundrobin" />
              <size_execute_queue                value="4"     />
              <nb_inst_execute                   value="2"     />
              <type                              value="0"     />
              <latence                           value="0"     />
         </executiveunit>

      </cluster>
    </execute>




    <!-- Etage 5bis : Memory -->
    <memory id="0">		                 	       
         <arbiter                                algo ="roundrobin" />
         <link_dcache                            id="0"        />
         <link_commit                            id="0"        />
         <nb_inst_commit                         value="4"     />
         <nb_memory_complete                     value="5"     />
         <size_load_store_queue                  value="32"    />
         <bypass_memory_in                       value="false" />
         <bypass_memory_out                      value="false" />
         <bypass_memory_internal                 value="false" />
    </memory>




    <!-- Banc de registres 
         (Autant de RegFile que d'étage 3) -->
    <general_registerfile id="0">		                 	       
         <arbiter                                algo ="roundrobin" />
         <nb_gpr_reader                          value="5"     />
         <nb_gpr_writer                          value="5"     />
         <nb_spr_reader                          value="5"     />
         <nb_spr_writer                          value="5"     />
    </general_registerfile>





    <!-- Etage 6 : Commit -->
    <commit id="0">		                 	       
         <arbiter                                algo ="roundrobin" />
         <nb_inst_commit                         value="4"     />
         <nb_inst_update                         value="5"     />
         <nb_inst_update_windows                 value="9"     />
         <size_re_order_buffer                   value="32"    />
         <commit_out_of_order_thread             value="false" />
    </commit>


  </internal>

</cpu>
