<?xml version="1.0" encoding="ISO-8859-1"?>

<cpu name="my_cpu">
  
  <!-- **************************** -->
  <!-- * Définition du processeur * -->
  <!-- **************************** -->

  <definition>
    <!-- Définition global s'applique à tous le proc -->
    <global>
      <size_data                                 value="32"     />        <!-- Balise Optionnel (defaut : 32 )     -->
      <scheme_bypass                             algo ="complet"/>        <!-- Balise Optionnel (defaut : complet) -->
      <isa> 
        <ORBIS                                   value="true" type="2" /> <!-- Balise Obligatoire, attribut "type" optionniel (default : 1) -->
        <ORFPX                                   value="false"  />        <!-- Balise Obligatoire, attribut "type" optionniel (default : 1) -->
        <ORVDX                                   value="false"  />        <!-- Balise Obligatoire, attribut "type" optionniel (default : 1) -->
      </isa>
    </global>

    <cache>
      <icache id="0">
         <arbiter                              algo ="roundrobin" />
         <nb_icache_port                       value="2"     />
      </icache>
      <dcache id="0">
           <arbiter                              algo ="roundrobin" />
           <nb_dcache_port                       value="2"     />
      </dcache>
    </cache>

    <!-- Etage 1 : Ifetch -->
    <ifetch id="0">
         <nb_inst_fetch                          value="4"     />
         <size_fetch_queue                       value="3"     />

         <link_icache                            id="0"        />
         <link_decod                             id="0"        />
         <link_predictor                         id="0"        />
    </ifetch>			                 	           

    <!-- Predicteur de branchement -->				                 	       
    <prediction>		                 	       
      <instance id="0">		                 	       
         <arbiter                                algo ="roundrobin" />

         <scheme_predictor                       algo ="all"   />
         <size_branch_target_buffer              value="32"    />
         <associativity_branch_target_buffer     value="4"     />

	 <meta_predictor>						       
           <size_prediction                      value="32"    />
           <nb_bit_counter                       value="2"     />
	 </meta_predictor>		

         <global_predictor>				       
           <size_prediction_history_table        value="4"     />
           <size_prediction                      value="16"    />
           <nb_bit_counter                       value="2"     />
	 </global_predictor>
	
         <local_predictor>
           <size_prediction_history_table        value="4"     />
           <size_prediction_l1                   value="8"     />
           <size_prediction_l2                   value="16"    />
           <nb_bit_counter                       value="2"     />
           <xor                                  value="false" />
         </local_predictor>

         <size_return_address_stack              value="8"     />
         <size_update_prediction                 value="4"     />

      </instance>					       
    </prediction>					       

    <branch_queue>
      <instance id="0">
         <arbiter                                algo ="roundrobin" />
         <nb_branch_speculated                   value="4"     />
         <nb_branch_complete                     value="1"     />
      </instance>
    </branch_queue>
	
    <!-- Etage 2 : Décodage -->				         	       
    <decod>				         	       
      <instance id="0">			         	       
         <arbiter                                algo ="roundrobin" />
         <link_rename                            id="0"        />
         <link_branch_queue                      id="0"        />
         <nb_inst_decod                          value="3"     />
         <nb_inst_rename                         value="3"     />
         <size_decod_queue                       value="4"     />
      </instance>		                 	           
    </decod>			                 	       
				                 	       
    <!-- Etage 3 : Renommage -->
    <rename>			                 	       
      <instance id="0">		                 	       
         <arbiter                                algo ="roundrobin" />

         <slot>
           <route                                id="0"        />
         </slot>

         <link_commit                            id="0"        />
         <link_load_store_queue                  id="0"        />
         <link_special_register_file             id="0"        />
         <nb_inst_rename                         value="5"     />
         <nb_inst_select_windows                 value="9"     />
         <size_rename_queue                      value="15"    />
         <nb_gpr_phy                             value="128"   />
         <nb_gpr_free                            value="4"     />
         <nb_spr_phy                             value="32"    />
         <nb_spr_free                            value="2"     />
      </instance>		                 	       
    </rename>

    <!-- Etage 4   Selection/Issue -->
    <select_issue>
      <!-- lien entre un slot est un cluster -->
      <slot id="0">
        <!-- lien entre un cluster et une waitunit -->
        <cluster id="0">
          <route                                 id="0"        />
        </cluster>
      </slot>
    </select_issue>

    <!-- Etage 5 : Execution -->
    <execute>

      <!-- Clusterisation des unités d'éxecution -->
      <cluster id="0">
         <!-- bypass intra cluster -->
         <bypass_register                        value="false" />
         <bypass_status                          value="false" />
         
         <!-- Wait Unit (Selection queue - Reservation Station) -->
         <waitunit>
           <instance id="0">
              <size_select_queue                 value="4"     />
              <size_reservation_station          value="4"     />
              <dispatch>
                <route                           id="0"        />
              </dispatch>
           </instance>
         </waitunit>

         <!-- Executive Unit (Ue (type des opérations accepté et latence des opérations) - Execute queue) -->
         <executiveunit>
           <instance id="0">
              <arbiter                           algo ="roundrobin" />
              <size_execute_queue                value="4"     />
              <nb_inst_execute                   value="2"     />
              <type                              value="0"     />
              <latence                           value="0"     />
           </instance>
         </executiveunit>

      </cluster>
    </execute>

    <!-- Etage 5bis : Memory -->
    <memory>
      <instance id="0">		                 	       
         <arbiter                                algo ="roundrobin" />
         <link_dcache                            id="0"        />
         <link_commit                            id="0"        />
         <nb_inst_commit                         value="4"     />
         <nb_memory_complete                     value="5"     />
         <size_load_store_queue                  value="32"    />
         <bypass_memory_in                       value="false" />
         <bypass_memory_out                      value="false" />
         <bypass_memory_internal                 value="false" />
      </instance>
    </memory>

    <!-- Banc de registres 
         (Autant de RegFile que d'étage 3) -->
    <general_registerfile>
      <instance id="0">		                 	       
         <arbiter                                algo ="roundrobin" />
         <nb_gpr_reader                          value="5"     />
         <nb_gpr_writer                          value="5"     />
         <nb_spr_reader                          value="5"     />
         <nb_spr_writer                          value="5"     />
      </instance>
    </general_registerfile>

    <!-- Etage 6 : Commit -->
    <commit>
      <instance id="0">		                 	       
         <arbiter                                algo ="roundrobin" />
         <nb_inst_commit                         value="4"     />
         <nb_inst_update                         value="5"     />
         <nb_inst_update_windows                 value="9"     />
         <size_re_order_buffer                   value="32"    />
         <commit_out_of_order_thread             value="false" />
      </instance>
    </commit>
  </definition>

  <!-- ******** -->
  <!-- * Type * -->
  <!-- ******** -->

  <type>
    <!-- definition : pour chaque instance, definit les types autorisé -->
    <enumerate>
      <instance id="0">
        <allow id="0" />
        <allow id="2" />
      </instance>
    </enumerate>

    <!-- pour chaque operation, définit le type d'appartenance.
         default : 0 -->
    <affectation>
        <operation name="INST_L_ADD" type="0"/>
        <operation name="INST_L_SUB" type="0"/>
        <operation name="INST_L_AND" type="1"/>
        <operation name="INST_L_XOR" type="1"/>
        <operation name="INST_L_MUL" type="2"/>
        <operation name="INST_L_DIV" type="2"/>
    </affectation>
  </type>

  <!-- *********** -->
  <!-- * Latence * -->
  <!-- *********** -->

  <!-- liste pour chaque opération leur delay et latence, 
       default : latence = 1, delay = 1 -->
  <latence>
    <instance id="0">
      <operation name="INST_L_ADD" delay="1" latence="2" />
      <operation name="INST_L_MUL" delay="8" latence="4" />
    </instance>
  </latence>

</cpu>
