#ifdef VHDL_TESTBENCH
/*
 * $Id$
 *
 * [ Description ]
 * 
 */

#include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h"

namespace morpheo                    {
namespace behavioural {
namespace generic {
namespace registerfile{
namespace registerfile_multi_banked {


  void RegisterFile_Multi_Banked::vhdl_testbench_transition ()
  {
    log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_testbench_transition","Begin");

    // Evaluation before read the ouput signal
//     sc_start(0);

    // In order with file RegisterFile_Multi_Banked_vhdl_testbench_port.cpp
    // Warning : if a output depend of a subcomponent, take directly the port of subcomponent
    // (because we have no control on the ordonnancer's policy)

    _vhdl_testbench->add_input (PORT_READ( in_NRESET));

    // ----- Interface Read
    for (uint32_t i=0; i<_param._nb_port_read; i++)
      {
	_vhdl_testbench->add_input (PORT_READ(  in_READ_VAL     [i]));
	_vhdl_testbench->add_output(PORT_READ( out_READ_ACK     [i]));
	_vhdl_testbench->add_input (PORT_READ(  in_READ_ADDRESS [i]));
	_vhdl_testbench->add_output(PORT_READ( out_READ_DATA    [i]));
      }

    // ----- Interface Write
    for (uint32_t i=0; i<_param._nb_port_write; i++)
      {
	_vhdl_testbench->add_input (PORT_READ(  in_WRITE_VAL     [i]));
	_vhdl_testbench->add_output(PORT_READ( out_WRITE_ACK     [i]));
	_vhdl_testbench->add_input (PORT_READ(  in_WRITE_ADDRESS [i]));
	_vhdl_testbench->add_input (PORT_READ(  in_WRITE_DATA    [i]));
      }

    
    // add_test :
    //  - True  : the cycle must be compare with the output of systemC
    //  - False : no test
    _vhdl_testbench->add_test(true);

    _vhdl_testbench->new_cycle (); // always at the end

    log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_testbench_transition","End");
  };

}; // end namespace registerfile_multi_banked
}; // end namespace registerfile
}; // end namespace generic

}; // end namespace behavioural
}; // end namespace morpheo              
#endif
