Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 100)
@@ -220,4 +220,6 @@
   private   : Tcounter_t                   ** reg_NB_INST_COMMIT_ALL               ;//[nb_front_end][nb_context]
   private   : Tcounter_t                   ** reg_NB_INST_COMMIT_MEM               ;//[nb_front_end][nb_context]
+
+  private   : Tevent_state_t               ** reg_EVENT_STATE                      ;//[nb_front_end][nb_context]
 										   
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 100)
@@ -27,19 +27,21 @@
   typedef enum
     {
-      ROB_EMPTY                     , // 
-      ROB_BRANCH_WAIT_END           , // 
-      ROB_BRANCH_COMPLETE           , // 
-      ROB_STORE_WAIT_HEAD_OK        , // 
-//    ROB_STORE_WAIT_HEAD_KO        , // 
-      ROB_STORE_HEAD_OK             , // 
-      ROB_STORE_HEAD_KO             , // 
-      ROB_OTHER_WAIT_END            , // 
-      ROB_MISS_WAIT_END             , // 
-      ROB_END_OK_SPECULATIVE        , // 
-      ROB_END_OK                    , // 
-      ROB_END_KO_SPECULATIVE        , // 
-      ROB_END_KO                    , // 
-      ROB_END_MISS                  , // 
-      ROB_END_EXCEPTION_WAIT_HEAD   , // 
+      ROB_EMPTY                      , // 
+      ROB_BRANCH_WAIT_END            , // 
+      ROB_BRANCH_COMPLETE            , // 
+      ROB_STORE_WAIT_HEAD_OK         , // 
+//    ROB_STORE_WAIT_HEAD_KO         , // 
+      ROB_STORE_HEAD_OK              , // 
+      ROB_STORE_HEAD_KO              , // 
+      ROB_OTHER_WAIT_END             , // 
+      ROB_MISS_WAIT_END              , // 
+      ROB_END_OK_SPECULATIVE         , // 
+      ROB_END_OK                     , // 
+      ROB_END_KO_SPECULATIVE         , // 
+      ROB_END_KO                     , // 
+      ROB_END_BRANCH_MISS_SPECULATIVE, // 
+      ROB_END_BRANCH_MISS            , // 
+      ROB_END_MISS                   , // 
+      ROB_END_EXCEPTION_WAIT_HEAD    , // 
       ROB_END_EXCEPTION               // 
     } rob_state_t;
@@ -79,5 +81,4 @@
   public  : Tspecial_address_t num_reg_re_phy_new      ;
 
-  public  : Tevent_state_t     event_state             ;
   public  : Texception_t       exception               ;
   public  : Texception_t       exception_use           ;
@@ -161,19 +162,23 @@
     switch (x)
       {
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EMPTY                     : return "empty"                     ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_WAIT_END           : return "branch_wait_end"           ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_COMPLETE           : return "branch_complete"           ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_OK        : return "store_wait_head_ok"        ; break;
-//    case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_KO        : return "store_wait_head_ko"        ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_OK             : return "store_head_ok"             ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO             : return "store_head_ko"             ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END            : return "other_wait_end"            ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_MISS_WAIT_END             : return "miss_wait_end"             ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK_SPECULATIVE        : return "end_ok_speculative"        ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK                    : return "end_ok"                    ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO_SPECULATIVE        : return "end_ko_speculative"        ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO                    : return "end_ko"                    ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_WAIT_HEAD   : return "end_exception_wait_head"   ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION             : return "end_exception"             ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EMPTY                      : return "ROB_EMPTY"                       ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_WAIT_END            : return "ROB_BRANCH_WAIT_END"             ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_COMPLETE            : return "ROB_BRANCH_COMPLETE"             ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_OK         : return "ROB_STORE_WAIT_HEAD_OK"          ; break;
+//    case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_KO         : return "ROB_STORE_WAIT_HEAD_KO"          ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_OK              : return "ROB_STORE_HEAD_OK"               ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO              : return "ROB_STORE_HEAD_KO"               ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END             : return "ROB_OTHER_WAIT_END"              ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_MISS_WAIT_END              : return "ROB_MISS_WAIT_END"               ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK_SPECULATIVE         : return "ROB_END_OK_SPECULATIVE"          ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK                     : return "ROB_END_OK"                      ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO_SPECULATIVE         : return "ROB_END_KO_SPECULATIVE"          ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO                     : return "ROB_END_KO"                      ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_BRANCH_MISS_SPECULATIVE: return "ROB_END_BRANCH_MISS_SPECULATIVE" ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_BRANCH_MISS            : return "ROB_END_BRANCH_MISS"             ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_MISS                   : return "ROB_END_MISS"                    ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_WAIT_HEAD    : return "ROB_END_EXCEPTION_WAIT_HEAD"     ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION              : return "ROB_END_EXCEPTION"               ; break;
+
       default    : return ""      ; break;
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 100)
@@ -272,16 +272,12 @@
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-    _rob = new std::list<entry_t*> [_param->_nb_bank];
+    ALLOC1(_rob                   ,std::list<entry_t*>,_param->_nb_bank);
     
-    reg_BANK_PTR           = new uint32_t     [_param->_nb_bank];
-
-    reg_NB_INST_COMMIT_ALL = new Tcounter_t * [_param->_nb_front_end];
-    reg_NB_INST_COMMIT_MEM = new Tcounter_t * [_param->_nb_front_end];
+    ALLOC1(reg_BANK_PTR           ,uint32_t      ,_param->_nb_bank);
+
+    ALLOC2(reg_NB_INST_COMMIT_ALL ,Tcounter_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_NB_INST_COMMIT_MEM ,Tcounter_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
     
-    for (uint32_t i=0; i<_param->_nb_front_end; i++)
-      {
-	reg_NB_INST_COMMIT_ALL [i] = new Tcounter_t [_param->_nb_context [i]];
-	reg_NB_INST_COMMIT_MEM [i] = new Tcounter_t [_param->_nb_context [i]];
-      }
+    ALLOC2(reg_EVENT_STATE        ,Tevent_state_t,_param->_nb_front_end,_param->_nb_context [it1]);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 100)
@@ -178,15 +178,9 @@
         
         // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-        for (uint32_t i=0; i<_param->_nb_front_end; i++)
-          {
-            delete [] reg_NB_INST_COMMIT_ALL [i];
-            delete [] reg_NB_INST_COMMIT_MEM [i];
-          }
-        delete [] reg_NB_INST_COMMIT_ALL;
-        delete [] reg_NB_INST_COMMIT_MEM;
-        
-        delete [] reg_BANK_PTR;
-        
-        delete [] _rob;
+        DELETE1(_rob                   ,_param->_nb_bank);
+        DELETE1(reg_BANK_PTR           ,_param->_nb_bank);
+        DELETE2(reg_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_STATE        ,_param->_nb_front_end,_param->_nb_context [it1]);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp	(revision 100)
@@ -30,4 +30,5 @@
     uint32_t           bank_nb_access    [_param->_nb_bank];
     Tcontrol_t         commit_ack        [_param->_nb_inst_commit];
+
     // Initialisation
     for (uint32_t i=0; i<_param->_nb_bank; i++)
@@ -38,14 +39,15 @@
       }
 
-    // commit interface
+    // commit interface -> scan all entry (Out of Order)
     for (uint32_t i=0; i<_param->_nb_inst_commit; i++)
       {
         commit_ack        [i] = false;
 
-	// Test if have instruction
+	// Test if have valid instruction
 	if (PORT_READ(in_COMMIT_VAL [i]))
 	  {
-	    Tpacket_t packet          = (_param->_have_port_rob_ptr  )?PORT_READ(in_COMMIT_PACKET_ID [i]):0;
-	    uint32_t  num_bank        = packet >> _param->_shift_num_bank;
+            // packet_id number can 
+	    Tpacket_t packet_id       = (_param->_have_port_rob_ptr  )?PORT_READ(in_COMMIT_PACKET_ID [i]):0;
+	    uint32_t  num_bank        = packet_id >> _param->_shift_num_bank;
 	    uint32_t  num_bank_access = bank_nb_access [num_bank];
             
@@ -60,5 +62,5 @@
 		internal_BANK_COMMIT_NUM_INST [num_bank][num_bank_access] = i;
                 
-                Tpacket_t packet_id = packet & _param->_mask_size_bank;
+                Tpacket_t num_packet = packet_id & _param->_mask_size_bank;
                 
                 // find the good entry !!!
@@ -67,5 +69,5 @@
                      it!=_rob[num_bank].end();
                      it++)
-                  if ((*it)->ptr == packet_id)
+                  if ((*it)->ptr == num_packet)
                     {
                       entry = (*it);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 100)
@@ -54,5 +54,6 @@
     std::list<generic::priority::select_t> * select_insert = _priority_insert ->select(); // same select for all insert
     std::list<generic::priority::select_t>::iterator it=select_insert ->begin();
- 
+
+    // Scan all bank ...
     for (uint32_t i=0; i<_param->_nb_bank; i++)
       {
@@ -64,4 +65,5 @@
 // 	log_printf(TRACE,Commit_unit,FUNCTION,"    * full : %d", bank_full [num_bank]);
 
+        // Scan all insert interface to find a valid transaction
 	while (it!=select_insert ->end())
 	  {
@@ -87,5 +89,5 @@
 		if (not bank_full [num_bank])
 		  {
-		    // find
+		    // find !!!
 		    insert_ack       [num_rename_unit][num_inst_insert] = true;
 
@@ -112,4 +114,5 @@
       }
     
+    // Write output
     for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
       for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 100)
@@ -48,9 +48,13 @@
 	  retire_val [i][j] = false;
       }
-
     for (uint32_t i=0; i<_param->_nb_front_end; ++i)
       for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
-	spr_write_val [i][j] = 0;
-
+        {
+          spr_write_val [i][j] = 0;
+          spr_write_sr_f_val  [i][j] = 0;
+          spr_write_sr_cy_val [i][j] = 0;
+          spr_write_sr_ov_val [i][j] = 0;
+
+        }
     // Scan Top of each bank
     for (uint32_t i=0; i<_param->_nb_bank; i++)
@@ -64,5 +68,8 @@
 	    uint32_t   x     = entry->rename_unit_id;
 	    uint32_t   y     = num_inst_retire [x];
-	    
+	
+            // test if :
+            //  * can retire (all previous instruction is retired)
+            //  * all structure is ok (not busy)
 	    if (can_retire [x] and // in-order
 		(y < _param->_nb_inst_retire [x]) and
@@ -71,7 +78,8 @@
 		rob_state_t state = entry->state;
 		
-		if ((state == ROB_END_OK  ) or 
-		    (state == ROB_END_KO  ) or 
-		    (state == ROB_END_MISS)//  or 
+		if ((state == ROB_END_OK         ) or 
+		    (state == ROB_END_KO         ) or 
+		    (state == ROB_END_BRANCH_MISS) or 
+		    (state == ROB_END_MISS       )//  or 
 // 		    (state == ROB_END_EXCEPTION)
 		    )
@@ -85,5 +93,7 @@
 		    bool spr_write_ack = true;
 
+                    // Write in SR the good flag
 		    if ((state == ROB_END_OK  ) and write_re)
+                      // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE
 		      {
 			spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]);
@@ -138,5 +148,5 @@
 		    PORT_WRITE(out_RETIRE_CONTEXT_ID            [x][y], context_id                  );
 // 		    PORT_WRITE(out_RETIRE_RENAME_UNIT_ID        [x][y], entry->rename_unit_id       );
-		    PORT_WRITE(out_RETIRE_EVENT_STATE           [x][y], entry->event_state          );
+		    PORT_WRITE(out_RETIRE_EVENT_STATE           [x][y], reg_EVENT_STATE[front_end_id][context_id]);
 		    PORT_WRITE(out_RETIRE_USE_STORE_QUEUE       [x][y], entry->use_store_queue      );
 		    PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE        [x][y], entry->use_load_queue       );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 100)
@@ -28,4 +28,7 @@
     // ===================================================================
     {
+      // Store instruction comming Out Of Order in Load Store Unit. 
+      // Must be executed in no speculative mode. Also, send a signal when an Store is in head of ROB
+
       Tcontrol_t val = false;
 
@@ -35,4 +38,5 @@
 	  rob_state_t  state = entry->state;
 
+          // Test state
 	  val   = ((state == ROB_STORE_HEAD_OK) or
 		   (state == ROB_STORE_HEAD_KO));
@@ -40,4 +44,5 @@
 	  if (val)
 	    {
+              // Reexecute store
 	      if (_param->_have_port_context_id)
   	      PORT_WRITE(out_REEXECUTE_CONTEXT_ID            [0], entry->context_id           );
@@ -62,6 +67,8 @@
     // ===================================================================
     {
+      // Branchement must be send at the prediction unit
       uint32_t nb_scan_bank = 0;
 
+      // for each port, find a valid branchement.
       for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
 	{
@@ -72,4 +79,5 @@
 	      nb_scan_bank ++;
 
+              // translate bank number
 	      uint32_t num_bank = (reg_NUM_BANK_HEAD+j)%_param->_nb_bank;
 	      
@@ -124,16 +132,4 @@
 	}
     }
-
-//   public    : SC_OUT(Tcontrol_t         )   * out_UPDATE_VAL                        ;
-//   public    : SC_IN (Tcontrol_t         )   *  in_UPDATE_ACK                        ;
-//   public    : SC_OUT(Tcontext_t         )   * out_UPDATE_CONTEXT_ID                 ;
-//   public    : SC_OUT(Tcontext_t         )   * out_UPDATE_FRONT_END_ID               ;
-//   public    : SC_OUT(Tdepth_t           )   * out_UPDATE_DEPTH                      ;
-//   public    : SC_OUT(Tevent_type_t      )   * out_UPDATE_TYPE                       ;
-//   public    : SC_OUT(Tcontrol_t         )   * out_UPDATE_IS_DELAY_SLOT              ;
-//   public    : SC_OUT(Taddress_t         )   * out_UPDATE_ADDRESS                    ;
-//   public    : SC_OUT(Taddress_t         )   * out_UPDATE_ADDRESS_EPCR               ;
-//   public    : SC_OUT(Tcontrol_t         )   * out_UPDATE_ADDRESS_EEAR_VAL           ;
-//   public    : SC_OUT(Taddress_t         )   * out_UPDATE_ADDRESS_EEAR               ;
  
     // ===================================================================
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp	(revision 100)
@@ -57,4 +57,7 @@
       _stat->create_expr_average_by_cycle("average_inst_retire_ko", sum_nb_inst_retire_ko, "", _("Average instruction retire ko (event, miss) by cycle"));
       _stat->create_expr_average_by_cycle("average_inst_retire"   , "+ "+sum_nb_inst_retire_ok+" "+sum_nb_inst_retire_ko, "", _("Average instruction retire by cycle"));
+
+      _stat->create_expr                 ("IPC", "average_inst_retire_ok", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle");
+      _stat->create_expr                 ("CPI", "/ 1 IPC"               , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction");
     }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 100)
@@ -26,4 +26,5 @@
     if (PORT_READ(in_NRESET) == 0)
       {
+        // Clear all bank 
         for (uint32_t i=0; i<_param->_nb_bank; i++)
 	  {
@@ -32,7 +33,9 @@
 	  }
 
+        // Reset pointer
 	reg_NUM_BANK_HEAD = 0;
 	reg_NUM_BANK_TAIL = 0;
 
+        // Reset counter
 	for (uint32_t i=0; i<_param->_nb_front_end; i++)
 	  for (uint32_t j=0; j<_param->_nb_context [i]; j++)
@@ -40,12 +43,29 @@
 	      reg_NB_INST_COMMIT_ALL [i][j] = 0;
 	      reg_NB_INST_COMMIT_MEM [i][j] = 0;
+
+              reg_EVENT_STATE        [i][j] = EVENT_STATE_NO_EVENT;
 	    }
 
+        // Reset priority algorithm
 	_priority_insert->reset();
       }
     else
       {
-	// next priority
+	// Compute next priority
 	_priority_insert->transition();
+
+	// ===================================================================
+	// =====[ GARBAGE COLLECTOR ]=========================================
+	// ===================================================================
+	for (uint32_t i=0; i<_param->_nb_front_end; i++)
+	  for (uint32_t j=0; j<_param->_nb_context [i]; j++)
+            switch (reg_EVENT_STATE [i][j])
+              {
+              case EVENT_STATE_EVENT    : reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; break;
+              case EVENT_STATE_END      : reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; break;
+//            case EVENT_STATE_NO_EVENT : 
+//            case EVENT_STATE_WAITEND  : 
+              default : break;
+              }
 
 	// ===================================================================
@@ -55,4 +75,5 @@
 	  if (internal_BANK_INSERT_VAL [i])
 	    {
+              // get rename unit source and instruction.
 	      uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i];
 	      uint32_t y = internal_BANK_INSERT_NUM_INST        [i];
@@ -67,8 +88,11 @@
 #endif
 
+                  // get information
 		  Tcontext_t   front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0;
 		  Tcontext_t   context_id   = (_param->_have_port_context_id  )?PORT_READ(in_INSERT_CONTEXT_ID   [x][y]):0;
 		  Ttype_t      type         = PORT_READ(in_INSERT_TYPE         [x][y]);
                   Toperation_t operation    = PORT_READ(in_INSERT_OPERATION    [x][y]);
+                  bool         is_store     = is_operation_memory_store(operation);
+
 		  Texception_t exception    = PORT_READ(in_INSERT_EXCEPTION    [x][y]);
 
@@ -78,5 +102,6 @@
 		  log_printf(TRACE,Commit_unit,FUNCTION,"    * operation      : %d",operation );
 		  log_printf(TRACE,Commit_unit,FUNCTION,"    * exception      : %d",exception );
-
+                  
+                  // Create new entry.
 		  entry_t * entry = new entry_t;
 
@@ -92,6 +117,6 @@
 		  entry->exception               = exception;
 		  entry->exception_use           = PORT_READ(in_INSERT_EXCEPTION_USE         [x][y]);
-		  entry->use_store_queue         = (type == TYPE_MEMORY) and (    is_operation_memory_store(operation));
-		  entry->use_load_queue          = (type == TYPE_MEMORY) and (not is_operation_memory_store(operation));
+		  entry->use_store_queue         = (type == TYPE_MEMORY) and (    is_store);
+		  entry->use_load_queue          = (type == TYPE_MEMORY) and (not is_store);
 		  entry->store_queue_ptr_write   = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]);
 		  entry->load_queue_ptr_write    = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0;
@@ -114,4 +139,12 @@
 		  entry->num_reg_re_phy_new      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW    [x][y]);
 
+                  // Test if exception :
+                  //  * yes : no execute instruction, wait ROB Head
+                  //  * no  : test type
+                  //            * BRANCH : l.j   -> branch is ended
+                  //                       other -> wait the execution end of branchment
+                  //            * MEMORY : store -> wait store is at head of ROB
+                  //                       other -> wait end of instruction
+                  //            * OTHER
 		  if (exception == EXCEPTION_NONE)
 		    {
@@ -124,5 +157,5 @@
 			{
 			case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;}
-			case TYPE_MEMORY : {entry->state=ROB_STORE_WAIT_HEAD_OK; break;}
+			case TYPE_MEMORY : {entry->state=(is_store  ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;}
 			default          : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
 			}
@@ -130,4 +163,6 @@
 		  else
 		    {
+                      // Have an exception : wait head of ROB
+
                       // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
 
@@ -135,7 +170,8 @@
 		    }
 
+                  // Push in rob
 		  _rob[i].push_back(entry);
 
-		  // Update nb_inst
+		  // Update counter and pointer
 		  reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++;
 		  if (type == TYPE_MEMORY)
@@ -160,4 +196,6 @@
 	    if (internal_BANK_COMMIT_VAL [i][j])
 	      {
+                // An instruction is executed. Change state of this instruction
+
 		uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j];
 
@@ -171,93 +209,73 @@
 #endif
 
-// 		    Tpacket_t packet_id = (_param->_have_port_rob_ptr  )?(PORT_READ(in_COMMIT_PACKET_ID [x])&_param->_mask_size_bank):0;
-		    
 		    log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank   : %d",i);
-// 		    log_printf(TRACE,Commit_unit,FUNCTION,"    * packet_id  : %d",(_param->_have_port_rob_ptr  )?(PORT_READ(in_COMMIT_PACKET_ID [x])):0);
-// 		    log_printf(TRACE,Commit_unit,FUNCTION,"    * num_entry  : %d",packet_id);
-		    
-		    // test pandex with ptr_write.
-// 		    Tpacket_t index     = (packet_id<reg_BANK_PTR [i])?(reg_BANK_PTR [i]-packet_id):(_param->_size_bank+reg_BANK_PTR [i]-packet_id);
 
 		    // find the good entry !!!
-		    entry_t *       entry       = internal_BANK_COMMIT_ENTRY [i][j];
-
-		  //Toperation_t    operation   = PORT_READ(in_COMMIT_OPERATION   [x]);
-		  //Ttype_t         type        = PORT_READ(in_COMMIT_TYPE        [x]);
-		    Texception_t    exception   = PORT_READ(in_COMMIT_EXCEPTION   [x]);
-
-		    rob_state_t state        = entry->state;
-		    Tcontext_t  front_end_id = entry->front_end_id;
-		    Tcontext_t  context_id   = entry->context_id;
-
-		    // change state
+		    entry_t *       entry        = internal_BANK_COMMIT_ENTRY [i][j];
+                                                 
+		  //Toperation_t    operation    = PORT_READ(in_COMMIT_OPERATION   [x]);
+		  //Ttype_t         type         = PORT_READ(in_COMMIT_TYPE        [x]);
+		    Texception_t    exception    = PORT_READ(in_COMMIT_EXCEPTION   [x]);
+
+		    rob_state_t     state        = entry->state;
+		    Tcontext_t      front_end_id = entry->front_end_id;
+		    Tcontext_t      context_id   = entry->context_id;
+
+		    // change state : test exception_use
 		    //  * test if exception : exception and mask
 		    
-		    bool have_exception = false;
-		    
+		    bool have_exception        = false;
+                    bool have_miss_speculation = false;
+
 		    if (exception != EXCEPTION_NONE)
-		      switch (entry->exception_use)
-			{
-			case  EXCEPTION_USE_RANGE                    : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;}
-			case  EXCEPTION_USE_MEMORY_WITH_ALIGNMENT    : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
-											  (exception == EXCEPTION_DATA_TLB ) or
-											  (exception == EXCEPTION_DATA_PAGE) or
-											  (exception == EXCEPTION_ALIGNMENT)); break;};
-			case  EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
-											  (exception == EXCEPTION_DATA_TLB ) or
-											  (exception == EXCEPTION_DATA_PAGE)); break;};
-			case  EXCEPTION_USE_CUSTOM_0                 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; 
-			case  EXCEPTION_USE_CUSTOM_1                 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; 
-			case  EXCEPTION_USE_CUSTOM_2                 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; 
-			case  EXCEPTION_USE_CUSTOM_3                 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; 
-			case  EXCEPTION_USE_CUSTOM_4                 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; 
-			case  EXCEPTION_USE_CUSTOM_5                 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; 
-			case  EXCEPTION_USE_CUSTOM_6                 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; 
-			case  EXCEPTION_USE_TRAP                     : {have_exception = false; break;};
-			case  EXCEPTION_USE_NONE                     : {have_exception = false; break;}; 
-			case  EXCEPTION_USE_ILLEGAL_INSTRUCTION      : {have_exception = false; break;};
-			case  EXCEPTION_USE_SYSCALL                  : {have_exception = false; break;};
-			default :
-			  {
-			    throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n"));
-			    break;
-			  }
-			}
-
-		    if (not have_exception)
-		      {
-			switch (state)
-			  {
-			  case ROB_OTHER_WAIT_END  : {state = ROB_END_OK_SPECULATIVE; break;}
-			  case ROB_BRANCH_WAIT_END : {state = ROB_BRANCH_COMPLETE   ; break;}
-			  case ROB_MISS_WAIT_END   : {state = ROB_END_KO_SPECULATIVE; break;}
-			  default :
-			    {
-			      throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str()));
-			      break;
-			    }
-			  }
-			// can have an exception, but this instruction is not sensible a this exception
-			exception = EXCEPTION_NONE; 
-		      }
-		    else
-		      {
-#ifdef DEBUG_TEST
-			if ((entry->type == TYPE_MEMORY) and (exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
-			  throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception.\n"));
-#endif 
-
-			switch (state)
-			  {
-			  case ROB_OTHER_WAIT_END  : 
-			  case ROB_BRANCH_WAIT_END : {state = ROB_END_EXCEPTION_WAIT_HEAD; break;}
-			  case ROB_MISS_WAIT_END   : {state = ROB_END_KO_SPECULATIVE     ; break;}
-			  default :
-			    {
-			      throw ERRORMORPHEO(FUNCTION,_("Commit : invalid state value.\n"));
-			      break;
-			    }
-			  }
-		      }
+                      {
+                        // Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store)
+                        have_miss_speculation  = (exception == EXCEPTION_MEMORY_MISS_SPECULATION);
+
+                        switch (entry->exception_use)
+                          {
+                            // Have overflow exception if bit overflow enable is set.
+                          case  EXCEPTION_USE_RANGE                    : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;}
+                          case  EXCEPTION_USE_MEMORY_WITH_ALIGNMENT    : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
+                                                                                            (exception == EXCEPTION_DATA_TLB ) or
+                                                                                            (exception == EXCEPTION_DATA_PAGE) or
+                                                                                            (exception == EXCEPTION_ALIGNMENT)); break;};
+                          case  EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
+                                                                                            (exception == EXCEPTION_DATA_TLB ) or
+                                                                                            (exception == EXCEPTION_DATA_PAGE)); break;};
+                          case  EXCEPTION_USE_CUSTOM_0                 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; 
+                          case  EXCEPTION_USE_CUSTOM_1                 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; 
+                          case  EXCEPTION_USE_CUSTOM_2                 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; 
+                          case  EXCEPTION_USE_CUSTOM_3                 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; 
+                          case  EXCEPTION_USE_CUSTOM_4                 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; 
+                          case  EXCEPTION_USE_CUSTOM_5                 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; 
+                          case  EXCEPTION_USE_CUSTOM_6                 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; 
+                            // Case already manage (decod stage -> in insert in ROB)
+                          case  EXCEPTION_USE_TRAP                     : {have_exception = false; exception = EXCEPTION_NONE; break;};
+                          case  EXCEPTION_USE_NONE                     : {have_exception = false; exception = EXCEPTION_NONE; break;}; 
+                          case  EXCEPTION_USE_ILLEGAL_INSTRUCTION      : {have_exception = false; exception = EXCEPTION_NONE; break;};
+                          case  EXCEPTION_USE_SYSCALL                  : {have_exception = false; exception = EXCEPTION_NONE; break;};
+                          default :
+                            {
+                              throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n"));
+                              break;
+                            }
+                          }
+                      }
+                   
+                    switch (state)
+                      {
+                        // Branch ...
+                      case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;}
+                        // Store KO
+                      case ROB_MISS_WAIT_END   : {state = ROB_END_KO_SPECULATIVE; break;}
+                        // Store OK, Load and other instruction
+                      case ROB_OTHER_WAIT_END  : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_MISS:ROB_END_OK_SPECULATIVE); break;}
+                      default :
+                        {
+                          throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str()));
+                          break;
+                        }
+                      }
 
 		    // update Re Order Buffer
@@ -287,9 +305,9 @@
 
 	      entry_t *  entry        =  _rob [i].front();
+              rob_state_t state = entry->state;
+              
 #ifdef STATISTICS
               if (usage_is_set(_usage,USE_STATISTICS))
                 {
-                  rob_state_t state = entry->state;
-                  
                   if (state == ROB_END_OK)
                     (*_stat_nb_inst_retire_ok [x]) ++;
@@ -302,4 +320,11 @@
 	      Tcontext_t context_id   = entry->context_id  ;
 	      Ttype_t    type         = entry->type        ;
+
+              if (state == ROB_END_BRANCH_MISS)
+                {
+                  reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT;
+
+                  // !!!!!!!!!!! Compute address
+                }
 	      
 	      // Update nb_inst
@@ -307,5 +332,8 @@
 	      if (type == TYPE_MEMORY)
 		reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
-	      
+
+              if (reg_NB_INST_COMMIT_ALL [front_end_id][context_id] == 0)
+                reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_END;
+
 	      reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank;
 	      
@@ -350,10 +378,21 @@
 #endif
 
-	      entry->state = ROB_END_OK_SPECULATIVE;
+              entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_OK_SPECULATIVE:ROB_END_BRANCH_MISS_SPECULATIVE;
+//               entry->state = ROB_END_OK_SPECULATIVE;
 	    }
 
 	// ===================================================================
+	// =====[ UPDATE ]====================================================
+	// ===================================================================
+        {
+          // Not yet implemented
+        }
+
+	// ===================================================================
 	// =====[ EVENT ]=====================================================
 	// ===================================================================
+        {
+          // Not yet implemented
+        }
 
 	// ===================================================================
@@ -400,24 +439,26 @@
 		  switch (state)
 		    {
-		    case ROB_BRANCH_WAIT_END           : {state = ROB_MISS_WAIT_END; break;}
-		    case ROB_BRANCH_COMPLETE           : {state = ROB_END_MISS     ; break;}
-		    case ROB_STORE_WAIT_HEAD_OK        : {state = ROB_STORE_HEAD_KO; break;}
-		  //case ROB_STORE_WAIT_HEAD_KO        : {state = ; break;}
-		    case ROB_OTHER_WAIT_END            : {state = ROB_MISS_WAIT_END; break;}
-		    case ROB_END_OK_SPECULATIVE        : {state = ROB_END_MISS     ; break;}
-		    case ROB_END_KO_SPECULATIVE        : {state = ROB_END_MISS     ; break;}
-		    case ROB_END_EXCEPTION_WAIT_HEAD   : {state = ROB_END_MISS     ; break;}
-		      
-		      // don't change
-		    case ROB_STORE_HEAD_KO             : {break;}
-		    case ROB_MISS_WAIT_END             : {break;}
-		    case ROB_END_MISS                  : {break;}
-		      
-		      // can't have miss speculation
-		    case ROB_STORE_HEAD_OK             :
-		    case ROB_END_OK                    :
-		    case ROB_END_KO                    :
-		    case ROB_END_EXCEPTION             :
-		    default                            : 
+		    case ROB_BRANCH_WAIT_END             : {state = ROB_MISS_WAIT_END; break;}
+		    case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS     ; break;}
+                    case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS     ; break;}
+		    case ROB_STORE_WAIT_HEAD_OK          : {state = ROB_STORE_HEAD_KO; break;}
+		  //case ROB_STORE_WAIT_HEAD_KO          : {state = ; break;}
+		    case ROB_OTHER_WAIT_END              : {state = ROB_MISS_WAIT_END; break;}
+		    case ROB_END_OK_SPECULATIVE          : {state = ROB_END_MISS     ; break;}
+		    case ROB_END_KO_SPECULATIVE          : {state = ROB_END_MISS     ; break;}
+		    case ROB_END_EXCEPTION_WAIT_HEAD     : {state = ROB_END_MISS     ; break;}
+		                                         
+		      // don't change                    
+		    case ROB_STORE_HEAD_KO               : {break;}
+		    case ROB_MISS_WAIT_END               : {break;}
+		    case ROB_END_MISS                    : {break;}
+		                                         
+		      // can't have miss speculation     
+		    case ROB_STORE_HEAD_OK               :
+		    case ROB_END_OK                      :
+		    case ROB_END_KO                      :
+                    case ROB_END_BRANCH_MISS             :
+		    case ROB_END_EXCEPTION               :
+		    default                              : 
 		      {
 			throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n"));
@@ -434,6 +475,7 @@
 		  switch (state)
 		    {
-		    case ROB_END_OK_SPECULATIVE        : {state = ROB_END_OK                 ; break;}
-		    case ROB_END_KO_SPECULATIVE        : {state = ROB_END_KO                 ; break;}
+		    case ROB_END_OK_SPECULATIVE          : {state = ROB_END_OK                 ; break;}
+		    case ROB_END_KO_SPECULATIVE          : {state = ROB_END_KO                 ; break;}
+		    case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS        ; break;}
 		    default : {break;}
 		  }
@@ -519,11 +561,10 @@
                        (*it)->num_reg_re_phy_new      );
             
-            log_printf(TRACE,Commit_unit,FUNCTION,"             %.2d %.2d %.1d %.1d %.8x %s",
+            log_printf(TRACE,Commit_unit,FUNCTION,"             %.2d %.2d %.1d %.1d %.8x",
                        (*it)->exception     ,
                        (*it)->exception_use ,
                        (*it)->flags         ,
                        (*it)->no_sequence   ,
-                       (*it)->data_commit   ,
-                       toString((*it)->event_state).c_str()
+                       (*it)->data_commit   
                        );
 
