Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp	(revision 100)
@@ -255,9 +255,9 @@
     // Result
     op->_timing       = param->_timing[op->_type][op->_operation];
-    op->_data_rd      = imm;
+    op->_data_rd      = imm<<2; // add "00"
   //op->_data_re      = 0;
     op->_exception    = EXCEPTION_ALU_NONE;
     op->_no_sequence  = 1;
-    op->_address      = gpr;
+    op->_address      = gpr>>2; // del "00"
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp	(revision 100)
@@ -279,7 +279,7 @@
 							     			       
   							     			       
-  transaction_in.push_back(execute_transaction(_param,0,0,0, 31,OPERATION_BRANCH_L_JALR    ,TYPE_BRANCH,0,0xdeadbeef,0x0       ,0x12345678,0              ,0,63,0xdeadbeef,0,15,FLAG_CY        ,EXCEPTION_NONE     ,1,0x12345678)); // jr
-  transaction_in.push_back(execute_transaction(_param,0,0,0, 32,OPERATION_BRANCH_L_JALR    ,TYPE_BRANCH,1,0xdeadbeef,0x0       ,0x12345678,0              ,1,63,0xdeadbeef,0,15,FLAG_CY        ,EXCEPTION_NONE     ,1,0x12345678)); // jal
-  transaction_in.push_back(execute_transaction(_param,0,0,0, 33,OPERATION_BRANCH_L_JALR    ,TYPE_BRANCH,1,0xdeadbeef,0x0       ,0x12345678,0              ,1,63,0xdeadbeef,0,15,FLAG_CY        ,EXCEPTION_NONE     ,1,0x12345678)); // jalr
+  transaction_in.push_back(execute_transaction(_param,0,0,0, 31,OPERATION_BRANCH_L_JALR    ,TYPE_BRANCH,0,0xdeadbeef,0x0       ,0x12345678,0              ,0,63,0xdeadbeef,0,15,FLAG_CY        ,EXCEPTION_NONE     ,1,0x12345678>>2)); // jr
+  transaction_in.push_back(execute_transaction(_param,0,0,0, 32,OPERATION_BRANCH_L_JALR    ,TYPE_BRANCH,1,0xdeadbeef,0x0       ,0x12345678,0              ,1,63,0xdeadbeef<<2,0,15,FLAG_CY        ,EXCEPTION_NONE     ,1,0x12345678>>2)); // jal
+  transaction_in.push_back(execute_transaction(_param,0,0,0, 33,OPERATION_BRANCH_L_JALR    ,TYPE_BRANCH,1,0xdeadbeef,0x0       ,0x12345678,0              ,1,63,0xdeadbeef<<2,0,15,FLAG_CY        ,EXCEPTION_NONE     ,1,0x12345678>>2)); // jalr
 							     
   transaction_in.push_back(execute_transaction(_param,0,0,0, 34,OPERATION_EXTEND_L_EXTEND_S,TYPE_EXTEND,1,8         ,0x12345678,0x0       ,0              ,1,63,0x00000078,0,15,FLAG_CY        ,EXCEPTION_NONE     ,0));
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp	(revision 100)
@@ -138,5 +138,5 @@
             log_printf(TRACE,Functionnal_unit,FUNCTION,"    * exception     : %d"  ,_execute_operation_in->_exception  );
             log_printf(TRACE,Functionnal_unit,FUNCTION,"    * no_sequence   : %d"  ,_execute_operation_in->_no_sequence);
-            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * address       : %.8x",_execute_operation_in->_address    );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * address       : %.8x (%.8x)",_execute_operation_in->_address,_execute_operation_in->_address<<2);
 
 #ifdef STATISTICS
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl.cpp	(revision 100)
@@ -32,5 +32,6 @@
     param_queue = new morpheo::behavioural::generic::queue::Parameters
       (_param->_size_queue,
-       _param->_size_internal_queue
+       _param->_size_internal_queue,
+       0
        );
     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl.cpp	(revision 100)
@@ -34,5 +34,6 @@
     param_queue = new morpheo::behavioural::generic::queue::Parameters
       (_param->_size_queue,
-       _param->_size_internal_queue
+       _param->_size_internal_queue,
+       0
        );
     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp	(revision 100)
@@ -903,6 +903,6 @@
     inst->_type               = instruction_information(INSTRUCTION_L_JALR)._type     ; //TYPE_BRANCH;
     inst->_operation          = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR;
-    inst->_has_immediat       = 0;
-    inst->_immediat           = 0; // unnecessary
+    inst->_has_immediat       = 1;
+    inst->_immediat           = inst->_address_next+1;
     inst->_read_ra            = 0;
     inst->_num_reg_ra         = 0; //unnecessary
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/config_mono_context.cfg	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/config_mono_context.cfg	(revision 100)
@@ -3,5 +3,5 @@
 1	1	*4	# nb_decod_unit      
 30	30	+32	# size_address       
-1	1	*4	# nb_instruction  [0] [nb_context]
+1	4	*2	# nb_instruction  [0] [nb_context]
 1	1	*4	# size_depth      [0] [nb_context]
 4	4	*4	# nb_inst_decod   [0] [nb_decod_unit]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp	(revision 100)
@@ -362,4 +362,8 @@
 
   // Initialisation
+  const bool test1 = false;
+  const bool test2 = true ;
+  const bool test3 = false;
+  const bool test4 = false;
 
   const uint32_t seed = 0;
@@ -402,4 +406,5 @@
       LABEL("Iteration %d",iteration);
 
+      if (test1)
       {
 	LABEL("Test sequential");
@@ -481,4 +486,5 @@
       }
 
+      if (test2)
       {
       	LABEL("Test no sequential - L.J");
@@ -489,11 +495,13 @@
 	for (uint32_t i=0; i<_param->_nb_instruction [context]; i++)
 	  {
-	    Taddress_t addr      = (1<<(_param->_nb_instruction[context]+4));
-	    Taddress_t addr_src  = addr+i;
+	    Taddress_t pc_current  = (1<<(_param->_nb_instruction[context]+3));
+            Taddress_t pc_previous = pc_current-1;
+	    Taddress_t addr_src  = pc_current+i;
 	    Taddress_t addr_dest = 0xdeadbeef;
-	    
-	    in_PREDICT_PC_PREVIOUS           [context]->write(0);
-	    in_PREDICT_PC_CURRENT            [context]->write(addr);
-	    in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]->write(0);
+	    Tcontrol_t is_ds_take= rand()%2;
+
+	    in_PREDICT_PC_PREVIOUS           [context]->write(pc_previous);
+	    in_PREDICT_PC_CURRENT            [context]->write(pc_current);
+	    in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]->write(is_ds_take);
 
 	    bool find = false;
@@ -515,5 +523,5 @@
 		    LABEL(" * BTB address : 0x%x",out_PREDICT_BTB_ADDRESS    [port]->read());
 		    if ((out_PREDICT_BTB_CONTEXT_ID [port]->read() == context) and
-			(out_PREDICT_BTB_ADDRESS    [port]->read() == addr   ))
+			(out_PREDICT_BTB_ADDRESS    [port]->read() == (is_ds_take)?pc_previous:pc_current   ))
 		      {
 			in_PREDICT_BTB_ACK          [port]->write((rand()%100)<percent_transaction_predict);
@@ -531,27 +539,42 @@
 		SC_START(0);
 
+                LABEL ("PREDICT_VAL : %d", in_PREDICT_VAL[context]->read());
+                LABEL ("PREDICT_ACK : %d",out_PREDICT_ACK[context]->read());
+                
 		if (in_PREDICT_VAL[context]->read() and out_PREDICT_ACK[context]->read())
 		  {
 		    LABEL ("PREDICT         [%d] - Transaction accepted",context);
+		    LABEL ("  * pc_previous: 0x%x",pc_previous );
+		    LABEL ("  * pc_current : 0x%x",pc_current      );
+		    LABEL ("  * addr_src   : 0x%x",addr_src  );
+		    LABEL ("  * addr_dest  : 0x%x",addr_dest );
+		    LABEL ("  * is_ds_take : %d"  ,is_ds_take);
+
 		    find = true;
-
-		    TEST(Taddress_t        ,out_PREDICT_PC_NEXT                     [context]->read(),addr_dest);
-		    TEST(Tcontrol_t        ,out_PREDICT_PC_NEXT_IS_DS_TAKE          [context]->read(),i==(_param->_nb_instruction [context]-1));
+                    
+                    Tcontrol_t next_is_ds_take = (not is_ds_take and (i==(_param->_nb_instruction [context]-1)));
+
+                    TEST(Tcontrol_t        ,out_PREDICT_PC_NEXT_IS_DS_TAKE          [context]->read(), next_is_ds_take);
+		    TEST(Taddress_t        ,out_PREDICT_PC_NEXT                     [context]->read(),(next_is_ds_take)?(addr_src+1):addr_dest);
 		    TEST(Tinst_ifetch_ptr_t,out_PREDICT_INST_IFETCH_PTR             [context]->read(),i);
-		    TEST(Tbranch_state_t   ,out_PREDICT_BRANCH_STATE                [context]->read(),BRANCH_STATE_NSPEC_TAKE);
+                    TEST(Tbranch_state_t   ,out_PREDICT_BRANCH_STATE                [context]->read(),(next_is_ds_take)?BRANCH_STATE_NONE:BRANCH_STATE_NSPEC_TAKE);
 // 		    TEST(Tprediction_ptr_t ,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context]->read(),0);
 
-		    uint32_t k=((addr_src%_param->_nb_instruction[context])==_param->_nb_instruction[context]-1)?_param->_nb_instruction[context]:((addr_src%_param->_nb_instruction[context])+2);
+		    uint32_t k=((is_ds_take)?1:((next_is_ds_take)?_param->_nb_instruction[context]:((addr_src%_param->_nb_instruction [context])+2)));
+
+
+// ((addr_src%_param->_nb_instruction[context])==_param->_nb_instruction[context]-1)?_param->_nb_instruction[context]:((addr_src%_param->_nb_instruction[context])+2);
+
 		    LABEL("instruction enable : ");
 		    LABEL("  [0:%d[ = 1",k);
-		    LABEL("  [%d:%d[ = 1",k,_param->_nb_instruction[context]);
+		    LABEL("  [%d:%d[ = 0",k,_param->_nb_instruction[context]);
 		    for (uint32_t j=0; j<k; j++)
-		      TEST(Tcontrol_t        ,out_PREDICT_INSTRUCTION_ENABLE [context][j]->read(),1);
+		    TEST(Tcontrol_t        ,out_PREDICT_INSTRUCTION_ENABLE [context][j]->read(),1);
 		    for (uint32_t j=k; j<_param->_nb_instruction[context]; j++)
-		      TEST(Tcontrol_t        ,out_PREDICT_INSTRUCTION_ENABLE [context][j]->read(),0);
+		    TEST(Tcontrol_t        ,out_PREDICT_INSTRUCTION_ENABLE [context][j]->read(),0);
 
 		    TEST(Tcontrol_t        ,out_PREDICT_BTB_VAL        [port]->read(),1); 
 		    TEST(Tcontext_t        ,out_PREDICT_BTB_CONTEXT_ID [port]->read(),context);
-		    TEST(Taddress_t        ,out_PREDICT_BTB_ADDRESS    [port]->read(),addr);
+		    TEST(Taddress_t        ,out_PREDICT_BTB_ADDRESS    [port]->read(),(is_ds_take)?pc_previous:pc_current);
 		  }
 		
@@ -571,5 +594,6 @@
 	  }
       }
-
+      
+      if (test3)
       {
 	LABEL("Decod - Ok");
@@ -618,4 +642,5 @@
       }
 
+      if (test4)
       {
 	LABEL("Decod - Ko");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp	(revision 100)
@@ -27,5 +27,4 @@
     if (PORT_READ(in_NRESET))
       {
-  
     // Init
     Tcontrol_t ack [_param->_nb_context];
@@ -36,5 +35,6 @@
       {
         log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"  * PREDICT [%d]",i);
-
+        
+        // No access
         Tcontrol_t btb_val = false;
         Tcontrol_t dir_val = false;
@@ -42,4 +42,5 @@
         Tcontrol_t upt_val = false;
 
+        // Get ack
         Tcontrol_t btb_ack = PORT_READ(in_PREDICT_BTB_ACK [i]);
         Tcontrol_t dir_ack = PORT_READ(in_PREDICT_DIR_ACK [i]);
@@ -47,11 +48,14 @@
         Tcontrol_t upt_ack = PORT_READ(in_PREDICT_UPT_ACK [i]);
 
+        // Read context_id
         Tcontext_t context = (reg_PREDICT_PRIORITY+i)%_param->_nb_context; // priority
         log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * context    : %d",context);
 
+        // Now : ack transaction
         ack [context] = 1;
 
         if (PORT_READ(in_PREDICT_VAL[context]) == 0)
           {
+            // Nothing
             log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * not valid ...");
 
@@ -63,12 +67,14 @@
         else
           {
+            // Have transaction
             log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * valid ...");
 
+            // Read information (PC)
             Taddress_t          pc_previous           = PORT_READ(in_PREDICT_PC_PREVIOUS           [context]);
             Taddress_t          pc_current            = PORT_READ(in_PREDICT_PC_CURRENT            [context]);
             Tcontrol_t          pc_current_is_ds_take = PORT_READ(in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]);
 
-            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * pc_previous           : 0x%.8x",pc_previous          );
-            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * pc_current            : 0x%.8x",pc_current           );
+            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * pc_previous           : 0x%.8x (0x%.8x)",pc_previous,pc_previous<<2);
+            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * pc_current            : 0x%.8x (0x%.8x)",pc_current ,pc_current <<2);
             log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * pc_current_is_ds_take : %d"    ,pc_current_is_ds_take);
 
@@ -80,30 +86,35 @@
             
             // STEP (1) - Compute the address source
-            // if pc_current is a ds take, then pc_previous is a branchement
+            //   -> if pc_current is a ds take, then pc_previous is a branchement
+            //      get branchement address to send at the BTB
             Taddress_t          address     = (pc_current_is_ds_take)?pc_previous:pc_current;
+            // Address_lsb = position in fetch packet
             Taddress_t          address_lsb = pc_current%_param->_nb_instruction [context]; //if pc_current_is_ds_take, then pc_current%_param->_nb_instruction [context] == 0
             Taddress_t          address_msb;
 
-            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * address               : 0x%.8x",address);
+            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * address               : 0x%.8x (0x%.8x)",address,address<<2);
             log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * address_lsb           : %d"    ,address_lsb);
 
             // STEP (2) - Test if branch (access at branch_target_buffer)
+            // Access at the btb
             btb_val = true;
 
+            // Create the request
             if (_param->_have_port_context_id)
             PORT_WRITE(out_PREDICT_BTB_CONTEXT_ID [i],context);
             PORT_WRITE(out_PREDICT_BTB_ADDRESS    [i],address);
 
+            // Transaction can be ack if btb is not busy
             ack [context] &= btb_ack;
 
             log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * btb_ack               : %d"    ,btb_ack);
 
-            // BTB_ack = 0 ?
+            // BTB_ack = 0 ? else can continue
             if (not btb_ack)
               continue;
 
-            // special case :
-            //  if pc_current_is_ds, then pc_previous have branch, also hit must be set.
-            //  else : a another branch have eject this branch : can't accurate
+            // Test a special case :
+            //  if pc_current is a delay slot, then pc_previous is a branchement instruction, also hit must be set.
+            //  else : an another branch instruction have eject this branch : can't accurate
             Tcontrol_t          hit         = PORT_READ(in_PREDICT_BTB_HIT[i]);
             Tcontrol_t          is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE  [i]) and not (pc_current_is_ds_take and not hit);
@@ -112,193 +123,214 @@
             log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * is_accurate           : %d"    ,is_accurate);
 
-            // STEP (3) : Test if have branch in the packet
+            // STEP (3) : Test if BTB find a branch instruction in the packet
             if (hit == 1)
               {
+                log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * BTB hit : no sequential order");
+
                 // STEP (3a) : branch - test condition
                 bool                use_dir      = false;
                 bool                use_ras      = false;
                 bool                use_upt      = false;
-                
-                Tbranch_condition_t condition    = PORT_READ(in_PREDICT_BTB_CONDITION    [i]);
-                Taddress_t          address_src  = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC  [i]);
-                Taddress_t          address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]);
-                Tcontrol_t          push     ;
-                Tcontrol_t          direction;
-
-                log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * condition             : %s"    ,toString(condition).c_str());
-                log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * address_src           : 0x%.8x",address_src);
-                log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * address_dest          : 0x%.8x",address_dest);
-
-                switch (condition)
-                  {
-                  case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK          : // l.j
-                    {
-                      // use none unit (dir, upt and ras)
-                      direction    = true;
-                      pc_next      = address_dest;
-                      branch_state = BRANCH_STATE_NSPEC_TAKE;
-                      break;
-                    }
-                  case BRANCH_CONDITION_NONE_WITH_WRITE_STACK             : // l.jal
-                    {
-                      use_upt      = true;
-                      use_ras      = true;
-                      push         = true;
-                      direction    = true;
-                      pc_next      = address_dest;
-                      branch_state = BRANCH_STATE_NSPEC_TAKE;
-                      break;
-                    }
-                  case BRANCH_CONDITION_FLAG_UNSET                        : // l.bnf
-                  case BRANCH_CONDITION_FLAG_SET                          : // l.bf
-                    {
-                      use_upt      = true;
-                      use_dir      = true;
-                      // Test direction
-                      direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same
-                      if (direction = 1)
-                        {
-                          branch_state = BRANCH_STATE_SPEC_TAKE;
-                          pc_next      = address_dest;
-                        }
-                      else
-                        {
-                          branch_state = BRANCH_STATE_SPEC_NTAKE;
-                          pc_next      = address_src+2; // +1 = delay slot
-                        }
-                      break;
-                    }
-                  case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : // l.jr (rb!=9)
-                    {
-                      use_upt      = true;
-                      use_ras      = true;
-                      push         = true;
-                      direction    = true;
-                      pc_next      = address_dest;
-                      branch_state = BRANCH_STATE_SPEC_TAKE;
-                      break;
-                    }
-                  case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK    : // l.jalr
-                    {
-                      use_upt      = true;
-                      use_ras      = true;
-                      push         = true;
-                      direction    = true;
-                      pc_next      = address_dest;
-                      branch_state = BRANCH_STATE_NSPEC_TAKE;
-                      break;
-                    }
-                  case BRANCH_CONDITION_READ_STACK                        : // l.jr (rb==9)
-                    {
-                      use_upt      = true;
-                      use_ras      = true;
-                      push         = false;
-                      direction    = true;
-                      pc_next      = PORT_READ(in_PREDICT_RAS_ADDRESS_POP  [i]);
-                      branch_state = BRANCH_STATE_SPEC_TAKE;
-                      break;
-                    }
-                  default :
-                    {
-                      ERRORMORPHEO(FUNCTION,"Unknow Condition");
-                      break;
-                    }
-                  }
-
-                if (use_dir)
-                  {
-                    ack[context] &= dir_ack;
-                    PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src);
-                    PORT_WRITE(out_PREDICT_DIR_STATIC      [i], address_dest<address_src); // if destination is previous : the static direction is take
-//                  PORT_WRITE(out_PREDICT_DIR_LAST_TAKE   [i], PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]));
-                  }
-
-                if (use_ras)
-                  {
-                    ack[context] &= ras_ack;
-                    if (_param->_have_port_context_id)
-                    PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID   [i], context);
-                    PORT_WRITE(out_PREDICT_RAS_PUSH         [i], push); 
-                    PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); 
-
-                    is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate
-                  }
-
-                if (use_upt)
-                  {
-                    ack[context] &= upt_ack;
-                    
-                    if (_param->_have_port_context_id)
-                    PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID       [i],context);
-                    PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC  [i],address_src);
-                    PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest);
-                    PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION    [i],condition);
-                    PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE    [i],direction);
-                    PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE  [i],is_accurate);
-//                  PORT_WRITE(out_PREDICT_UPT_DIR_HISTORY      [i],PORT_READ(in_PREDICT_DIR_HISTORY      [i]));
-                    PORT_WRITE(out_PREDICT_UPT_RAS_ADDRESS      [i],PORT_READ(in_PREDICT_RAS_ADDRESS_POP  [i]));
-//                  PORT_WRITE(out_PREDICT_UPT_RAS_INDEX        [i],PORT_READ(in_PREDICT_RAS_INDEX        [i]));
-                  }
-
-                // ack = 1 if :
-                //   *             btb_ack
-                //   * use_dir and dir_ack
-                //   * use_ras and ras_ack
-                //   * use_upt and upt_ack
-//              ack [context] = (btb_ack and 
-//                               (use_dir and dir_ack) and 
-//                               (use_ras and ras_ack) and 
-//                               (use_upt and upt_ack));
-
-                dir_val = (btb_ack and 
-                           use_dir and
-//                         use_ras and
-//                         use_upt and
-//                         (not use_dir or (use_dir and dir_ack)) and 
-                           (not use_ras or (use_ras and ras_ack)) and 
-                           (not use_upt or (use_upt and upt_ack)));
-
-                ras_val = (btb_ack and 
-//                         use_dir and
-                           use_ras and
-//                         use_upt and
-                           (not use_dir or (use_dir and dir_ack)) and 
-//                         (not use_ras or (use_ras and ras_ack)) and 
-                           (not use_upt or (use_upt and upt_ack)));
-
-                upt_val = (btb_ack and 
-//                         use_dir and
-//                         use_ras and
-                           use_upt and
-                           (not use_dir or (use_dir and dir_ack)) and 
-                           (not use_ras or (use_ras and ras_ack))//  and 
-//                         (not use_upt or (use_upt and upt_ack))
-                           );
-
-//              pc_next      - is previously computed
-//              branch_state - is previously computed
-
-                Taddress_t address_src_lsb  = address_src%_param->_nb_instruction [context];
-
-                log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * address_src     : 0x%x",address_src);
+
+                Taddress_t          address_src      = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC  [i]);
+                Taddress_t          address_src_lsb  = address_src%_param->_nb_instruction [context];
+
+                inst_ifetch_ptr = address_src_lsb;
+
+                log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * address_src     : 0x%.8x (0x%.8x)",address_src,address_src<<2);
                 log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * address_src_lsb : %d",address_src_lsb);
 
-                if (address_src_lsb == (_param->_nb_instruction [context]-1))
+                // Special case :
+                //   * BTB hit and the branchement is the PC current and it's the last slot.
+                //     -> next pc must be the delay slot
+                if ((not pc_current_is_ds_take) and // if pc_current is ds_take, alors pc_next is the destination of branchement
+                    (address_src_lsb == (_param->_nb_instruction [context]-1)))
                   {
                     // branch is in the last slot of the packet
                     log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * branch is in the last slot of the packet");
                 
+                    // Branch is the last slot : next paquet is the delay slot
+                    pc_next            = address_src+1; // sequencial
+                    pc_next_is_ds_take = 1;
                     address_msb        = _param->_nb_instruction [context]; // == (address_src_lsb+1)
-                    pc_next_is_ds_take = 1;
+                    branch_state       = BRANCH_STATE_NONE;
                   }
                 else
                   {
+                    Tbranch_condition_t condition    = PORT_READ(in_PREDICT_BTB_CONDITION    [i]);
+                    Taddress_t          address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]);
+                    Tcontrol_t          push     ;
+                    Tcontrol_t          direction;
+                    
+                    log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * condition             : %s"    ,toString(condition).c_str());
+                    log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * address_src           : 0x%.8x (0x%.8x)",address_src ,address_src <<2);
+                    log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * address_dest          : 0x%.8x (0x%.8x)",address_dest,address_dest<<2);
+                    
+                    switch (condition)
+                      {
+                      case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK          : // l.j
+                        {
+                          log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK");
+                          
+                          // use none unit (dir, upt and ras)
+                          direction    = true;
+                          pc_next      = address_dest;
+                          branch_state = BRANCH_STATE_NSPEC_TAKE;
+                          break;
+                        }
+                      case BRANCH_CONDITION_NONE_WITH_WRITE_STACK             : // l.jal
+                        {
+                          log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * BRANCH_CONDITION_NONE_WITH_WRITE_STACK");
+                          
+                          use_upt      = true;
+                          use_ras      = true;
+                          push         = true;
+                          direction    = true;
+                          pc_next      = address_dest;
+                          branch_state = BRANCH_STATE_NSPEC_TAKE;
+                          break;
+                        }
+                      case BRANCH_CONDITION_FLAG_UNSET                        : // l.bnf
+                      case BRANCH_CONDITION_FLAG_SET                          : // l.bf
+                        {
+                          log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * BRANCH_CONDITION_FLAG");
+                          
+                          use_upt      = true;
+                          use_dir      = true;
+                          // Test direction
+                          direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same
+                          if (direction = 1)
+                            {
+                              branch_state = BRANCH_STATE_SPEC_TAKE;
+                              pc_next      = address_dest;
+                            }
+                          else
+                            {
+                              branch_state = BRANCH_STATE_SPEC_NTAKE;
+                              pc_next      = address_src+2; // +1 = delay slot
+                            }
+                          break;
+                        }
+                      case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : // l.jr (rb!=9)
+                        {
+                          log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK");
+                          
+                          use_upt      = true;
+                          use_ras      = true;
+                          push         = true;
+                          direction    = true;
+                          pc_next      = address_dest;
+                          branch_state = BRANCH_STATE_SPEC_TAKE;
+                          break;
+                        }
+                      case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK    : // l.jalr
+                        {
+                          log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK");
+                          
+                          use_upt      = true;
+                          use_ras      = true;
+                          push         = true;
+                          direction    = true;
+                          pc_next      = address_dest;
+                          branch_state = BRANCH_STATE_NSPEC_TAKE;
+                          break;
+                        }
+                      case BRANCH_CONDITION_READ_STACK                        : // l.jr (rb==9)
+                        {
+                          log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * BRANCH_CONDITION_READ_STACK");
+                          use_upt      = true;
+                          use_ras      = true;
+                          push         = false;
+                          direction    = true;
+                          pc_next      = PORT_READ(in_PREDICT_RAS_ADDRESS_POP  [i]);
+                          branch_state = BRANCH_STATE_SPEC_TAKE;
+                          break;
+                        }
+                      default :
+                        {
+                          ERRORMORPHEO(FUNCTION,"Unknow Condition");
+                          break;
+                        }
+                      }
+                    
+                    if (use_dir)
+                      {
+                        ack[context] &= dir_ack;
+                        PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src);
+                        PORT_WRITE(out_PREDICT_DIR_STATIC      [i], address_dest<address_src); // if destination is previous : the static direction is take
+//                      PORT_WRITE(out_PREDICT_DIR_LAST_TAKE   [i], PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]));
+                      }
+                    
+                    if (use_ras)
+                      {
+                        ack[context] &= ras_ack;
+                        if (_param->_have_port_context_id)
+                        PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID   [i], context);
+                        PORT_WRITE(out_PREDICT_RAS_PUSH         [i], push); 
+                        PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); 
+                        
+                        is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate
+                      }
+                    
+                    if (use_upt)
+                      {
+                        ack[context] &= upt_ack;
+                        
+                        if (_param->_have_port_context_id)
+                        PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID       [i],context);
+                        PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC  [i],address_src);
+                        PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest);
+                        PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION    [i],condition);
+                        PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE    [i],direction);
+                        PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE  [i],is_accurate);
+//                      PORT_WRITE(out_PREDICT_UPT_DIR_HISTORY      [i],PORT_READ(in_PREDICT_DIR_HISTORY      [i]));
+                        PORT_WRITE(out_PREDICT_UPT_RAS_ADDRESS      [i],PORT_READ(in_PREDICT_RAS_ADDRESS_POP  [i]));
+//                      PORT_WRITE(out_PREDICT_UPT_RAS_INDEX        [i],PORT_READ(in_PREDICT_RAS_INDEX        [i]));
+                      }
+                    
+                    // ack = 1 if :
+                    //   *             btb_ack
+                    //   * use_dir and dir_ack
+                    //   * use_ras and ras_ack
+                    //   * use_upt and upt_ack
+//                  ack [context] = (btb_ack and 
+//                                   (use_dir and dir_ack) and 
+//                                   (use_ras and ras_ack) and 
+//                                   (use_upt and upt_ack));
+
+                    dir_val = (btb_ack and 
+                               use_dir and
+//                             use_ras and
+//                             use_upt and
+//                             (not use_dir or (use_dir and dir_ack)) and 
+                               (not use_ras or (use_ras and ras_ack)) and 
+                               (not use_upt or (use_upt and upt_ack)));
+                    
+                    ras_val = (btb_ack and 
+//                             use_dir and
+                               use_ras and
+//                             use_upt and
+                               (not use_dir or (use_dir and dir_ack)) and 
+//                             (not use_ras or (use_ras and ras_ack)) and 
+                               (not use_upt or (use_upt and upt_ack)));
+                    
+                    upt_val = (btb_ack and 
+//                             use_dir and
+//                             use_ras and
+                               use_upt and
+                               (not use_dir or (use_dir and dir_ack)) and 
+                               (not use_ras or (use_ras and ras_ack))//  and 
+//                             (not use_upt or (use_upt and upt_ack))
+                               );
+                    
+//                  pc_next      - is previously computed
+//                  branch_state - is previously computed
+
+
                     // branch is in the last slot of the packet
                     address_msb        = (address_src_lsb+2); // +1 == delayed slot
                     pc_next_is_ds_take = 0;
                   }
-                log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * address_msb     : %d",address_msb);
-
-                inst_ifetch_ptr             = address_src_lsb;
+
 //              branch_update_prediction_id = (_param->_have_port_depth)?((PORT_READ(in_DEPTH_UPT_TAIL[context])+PORT_READ(in_DEPTH_UPT_NB_BRANCH [context]))%_param->_array_size_depth[context]):0;
               }
@@ -308,5 +340,6 @@
                 log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * BTB miss : sequential order");
 
-                pc_next                     = address-address_lsb+_param->_nb_instruction [context]; // sequencial
+                // Take the address packet base and add new packet
+                pc_next                     = pc_current-address_lsb+_param->_nb_instruction [context]; // sequencial
                 pc_next_is_ds_take          = 0; // no branch, also no delay slot
                 inst_ifetch_ptr             = 0;
@@ -316,28 +349,35 @@
                 address_msb = _param->_nb_instruction [context];
               }
-              
-              PORT_WRITE(out_PREDICT_PC_NEXT                     [context]   , pc_next                    );
-              PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE          [context]   , pc_next_is_ds_take         );
-
-              Taddress_t address_limit_min = address_lsb;
-              Taddress_t address_limit_max = ((pc_current_is_ds_take)?(address_lsb+1):address_msb);
-
-              log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * instruction enable :");
-              log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * nb_inst : %d",_param->_nb_instruction [context]);
-              log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * [0:%d[ = 0" ,address_limit_min);
-              log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * [%d:%d[ = 1",address_limit_min,address_limit_max);
-              log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * [%d:%d[ = 0",address_limit_max,_param->_nb_instruction [context]);
-
-              for (uint32_t j=0; j<address_limit_min; j++)
-              PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE          [context][j], 0); // Before the address : not valid
-              for (uint32_t j=address_limit_min; j<address_limit_max; j++)
-              PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE          [context][j], 1); // Vald packet
-              for (uint32_t j=address_limit_max; j<_param->_nb_instruction [context]; j++)
-              PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE          [context][j], 0); // After last address (branch) : not valid
-              if (_param->_have_port_inst_ifetch_ptr)
-              PORT_WRITE(out_PREDICT_INST_IFETCH_PTR             [context]   , inst_ifetch_ptr            );
-              PORT_WRITE(out_PREDICT_BRANCH_STATE                [context]   , branch_state               );
-              if (_param->_have_port_depth)
-              PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context]   , PORT_READ(in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID [i]));
+
+            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * address_msb           : %d",address_msb);
+            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * pc_next               : 0x%.8x (0x%.8x)",pc_next,pc_next<<2);
+            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * pc_next_is_ds_take    : %d"    ,pc_next_is_ds_take);
+            
+            // Write Output
+            PORT_WRITE(out_PREDICT_PC_NEXT                     [context]   , pc_next                    );
+            PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE          [context]   , pc_next_is_ds_take         );
+
+            // Create enable mask
+            Taddress_t address_limit_min = address_lsb;
+            Taddress_t address_limit_max = ((pc_current_is_ds_take)?(address_lsb+1):address_msb);
+
+            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"    * instruction enable :");
+            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * nb_inst : %d",_param->_nb_instruction [context]);
+            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * [0:%d[ = 0" ,address_limit_min);
+            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * [%d:%d[ = 1",address_limit_min,address_limit_max);
+            log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"      * [%d:%d[ = 0",address_limit_max,_param->_nb_instruction [context]);
+
+            for (uint32_t j=0; j<address_limit_min; j++)
+            PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE          [context][j], 0); // Before the address : not valid
+            for (uint32_t j=address_limit_min; j<address_limit_max; j++)
+            PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE          [context][j], 1); // Valid packet
+            for (uint32_t j=address_limit_max; j<_param->_nb_instruction [context]; j++)
+            PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE          [context][j], 0); // After last address (branch) : not valid
+
+            if (_param->_have_port_inst_ifetch_ptr)
+            PORT_WRITE(out_PREDICT_INST_IFETCH_PTR             [context]   , inst_ifetch_ptr            );
+            PORT_WRITE(out_PREDICT_BRANCH_STATE                [context]   , branch_state               );
+            if (_param->_have_port_depth)
+            PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context]   , PORT_READ(in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID [i]));
           }
 
@@ -348,5 +388,6 @@
         PORT_WRITE(out_PREDICT_UPT_VAL [i], upt_val);
       }
-
+    
+    // Write output
     for (uint32_t i=0; i<_param->_nb_context; i++)
       PORT_WRITE(out_PREDICT_ACK[i],ack[i]);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp	(revision 100)
@@ -125,5 +125,9 @@
 
   // Initialisation
-
+  const bool test1 = true;
+  const bool test2 = true;
+  const bool test3 = true;
+  const bool test4 = true;
+  
   const uint32_t seed = 0;
 //const uint32_t seed = static_cast<uint32_t>(time(NULL));
@@ -144,275 +148,447 @@
     {
       LABEL("Iteration %d",iteration);
-
-      if (1)
+      
+      if (test1)
 	{
-	uint32_t port = rand()%_param->_nb_inst_predict;
-
-	LABEL("PREDICT - PUSH");
+          uint32_t port = rand()%_param->_nb_inst_predict;
+          
+          LABEL("PREDICT - PUSH");
+          
+          in_PREDICT_VAL  [port]->write(1);
+          in_PREDICT_PUSH [port]->write(1);
+          
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]; j++)
+              {
+                in_PREDICT_CONTEXT_ID   [port]->write(i);
+                in_PREDICT_ADDRESS_PUSH [port]->write(0xdeadbeef+j);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_PREDICT_ACK  [port]->read(), 1);
+                TEST(Tptr_t    , out_PREDICT_INDEX[port]->read(),(j+1)%_param->_size_queue[i]);
+                
+                SC_START(1);
+                
+              }
+          in_PREDICT_VAL [port]->write(0);
+          
+          SC_START(1);
+          
+          in_PREDICT_VAL  [port]->write(1);
+          in_PREDICT_PUSH [port]->write(1);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]; j++)
+              {
+                in_PREDICT_CONTEXT_ID   [port]->write(i);
+                in_PREDICT_ADDRESS_PUSH [port]->write(0x21071981+j);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_PREDICT_ACK        [port]->read(), 1);
+                TEST(Tptr_t    , out_PREDICT_INDEX      [port]->read(),(j+1)%_param->_size_queue[i]);
+                TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port]->read(),0xdeadbeef+j);
+                
+                SC_START(1);
+              }
+          in_PREDICT_VAL [port]->write(0);
+          
+          LABEL("PREDICT - POP");
+          
+          in_PREDICT_VAL  [port]->write(1);
+          in_PREDICT_PUSH [port]->write(0);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j< _param->_size_queue[i]; j++)
+              {
+                in_PREDICT_CONTEXT_ID   [port]->write(i);
+                in_PREDICT_ADDRESS_PUSH [port]->write(0xbabedead);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_PREDICT_ACK        [port]->read(), 1);
+                TEST(Tcontrol_t, out_PREDICT_HIT        [port]->read(), 1);
+                uint32_t k=(_param->_size_queue[i]-j)%_param->_size_queue[i];
+                TEST(Tptr_t    , out_PREDICT_INDEX      [port]->read(), k);
+                TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port]->read(),(0x21071981+((k==0)?(_param->_size_queue[i]-1):(k-1))));
+                
+                SC_START(1);
+              }
+          in_PREDICT_VAL [port]->write(0);
+
+          // Now, the stack is empty
+        }
+
+      if (test2)
+	{
+          uint32_t port = rand()%_param->_nb_inst_decod;
+          
+          LABEL("DECOD - without predict");
+          
+          LABEL("DECOD - PUSH");  
+          
+          in_DECOD_VAL             [port]->write(1);
+          in_DECOD_PUSH            [port]->write(1);
+          in_DECOD_MISS_PREDICTION [port]->write(0);
+          
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]; j++)
+              {
+                in_DECOD_CONTEXT_ID   [port]->write(i);
+                in_DECOD_ADDRESS_PUSH [port]->write(0xbeefcaca+j);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_DECOD_ACK  [port]->read(), 1);
+                TEST(Tptr_t    , out_DECOD_INDEX[port]->read(),(j+1)%_param->_size_queue[i]);
+                
+                SC_START(1);
+                
+              }
+          in_DECOD_VAL [port]->write(0);
 	
-	in_PREDICT_VAL  [port]->write(1);
-	in_PREDICT_PUSH [port]->write(1);
-	for (uint32_t i=0; i<_param->_nb_context; i++)
-	  for (uint32_t j=0; j<_param->_size_queue[i]; j++)
-	    {
-	      in_PREDICT_CONTEXT_ID   [port]->write(i);
-	      in_PREDICT_ADDRESS_PUSH [port]->write(0xdeadbeef+j);
-	      
-	      SC_START(0);
-	      
-	      TEST(Tcontrol_t, out_PREDICT_ACK  [port]->read(), 1);
-	      TEST(Tptr_t    , out_PREDICT_INDEX[port]->read(),(j+1)%_param->_size_queue[i]);
-	      
-	      SC_START(1);
-	      
-	    }
-	in_PREDICT_VAL [port]->write(0);
-	
-	SC_START(1);
-	
-	in_PREDICT_VAL  [port]->write(1);
-	in_PREDICT_PUSH [port]->write(1);
-	for (uint32_t i=0; i<_param->_nb_context; i++)
-	  for (uint32_t j=0; j<_param->_size_queue[i]; j++)
-	    {
-	      in_PREDICT_CONTEXT_ID   [port]->write(i);
-	      in_PREDICT_ADDRESS_PUSH [port]->write(0x21071981+j);
-	      
-	      SC_START(0);
-	      
-	      TEST(Tcontrol_t, out_PREDICT_ACK        [port]->read(), 1);
-	      TEST(Tptr_t    , out_PREDICT_INDEX      [port]->read(),(j+1)%_param->_size_queue[i]);
-	      TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port]->read(),0xdeadbeef+j);
-	      
-	      SC_START(1);
-	    }
-	in_PREDICT_VAL [port]->write(0);
-	
-	LABEL("PREDICT - POP");
-	
-	in_PREDICT_VAL  [port]->write(1);
-	in_PREDICT_PUSH [port]->write(0);
-	for (uint32_t i=0; i<_param->_nb_context; i++)
-	  for (uint32_t j=0; j< _param->_size_queue[i]; j++)
-	    {
-	      in_PREDICT_CONTEXT_ID   [port]->write(i);
-	      in_PREDICT_ADDRESS_PUSH [port]->write(0xbabedead);
-	      
-	      SC_START(0);
-	      
-	      TEST(Tcontrol_t, out_PREDICT_ACK        [port]->read(), 1);
-	      TEST(Tcontrol_t, out_PREDICT_HIT        [port]->read(), 1);
-	      uint32_t k=(_param->_size_queue[i]-j)%_param->_size_queue[i];
-	      TEST(Tptr_t    , out_PREDICT_INDEX      [port]->read(), k);
-	      TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port]->read(),(0x21071981+((k==0)?(_param->_size_queue[i]-1):(k-1))));
-	      
-	      SC_START(1);
-	    }
-	in_PREDICT_VAL [port]->write(0);
-	}
-
-      // Now, the stack is empty
-
-      if (1)
-	{
-	uint32_t port1 = rand()%_param->_nb_inst_decod;
-	uint32_t port2 = rand()%_param->_nb_inst_predict;
-
-	LABEL("DECOD - without predict");
-	
-	LABEL("DECOD - PUSH");  
-	
-	in_DECOD_VAL             [port1]->write(1);
-	in_DECOD_PUSH            [port1]->write(1);
-	in_DECOD_MISS_PREDICTION [port1]->write(0);
-	
-	for (uint32_t i=0; i<_param->_nb_context; i++)
-	  for (uint32_t j=0; j<_param->_size_queue[i]; j++)
-	    {
-	      in_DECOD_CONTEXT_ID   [port1]->write(i);
-	      in_DECOD_ADDRESS_PUSH [port1]->write(0xbeefcaca+j);
-	      
-	      SC_START(0);
-	      
-	      TEST(Tcontrol_t, out_DECOD_ACK  [port1]->read(), 1);
-	      TEST(Tptr_t    , out_DECOD_INDEX[port1]->read(),(j+1)%_param->_size_queue[i]);
-	      
-	      SC_START(1);
-	      
-	    }
-	in_DECOD_VAL [port1]->write(0);
-	
-	SC_START(1);
-	
-	in_DECOD_VAL  [port1]->write(1);
-	in_DECOD_PUSH [port1]->write(1);
-	for (uint32_t i=0; i<_param->_nb_context; i++)
-	  for (uint32_t j=0; j<_param->_size_queue[i]; j++)
-	    {
-	      in_DECOD_CONTEXT_ID   [port1]->write(i);
-	      in_DECOD_ADDRESS_PUSH [port1]->write(0x21071981+j);
-	      
-	      SC_START(0);
-	      
-	      TEST(Tcontrol_t, out_DECOD_ACK        [port1]->read(), 1);
-	      TEST(Tptr_t    , out_DECOD_INDEX      [port1]->read(),(j+1)%_param->_size_queue[i]);
-	      TEST(Taddress_t, out_DECOD_ADDRESS_POP[port1]->read(),0xbeefcaca+j);
-	      
-	      SC_START(1);
-	    }
-	in_DECOD_VAL [port1]->write(0);
-	
-	LABEL("DECOD - POP");
-	
-	in_DECOD_VAL  [port1]->write(1);
-	in_DECOD_PUSH [port1]->write(0);
-	for (uint32_t i=0; i<_param->_nb_context; i++)
-	  for (uint32_t j=0; j< _param->_size_queue[i]; j++)
-	    {
-	      in_DECOD_CONTEXT_ID   [port1]->write(i);
-	      in_DECOD_ADDRESS_PUSH [port1]->write(0xbabedead);
-	      
-	      SC_START(0);
-	      
-	      TEST(Tcontrol_t, out_DECOD_ACK        [port1]->read(), 1);
-	      TEST(Tcontrol_t, out_DECOD_HIT        [port1]->read(), 1);
-	      uint32_t k=(_param->_size_queue[i]-j)%_param->_size_queue[i];
-	      TEST(Tptr_t    , out_DECOD_INDEX      [port1]->read(), k);
-	      TEST(Taddress_t, out_DECOD_ADDRESS_POP[port1]->read(),(0x21071981+((k==0)?(_param->_size_queue[i]-1):(k-1))));
-	      
-	      SC_START(1);
-	    }
-	in_DECOD_VAL [port1]->write(0);
-
-	LABEL("DECOD - with predict");
-	
-	LABEL("DECOD - PUSH (size_queue/2)");  
-	
-	in_DECOD_VAL             [port1]->write(1);
-	in_DECOD_PUSH            [port1]->write(1);
-	in_DECOD_MISS_PREDICTION [port1]->write(1);
-	
-	for (uint32_t i=0; i<_param->_nb_context; i++)
-	  for (uint32_t j=0; j<_param->_size_queue[i]/2;j++)
-	    {
-	      in_DECOD_CONTEXT_ID   [port1]->write(i);
-	      in_DECOD_ADDRESS_PUSH [port1]->write(0x01234567+j);
-	      
-	      SC_START(0);
-	      
-	      TEST(Tcontrol_t, out_DECOD_ACK  [port1]->read(), 1);
-	      TEST(Tptr_t    , out_DECOD_INDEX[port1]->read(),(j+1)%_param->_size_queue[i]);
-	      
-	      SC_START(1);
-	      
-	    }
-	in_DECOD_VAL [port1]->write(0);
-
-	LABEL("PREDICT - PUSH (size_queue/2)");  
-	
-	in_PREDICT_VAL             [port2]->write(1);
-	in_PREDICT_PUSH            [port2]->write(1);
-	
-	for (uint32_t i=0; i<_param->_nb_context; i++)
-	  for (uint32_t j=0; j<_param->_size_queue[i]/2;j++)
-	    {
-	      in_PREDICT_CONTEXT_ID   [port2]->write(i);
-	      in_PREDICT_ADDRESS_PUSH [port2]->write((0x89abcdef+j)+(_param->_size_queue[i]/2));
-	      
-	      SC_START(0);
-	      
-	      TEST(Tcontrol_t, out_PREDICT_ACK  [port2]->read(), 1);
-	      TEST(Tptr_t    , out_PREDICT_INDEX[port2]->read(),(j+1+(_param->_size_queue[i]/2))%_param->_size_queue[i]);
-	      
-	      SC_START(1);
-	    }
-
-	in_PREDICT_VAL [port2]->write(0);
-
-	LABEL("PREDICT - POP (size_queue/2)");  
-
-	in_PREDICT_VAL  [port2]->write(1);
-	in_PREDICT_PUSH [port2]->write(0);
-	for (uint32_t i=0; i<_param->_nb_context; i++)
-	  {
-	    for (uint32_t j=0; j< _param->_size_queue[i]/2; j++)
-	      {
-		in_PREDICT_CONTEXT_ID   [port2]->write(i);
-		in_PREDICT_ADDRESS_PUSH [port2]->write(0xbabedead);
-		
-		SC_START(0);
-		
-		TEST(Tcontrol_t, out_PREDICT_ACK        [port2]->read(), 1);
-		TEST(Tcontrol_t, out_PREDICT_HIT        [port2]->read(), 1);
-		uint32_t k=  (_param->_size_queue[i]-j)%_param->_size_queue[i];
-		TEST(Tptr_t    , out_PREDICT_INDEX      [port2]->read(), k);
-
-		Taddress_t res = (0x89abcdef+((k==0)?(_param->_size_queue[i]-1):(k-1)));
-		LABEL("k      : %d",k);
-		LABEL("res    : %x",res);
-		LABEL("@_pop  : %x",out_PREDICT_ADDRESS_POP[port2]->read());
-
-		TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port2]->read(),res);
-		
-		SC_START(1);
-	      }
-
-	    for (uint32_t j=0; j< _param->_size_queue[i]/2; j++)
-	      {
-		in_PREDICT_CONTEXT_ID   [port2]->write(i);
-		in_PREDICT_ADDRESS_PUSH [port2]->write(0xbabedead);
-		
-		SC_START(0);
-		
-		TEST(Tcontrol_t, out_PREDICT_ACK        [port2]->read(), 1);
-		TEST(Tcontrol_t, out_PREDICT_HIT        [port2]->read(), 1);
-		uint32_t k=(_param->_size_queue[i]/2-j)%_param->_size_queue[i];
-		TEST(Tptr_t    , out_PREDICT_INDEX      [port2]->read(), k);
-
-		Taddress_t res = (0x01234567+((k==0)?(_param->_size_queue[i]/2-1):(k-1)));
-
-		LABEL("k      : %d",k);
-		LABEL("res    : %x",res);
-		LABEL("@_pop  : %x",out_PREDICT_ADDRESS_POP[port2]->read());
-
-		TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port2]->read(),res);
-		
-		SC_START(1);
-	      }
-	  }
-
-	in_PREDICT_VAL [port2]->write(0);
-
-	in_DECOD_VAL  [port1]->write(1);
-	in_DECOD_PUSH [port1]->write(0);
-	in_DECOD_MISS_PREDICTION [port1]->write(0);
-
-	for (uint32_t i=0; i<_param->_nb_context; i++)
-	  {
-	    for (uint32_t j=0; j< _param->_size_queue[i]/2; j++)
-	      {
-		in_DECOD_CONTEXT_ID   [port1]->write(i);
-		in_DECOD_ADDRESS_PUSH [port1]->write(0xbabedead);
-		
-		SC_START(0);
-		
-		TEST(Tcontrol_t, out_DECOD_ACK        [port1]->read(), 1);
-		TEST(Tcontrol_t, out_DECOD_HIT        [port1]->read(), 1);
-		uint32_t k=(_param->_size_queue[i]/2-j)%_param->_size_queue[i];
-		TEST(Tptr_t    , out_DECOD_INDEX      [port1]->read(), k);
-
-		Taddress_t res = (0x01234567+((k==0)?(_param->_size_queue[i]/2-1):(k-1)));
-
-		LABEL("k      : %d",k);
-		LABEL("res    : %x",res);
-		LABEL("@_pop  : %x",out_DECOD_ADDRESS_POP[port1]->read());
-
-		TEST(Taddress_t, out_DECOD_ADDRESS_POP[port1]->read(),res);
-		
-		SC_START(1);
-	      }
-	  }
-
-	in_DECOD_VAL [port1]->write(0);
+          SC_START(1);
+          
+          in_DECOD_VAL  [port]->write(1);
+          in_DECOD_PUSH [port]->write(1);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]; j++)
+              {
+                in_DECOD_CONTEXT_ID   [port]->write(i);
+                in_DECOD_ADDRESS_PUSH [port]->write(0x21071981+j);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_DECOD_ACK        [port]->read(), 1);
+                TEST(Tptr_t    , out_DECOD_INDEX      [port]->read(),(j+1)%_param->_size_queue[i]);
+                TEST(Taddress_t, out_DECOD_ADDRESS_POP[port]->read(),0xbeefcaca+j);
+                
+                SC_START(1);
+              }
+          in_DECOD_VAL [port]->write(0);
+          
+          LABEL("DECOD - POP");
+          
+          in_DECOD_VAL  [port]->write(1);
+          in_DECOD_PUSH [port]->write(0);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j< _param->_size_queue[i]; j++)
+              {
+                in_DECOD_CONTEXT_ID   [port]->write(i);
+                in_DECOD_ADDRESS_PUSH [port]->write(0xbabedead);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_DECOD_ACK        [port]->read(), 1);
+                TEST(Tcontrol_t, out_DECOD_HIT        [port]->read(), 1);
+                uint32_t k=(_param->_size_queue[i]-j)%_param->_size_queue[i];
+                TEST(Tptr_t    , out_DECOD_INDEX      [port]->read(), k);
+                TEST(Taddress_t, out_DECOD_ADDRESS_POP[port]->read(),(0x21071981+((k==0)?(_param->_size_queue[i]-1):(k-1))));
+                
+                SC_START(1);
+              }
+          in_DECOD_VAL [port]->write(0);
+          // Now, the stack is empty
+        }
+
+      if (test3)
+        {
+          uint32_t port1 = rand()%_param->_nb_inst_predict;
+          uint32_t port2 = rand()%_param->_nb_inst_decod;
+          uint32_t port3 = rand()%_param->_nb_inst_update;
+
+          LABEL("Test UPDATE");
+
+          LABEL("Predict");
+          in_PREDICT_VAL  [port1]->write(1);
+          in_PREDICT_PUSH [port1]->write(1);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]; j++)
+              {
+                in_PREDICT_CONTEXT_ID   [port1]->write(i);
+                in_PREDICT_ADDRESS_PUSH [port1]->write(0x25071959+j);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_PREDICT_ACK        [port1]->read(), 1);
+                TEST(Tptr_t    , out_PREDICT_INDEX      [port1]->read(),(j+1)%_param->_size_queue[i]);
+//              TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port1]->read(),0xdeadbeef+j);
+                
+                SC_START(1);
+              }
+          in_PREDICT_VAL [port1]->write(0);
+
+          LABEL("Decod");
+          in_DECOD_VAL  [port2]->write(1);
+          in_DECOD_PUSH [port2]->write(1);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]/2; j++)
+              {
+                in_DECOD_CONTEXT_ID      [port2]->write(i);
+                in_DECOD_ADDRESS_PUSH    [port2]->write(0x25071959+j);
+                in_DECOD_MISS_PREDICTION [port2]->write(0);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_DECOD_ACK        [port2]->read(), 1);
+                TEST(Tptr_t    , out_DECOD_INDEX      [port2]->read(),(j+1)%_param->_size_queue[i]);
+                TEST(Taddress_t, out_DECOD_ADDRESS_POP[port2]->read(),0x25071959+j);
+                
+                SC_START(1);
+              }
+          in_DECOD_VAL [port2]->write(0);
+
+          LABEL("Update Decod OK");
+          in_UPDATE_VAL  [port3]->write(1);
+          in_UPDATE_PUSH [port3]->write(1);
+          in_UPDATE_FLUSH[port3]->write(0);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]/2; j++)
+              {
+                uint32_t x=(_param->_size_queue[i]/2)-1;
+                in_UPDATE_CONTEXT_ID        [port3]->write(i);
+                in_UPDATE_MISS_PREDICTION   [port3]->write(0);
+                in_UPDATE_PREDICTION_IFETCH [port3]->write(0);
+                in_UPDATE_INDEX             [port3]->write((x+1)%_param->_size_queue[i]);
+                in_UPDATE_ADDRESS           [port3]->write(0x25071959+x);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_UPDATE_ACK        [port3]->read(), 1);
+                
+                SC_START(1);
+              }
+          in_UPDATE_VAL [port3]->write(0);
+
+          LABEL("Update FLUSH");
+          in_UPDATE_VAL  [port3]->write(1);
+          in_UPDATE_FLUSH[port3]->write(1);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]/2; j++)
+              {
+                in_UPDATE_CONTEXT_ID        [port3]->write(i);
+                SC_START(1);
+                TEST(Tcontrol_t, out_UPDATE_ACK        [port3]->read(), 1);
+              }
+          in_UPDATE_VAL [port3]->write(0);
+
+
+// Tcontrol_t, in_UPDATE_VAL               
+// Tcontrol_t,out_UPDATE_ACK               
+// Tcontext_t, in_UPDATE_CONTEXT_ID        
+// Tcontrol_t, in_UPDATE_PUSH              
+// Tcontrol_t, in_UPDATE_FLUSH             
+// Tptr_t    , in_UPDATE_INDEX             
+// Taddress_t, in_UPDATE_ADDRESS           
+// Tcontrol_t, in_UPDATE_MISS_PREDICTION   
+// Tcontrol_t, in_UPDATE_PREDICTION_IFETCH 
+
+
+        }
+
+      if (test4)
+        {
+          uint32_t port1 = rand()%_param->_nb_inst_predict;
+          uint32_t port2 = rand()%_param->_nb_inst_decod;
+          uint32_t port3 = rand()%_param->_nb_inst_update;
+
+          LABEL("Test UPDATE");
+
+          LABEL("Predict");
+          in_PREDICT_VAL  [port1]->write(1);
+          in_PREDICT_PUSH [port1]->write(1);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]; j++)
+              {
+                in_PREDICT_CONTEXT_ID   [port1]->write(i);
+                in_PREDICT_ADDRESS_PUSH [port1]->write(0x14011959+j);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_PREDICT_ACK        [port1]->read(), 1);
+                TEST(Tptr_t    , out_PREDICT_INDEX      [port1]->read(),(j+1)%_param->_size_queue[i]);
+//              TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port1]->read(),0xdeadbeef+j);
+                
+                SC_START(1);
+              }
+          in_PREDICT_VAL [port1]->write(0);
+
+          LABEL("Decod");
+          in_DECOD_VAL  [port2]->write(1);
+          in_DECOD_PUSH [port2]->write(1);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]/2; j++)
+              {
+                in_DECOD_CONTEXT_ID      [port2]->write(i);
+                in_DECOD_ADDRESS_PUSH    [port2]->write(0x14011959+j);
+                in_DECOD_MISS_PREDICTION [port2]->write(0);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_DECOD_ACK        [port2]->read(), 1);
+                TEST(Tptr_t    , out_DECOD_INDEX      [port2]->read(),(j+1)%_param->_size_queue[i]);
+                TEST(Taddress_t, out_DECOD_ADDRESS_POP[port2]->read(),0x14011959+j);
+                
+                SC_START(1);
+              }
+          in_DECOD_VAL [port2]->write(0);
+
+          LABEL("Update Decod KO");
+          in_UPDATE_VAL  [port3]->write(1);
+          in_UPDATE_PUSH [port3]->write(1);
+          in_UPDATE_FLUSH[port3]->write(0);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]/2; j++)
+              {
+                uint32_t x=(_param->_size_queue[i]/2);
+                in_UPDATE_CONTEXT_ID        [port3]->write(i);
+                in_UPDATE_MISS_PREDICTION   [port3]->write(1);
+                in_UPDATE_PREDICTION_IFETCH [port3]->write(0);
+                in_UPDATE_INDEX             [port3]->write((x-j)%_param->_size_queue[i]);
+                in_UPDATE_ADDRESS           [port3]->write(0xffffffff+x);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_UPDATE_ACK        [port3]->read(), 1);
+                
+                SC_START(1);
+              }
+          in_UPDATE_VAL [port3]->write(0);
+
+          LABEL("Decod");
+          in_DECOD_VAL  [port2]->write(1);
+          in_DECOD_PUSH [port2]->write(1);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]/2; j++)
+              {
+                in_DECOD_CONTEXT_ID      [port2]->write(i);
+                in_DECOD_ADDRESS_PUSH    [port2]->write(0x14011959+j);
+                in_DECOD_MISS_PREDICTION [port2]->write(0);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_DECOD_ACK        [port2]->read(), 1);
+                TEST(Tptr_t    , out_DECOD_INDEX      [port2]->read(),(j+1)%_param->_size_queue[i]);
+                TEST(Taddress_t, out_DECOD_ADDRESS_POP[port2]->read(),0x14011959+j);
+                
+                SC_START(1);
+              }
+          in_DECOD_VAL [port2]->write(0);
+
+
+          LABEL("Update Decod KO");
+          in_UPDATE_VAL  [port3]->write(1);
+          in_UPDATE_PUSH [port3]->write(1);
+          in_UPDATE_FLUSH[port3]->write(0);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]/2; j++)
+              {
+                uint32_t x=(_param->_size_queue[i]/2);
+                in_UPDATE_CONTEXT_ID        [port3]->write(i);
+                in_UPDATE_MISS_PREDICTION   [port3]->write(1);
+                in_UPDATE_PREDICTION_IFETCH [port3]->write(0);
+                in_UPDATE_INDEX             [port3]->write((x-j)%_param->_size_queue[i]);
+                in_UPDATE_ADDRESS           [port3]->write(0xffffffff+x);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_UPDATE_ACK        [port3]->read(), 1);
+                
+                SC_START(1);
+              }
+          in_UPDATE_VAL [port3]->write(0);
+
+          LABEL("Update Predict KO");
+          in_UPDATE_VAL  [port3]->write(1);
+          in_UPDATE_PUSH [port3]->write(1);
+          in_UPDATE_FLUSH[port3]->write(0);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]; j++)
+              {
+                uint32_t x=(_param->_size_queue[i]);
+                in_UPDATE_CONTEXT_ID        [port3]->write(i);
+                in_UPDATE_MISS_PREDICTION   [port3]->write(1);
+                in_UPDATE_PREDICTION_IFETCH [port3]->write(1);
+                in_UPDATE_INDEX             [port3]->write((x-j)%_param->_size_queue[i]);
+                in_UPDATE_ADDRESS           [port3]->write(0xffffffff+x);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_UPDATE_ACK        [port3]->read(), 1);
+                
+                SC_START(1);
+              }
+          in_UPDATE_VAL [port3]->write(0);
+
+          LABEL("Predict");
+          in_PREDICT_VAL  [port1]->write(1);
+          in_PREDICT_PUSH [port1]->write(1);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]; j++)
+              {
+                in_PREDICT_CONTEXT_ID   [port1]->write(i);
+                in_PREDICT_ADDRESS_PUSH [port1]->write(0x14011959+j);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_PREDICT_ACK        [port1]->read(), 1);
+                TEST(Tptr_t    , out_PREDICT_INDEX      [port1]->read(),(j+1)%_param->_size_queue[i]);
+                TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port1]->read(),0x14011959+j);
+                
+                SC_START(1);
+              }
+          in_PREDICT_VAL [port1]->write(0);
+
+          LABEL("Update Predict KO");
+          in_UPDATE_VAL  [port3]->write(1);
+          in_UPDATE_PUSH [port3]->write(0);
+          in_UPDATE_FLUSH[port3]->write(0);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]; j++)
+              {
+                uint32_t x=(_param->_size_queue[i]);
+                in_UPDATE_CONTEXT_ID        [port3]->write(i);
+                in_UPDATE_MISS_PREDICTION   [port3]->write(1);
+                in_UPDATE_PREDICTION_IFETCH [port3]->write(1);
+                in_UPDATE_INDEX             [port3]->write((x+j+1)%_param->_size_queue[i]);
+                in_UPDATE_ADDRESS           [port3]->write(0x87654321+j);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_UPDATE_ACK        [port3]->read(), 1);
+                
+                SC_START(1);
+              }
+          in_UPDATE_VAL [port3]->write(0);
+
+          LABEL("Predict");
+          in_PREDICT_VAL  [port1]->write(1);
+          in_PREDICT_PUSH [port1]->write(1);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]; j++)
+              {
+                in_PREDICT_CONTEXT_ID   [port1]->write(i);
+                in_PREDICT_ADDRESS_PUSH [port1]->write(0x14011959+j);
+                
+                SC_START(0);
+                
+                TEST(Tcontrol_t, out_PREDICT_ACK        [port1]->read(), 1);
+                TEST(Tptr_t    , out_PREDICT_INDEX      [port1]->read(),(j+1)%_param->_size_queue[i]);
+                TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port1]->read(),0x87654321+j);
+                
+                SC_START(1);
+              }
+          in_PREDICT_VAL [port1]->write(0);
+
+          LABEL("Update FLUSH");
+          in_UPDATE_VAL  [port3]->write(1);
+          in_UPDATE_FLUSH[port3]->write(1);
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            for (uint32_t j=0; j<_param->_size_queue[i]/2; j++)
+              {
+                in_UPDATE_CONTEXT_ID        [port3]->write(i);
+                SC_START(1);
+                TEST(Tcontrol_t, out_UPDATE_ACK        [port3]->read(), 1);
+              }
+          in_UPDATE_VAL [port3]->write(0);
         }
     }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h	(revision 100)
@@ -88,5 +88,5 @@
   public    : SC_IN (Tcontext_t)           **  in_UPDATE_CONTEXT_ID       ; //[nb_inst_update] 
   public    : SC_IN (Tcontrol_t)           **  in_UPDATE_PUSH             ; //[nb_inst_update]  1 = push, else pop
-  public    : SC_IN (Tcontrol_t)           **  in_UPDATE_FLUSH            ; //[nb_inst_update]  1 = push, else pop
+  public    : SC_IN (Tcontrol_t)           **  in_UPDATE_FLUSH            ; //[nb_inst_update]
   public    : SC_IN (Taddress_t)           **  in_UPDATE_ADDRESS          ; //[nb_inst_update]
   public    : SC_IN (Tptr_t    )           **  in_UPDATE_INDEX            ; //[nb_inst_update]
@@ -99,8 +99,8 @@
   private   : ras_entry_t                  ** reg_stack         ; //[nb_context][size_queue]
   private   : Tptr_t                        * reg_TOP           ; //[nb_context]
-  private   : Tptr_t                        * reg_BOTTOM        ; //[nb_context]
+//private   : Tptr_t                        * reg_BOTTOM        ; //[nb_context]
   private   : Tptr_t                        * reg_NB_ELT        ; //[nb_context]
   private   : Tptr_t                        * reg_PREDICT_TOP   ; //[nb_context]
-  private   : Tptr_t                        * reg_PREDICT_BOTTOM; //[nb_context]
+//private   : Tptr_t                        * reg_PREDICT_BOTTOM; //[nb_context]
   private   : Tptr_t                        * reg_PREDICT_NB_ELT; //[nb_context]
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Types.h	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Types.h	(revision 100)
@@ -21,7 +21,7 @@
   class ras_entry_t
   {
-  public : bool       _val    ;
-  public : bool       _predict;
-  public : bool       _miss   ;
+//public : bool       _val    ;
+//public : bool       _predict;
+//public : bool       _miss   ;
   public : Taddress_t _address;
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp	(revision 100)
@@ -107,9 +107,9 @@
 
     reg_TOP              = new Tptr_t     [_param->_nb_context];
-    reg_BOTTOM           = new Tptr_t     [_param->_nb_context];
+//  reg_BOTTOM           = new Tptr_t     [_param->_nb_context];
     reg_NB_ELT           = new Tptr_t     [_param->_nb_context];
 
     reg_PREDICT_TOP      = new Tptr_t     [_param->_nb_context];
-    reg_PREDICT_BOTTOM   = new Tptr_t     [_param->_nb_context];
+//  reg_PREDICT_BOTTOM   = new Tptr_t     [_param->_nb_context];
     reg_PREDICT_NB_ELT   = new Tptr_t     [_param->_nb_context];
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp	(revision 100)
@@ -64,8 +64,8 @@
         delete [] reg_stack;
         delete [] reg_TOP;
-        delete [] reg_BOTTOM;
+//      delete [] reg_BOTTOM;
         delete [] reg_NB_ELT;
         delete [] reg_PREDICT_TOP;
-        delete [] reg_PREDICT_BOTTOM;
+//      delete [] reg_PREDICT_BOTTOM;
         delete [] reg_PREDICT_NB_ELT;
         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_decod.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_decod.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_decod.cpp	(revision 100)
@@ -22,7 +22,9 @@
   void Return_Address_Stack::genMealy_decod (void)
   {
-    log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin");
+    log_begin(Return_Address_Stack,FUNCTION);
+    log_function(Return_Address_Stack,FUNCTION,_name.c_str());
 
 #ifdef DEBUG_TEST
+    // just to test if have many transaction on a same context
     bool context_valid [_param->_nb_context];
     for (uint32_t i=0; i<_param->_nb_context; i++)
@@ -32,4 +34,5 @@
     for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
       {
+        // Read context number
 	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
 
@@ -49,5 +52,5 @@
 	// if pop  : val and not miss
 	//   when the predictor : if hit = 0, wait (is not accurate)
-	internal_DECOD_HIT [i] = (push or (reg_stack[context][top]._val and not reg_stack[context][top]._miss and (reg_NB_ELT[context]>0)));
+	internal_DECOD_HIT [i] = (push or (reg_NB_ELT[context]>0));
 	PORT_WRITE(out_DECOD_HIT         [i], internal_DECOD_HIT [i]);
 
@@ -61,5 +64,5 @@
       }
 
-    log_printf(FUNC,Return_Address_Stack,FUNCTION,"End");
+    log_end(Return_Address_Stack,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_predict.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_predict.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_predict.cpp	(revision 100)
@@ -22,7 +22,9 @@
   void Return_Address_Stack::genMealy_predict (void)
   {
-    log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin");
+    log_begin(Return_Address_Stack,FUNCTION);
+    log_function(Return_Address_Stack,FUNCTION,_name.c_str());
 
 #ifdef DEBUG_TEST
+    // just to test if have many transaction on a same context
     bool context_valid [_param->_nb_context];
     for (uint32_t i=0; i<_param->_nb_context; i++)
@@ -32,6 +34,7 @@
     for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
       {
+        // Read context number
 	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
-
+        
 #ifdef DEBUG_TEST
 	if (PORT_READ(in_PREDICT_VAL [i]))
@@ -42,15 +45,18 @@
 	  }
 #endif
-
+        
+        // Get top
 	Tptr_t     top  = reg_PREDICT_TOP[context];
 	Tcontrol_t push = PORT_READ(in_PREDICT_PUSH [i]);
 
-	// if push : value is hit
-	// if pop  : val and not miss
-	internal_PREDICT_HIT [i] = (push or (reg_stack[context][top]._val and not reg_stack[context][top]._miss and (reg_PREDICT_NB_ELT[context]>0)));
+        // Hit :
+	//   * if push : value is hit
+	//   * if pop  : no empty
+	internal_PREDICT_HIT [i] = (push or (reg_PREDICT_NB_ELT[context]>0));
+
 	PORT_WRITE(out_PREDICT_HIT         [i], internal_PREDICT_HIT [i]);
 
 	// if pop  : address_pop   = stack [top]
-	// if push : stock [top+1] = address_push; also stock [top+1] is erase ! give the old value at the update table
+	// if push : stock [top+1] = address_push; also stack [top+1] is erase ! save the old value in the update table
 	if (push)
 	  top = (top+1)%_param->_size_queue[context];
@@ -60,5 +66,5 @@
       }
 
-    log_printf(FUNC,Return_Address_Stack,FUNCTION,"End");
+    log_end(Return_Address_Stack,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp	(revision 100)
@@ -22,24 +22,19 @@
   void Return_Address_Stack::transition (void)
   {
-    log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin");
+    log_begin(Return_Address_Stack,FUNCTION);
+    log_function(Return_Address_Stack,FUNCTION,_name.c_str());
 
     if (PORT_READ(in_NRESET)==0)
       {
+        // Reset all structure
 	for (uint32_t i=0; i<_param->_nb_context; i++)
 	  {
 	    reg_TOP    [i] = 0;
-	    reg_BOTTOM [i] = 0;
+// 	    reg_BOTTOM [i] = 0;
 	    reg_NB_ELT [i] = 0;
 
 	    reg_PREDICT_TOP    [i] = 0;
-	    reg_PREDICT_BOTTOM [i] = 0;
+// 	    reg_PREDICT_BOTTOM [i] = 0;
 	    reg_PREDICT_NB_ELT [i] = 0;
-
-	    for (uint32_t j=0; j<_param->_size_queue [i]; j++)
-	      {
-		reg_stack[i][j]._val     = false;
-		reg_stack[i][j]._predict = false;
-		reg_stack[i][j]._miss    = false;
-	      }
 	  }
       }
@@ -52,67 +47,76 @@
 	  if (PORT_READ(in_PREDICT_VAL [i]) and internal_PREDICT_ACK [i])
 	    {
-	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"PREDICT[%d] : Transaction",i);
+	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"  * PREDICT [%d] : Transaction",i);
+              
+              // Read information and pointer
 	      Tcontext_t context    = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
 	      Tcontrol_t push       = PORT_READ(in_PREDICT_PUSH [i]);
+
 	      Tptr_t     top_old    = reg_PREDICT_TOP    [context];
 	      Tptr_t     top_new    = top_old;
-	      Tptr_t     bottom_old = reg_PREDICT_BOTTOM [context];
-
-	      log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context);
-
-	      // Hit  : push or (val and not miss and not empty)
+// 	      Tptr_t     bottom_old = reg_PREDICT_BOTTOM [context];
+// 	      Tptr_t     bottom_new = bottom_old;
+	      Tptr_t     nb_elt_old = reg_PREDICT_NB_ELT [context];
+	      Tptr_t     nb_elt_new = nb_elt_old;
+
+	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * context : %d",context);
+
+	      // Hit  : push or not empty
 	      // Miss : ifetch is stall, no update
+
+              // Test if hit
 	      if (internal_PREDICT_HIT [i])
 		{
-		  log_printf(TRACE,Return_Address_Stack,FUNCTION," * before");
-		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"   * reg_predict_top     : %d",reg_PREDICT_TOP    [context]);
-		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"   * reg_predict_bottom  : %d",reg_PREDICT_BOTTOM [context]);
-		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"   * reg_predict_nb_elt  : %d",reg_PREDICT_NB_ELT [context]);
-
+		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * before");
+		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_top     : %d",top_old);
+// 		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_bottom  : %d",bottom_old);
+		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_nb_elt  : %d",nb_elt_old);
+
+                  // Test if push
 		  if (push)
 		    {
+                      log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * push (call procedure)");
+
 		      // push : increase the top (circular)
 		      top_new = (top_old+1)%_param->_size_queue[context];
-		      
-		      reg_stack [context][top_new]._val     = true; // New addr
-		      reg_stack [context][top_new]._predict = true; // Is speculative (erase a old addr (or not))
-		    //reg_stack [context][top_new]._miss    = ;
+
+                      // Write new value in Queue
 		      reg_stack [context][top_new]._address = PORT_READ(in_PREDICT_ADDRESS_PUSH [i]);
 
-		      // the stack is full, erase the most old stack
-
 		      // Test if full
-		      if (reg_PREDICT_NB_ELT[context]==_param->_size_queue[context])
-			reg_PREDICT_BOTTOM [context] = (bottom_old+1)%_param->_size_queue[context];
-		      // A new data is write : the stack is not empty
-		      if (reg_PREDICT_NB_ELT[context]< _param->_size_queue[context])
-			reg_PREDICT_NB_ELT[context]++;
+                      //   -> is full, the push erase the oldest value in stack, also nb_elt is the same
+                      //   -> is not full, increase nb_elt
+// 		      if (nb_elt_old==_param->_size_queue[context])
+// 			bottom_new = (bottom_old+1)%_param->_size_queue[context];
+//                       else
+// 			nb_elt_new ++;
+		      if (nb_elt_old!=_param->_size_queue[context])
+			nb_elt_new ++;
 		    }
 		  else
 		    {
 		      // pop
-// 		      top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1);
-		      
-		    //reg_stack [context][top_new]._val     = ;
-		    //reg_stack [context][top_new]._predict = ;
-		    //reg_stack [context][top_new]._miss    = ;
-		    //reg_stack [context][top_new]._address = ; 
-
-		      // the stack is empty
-		      if (reg_PREDICT_NB_ELT[context]>0)
+                      log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * pop (return procedure)");
+
+		      // Test if the stack is empty
+		      if (nb_elt_old>0)
 			{
 			  top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1);
-			  reg_PREDICT_NB_ELT[context] --;
+			  nb_elt_new --;
 			}
+                      // no else : can't pop
 		    }
 		  
-		  reg_PREDICT_TOP [context] = top_new;
-
-		  log_printf(TRACE,Return_Address_Stack,FUNCTION," * after");
-		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"   * reg_predict_top     : %d",reg_PREDICT_TOP    [context]);
-		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"   * reg_predict_bottom  : %d",reg_PREDICT_BOTTOM [context]);
-		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"   * reg_predict_nb_elt  : %d",reg_PREDICT_NB_ELT [context]);
-		}
-	    }
+                  // Write new pointer
+		  reg_PREDICT_TOP    [context] = top_new;
+// 		  reg_PREDICT_BOTTOM [context] = bottom_new;
+		  reg_PREDICT_NB_ELT [context] = nb_elt_new;
+
+		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * after");
+		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_top     : %d",top_new);
+// 		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_bottom  : %d",bottom_new);
+		  log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_nb_elt  : %d",nb_elt_new);
+                }
+            }
 
 	// ===================================================================
@@ -122,81 +126,96 @@
 	  if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i])
 	    {
-	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"DECOD[%d] : Transaction",i);
+	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"  * DECOD [%d] : Transaction",i);
+
+              // Read information
 	      Tcontext_t context    = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
 	      Tcontrol_t push       = PORT_READ(in_DECOD_PUSH [i]);
+
+              // Read pointer
 	      Tptr_t     top_old    = reg_TOP    [context];
 	      Tptr_t     top_new    = top_old;
-	      Tptr_t     bottom_old = reg_BOTTOM [context];
-	      //Tcontrol_t hit        = internal_DECOD_HIT [i];
-	      Tcontrol_t miss       = PORT_READ(in_DECOD_MISS_PREDICTION [i]);
-
-	      log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context);
-
-	      log_printf(TRACE,Return_Address_Stack,FUNCTION," * before");
-	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"   * reg_top     : %d",reg_TOP    [context]);
-	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"   * reg_bottom  : %d",reg_BOTTOM [context]);
-	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"   * reg_nb_elt  : %d",reg_NB_ELT [context]);
-
-	      if (push)
-		{
-		  // push : increase the top (circular)
-		  top_new = (top_old+1)%_param->_size_queue[context];
-		  
-		  reg_stack [context][top_new]._val     = true;  // New address
-		  reg_stack [context][top_new]._predict = false; // No speculative
-		  reg_stack [context][top_new]._miss    = false;
-		  reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]);
-		  
-		  // Test if full : if true, then icrease the bottom (erase the most old stack)
-		  if (reg_NB_ELT[context]==_param->_size_queue[context])
-		    reg_BOTTOM [context] = (bottom_old+1)%_param->_size_queue[context];
-		  // A new data is write : the stack is not empty
-		  if (reg_NB_ELT[context]< _param->_size_queue[context])
-		    reg_NB_ELT[context]++;
-		}
-	      else
-		{
-		  // pop
-// 		  top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1);
-
-		  //reg_stack [context][top_new]._val     = ;
-		  //reg_stack [context][top_new]._predict = ;
-		  //reg_stack [context][top_new]._miss    = ;
-		  //reg_stack [context][top_new]._address = ; 
-		  
-		  // the stack is empty
-		  if (reg_NB_ELT[context]>0)
-		    {
-		      top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1);
-		      reg_NB_ELT[context] --;
-		    }
-		}
-	      
-	      reg_TOP [context] = top_new;
-	      
-	      log_printf(TRACE,Return_Address_Stack,FUNCTION," * after");
-	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"   * reg_top     : %d",reg_TOP    [context]);
-	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"   * reg_bottom  : %d",reg_BOTTOM [context]);
-	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"   * reg_nb_elt  : %d",reg_NB_ELT [context]);
-
+// 	      Tptr_t     bottom_old = reg_BOTTOM [context];
+// 	      Tptr_t     bottom_new = bottom_old;
+	      Tptr_t     nb_elt_old = reg_NB_ELT [context];
+	      Tptr_t     nb_elt_new = nb_elt_old;
+
+	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * context : %d",context);
+
+	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * before");
+              log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_top     : %d",top_old);
+//            log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_bottom  : %d",bottom_old);
+              log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_nb_elt  : %d",nb_elt_old);
+
+              // Test if push
+              if (push)
+                {
+                  log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * push (call procedure)");
+                  
+                  // push : increase the top (circular)
+                  top_new = (top_old+1)%_param->_size_queue[context];
+                  
+                  // Write new value in Queue
+                  reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]);
+                  
+                  // Test if full
+                  //   -> is full, the push erase the oldest value in stack, also nb_elt is the same
+                  //   -> is not full, increase nb_elt
+//                   if (nb_elt_old==_param->_size_queue[context])
+//                     bottom_new = (bottom_old+1)%_param->_size_queue[context];
+//                   else
+//                     nb_elt_new ++;
+                  if (nb_elt_old!=_param->_size_queue[context])
+                    nb_elt_new ++;
+                }
+              else
+                {
+                  // pop
+                  log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * pop (return procedure)");
+                  
+                  // Test if the stack is empty
+                  if (nb_elt_old>0)
+                    {
+                      top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1);
+                      nb_elt_new --;
+                    }
+                  // no else : can't pop
+                }
+              
+              // Write new pointer
+              reg_TOP    [context] = top_new;
+//            reg_BOTTOM [context] = bottom_new;
+              reg_NB_ELT [context] = nb_elt_new;
+              
+              log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * after");
+              log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_top     : %d",top_new);
+//            log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_bottom  : %d",bottom_new);
+              log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_nb_elt  : %d",nb_elt_new);
+              
 	      // have previous miss of ifetch ?
 	      // 2 miss : 
 	      //   1) miss predict : is very limited (local at context), can be update very quickly
 	      //   2) miss decod   : result is in commit stage ... 
-	      if (miss)
-		{
-		  reg_PREDICT_BOTTOM [context] = reg_BOTTOM [context];
-		  reg_PREDICT_TOP    [context] = reg_TOP    [context];
-		  reg_PREDICT_NB_ELT [context] = reg_NB_ELT [context];
+
+              // manage by Update_Fetch_Prediction_Table and Update_Prediction_Table
+              // Note : 
+              //   if decod miss : ifetch can have predict call and return branchement. Also, the head of decod can be false
+
+// 	      Tcontrol_t miss       = PORT_READ(in_DECOD_MISS_PREDICTION [i]);
+
+// 	      if (miss)
+// 		{
+// 		  reg_PREDICT_BOTTOM [context] = reg_BOTTOM [context];
+// 		  reg_PREDICT_TOP    [context] = reg_TOP    [context];
+// 		  reg_PREDICT_NB_ELT [context] = reg_NB_ELT [context];
 		  
-		  // Scan full assoc !!!
-		  for (uint32_t j=0; j<_param->_size_queue [context]; j++)
-		    // Test if this slot is tagged with "predict" : if true, tagged as miss
-		    if (reg_stack [context][j]._predict)
-		      {
-			reg_stack [context][j]._predict = false;
-			reg_stack [context][j]._miss    = true;
-		      }
-		}
+// 		  // Scan full assoc !!!
+// 		  for (uint32_t j=0; j<_param->_size_queue [context]; j++)
+// 		    // Test if this slot is tagged with "predict" : if true, tagged as miss
+// 		    if (reg_stack [context][j]._predict)
+// 		      {
+// 			reg_stack [context][j]._predict = false;
+// 			reg_stack [context][j]._miss    = true;
+// 		      }
+// 		}
 	    }
 
@@ -207,42 +226,160 @@
 	  if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i])
 	    {
-	      throw ERRORMORPHEO(FUNCTION,"Fonction à implémenter !!!!!!!!!!!!");
-	      
-
-// 	      Tcontrol_t miss   = PORT_READ(in_UPDATE_MISS_PREDICTION [i]);
-// 	      // 
-// 	      if (miss)
-// 		{
-// 		  Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;
-// 		  Tcontrol_t ifetch  = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]);
-// 		  Tcontrol_t push    = PORT_READ(in_UPDATE_PUSH             [i]);
-// 		  Tcontrol_t flush   = PORT_READ(in_UPDATE_FLUSH            [i]);
-// 		  Tptr_t     index   = PORT_READ(in_UPDATE_INDEX            [i]);
-// 		  Taddress_t address = PORT_READ(in_UPDATE_ADDRESS          [i]);
-		  
-// 		  if (push)
-// 		    {
-// // 		      // push
-// // 		      top_new = (top_old+1)%_param->_size_queue[context];
-		      
-// // 		      reg_stack [context][index]._val     = true;
-// // 		      reg_stack [context][index]._predict = false;
-// // 		      reg_stack [context][index]._miss    = false;
-// // 		      reg_stack [context][index]._address = PORT_READ(in_UPDATE_ADDRESS [i]);
-
-// 		    }
-// 		  else
-// 		    {
-// // 		    //reg_stack [context][top_new]._val     = ;
-// // 		    //reg_stack [context][top_new]._predict = ;
-// // 		    //reg_stack [context][top_new]._miss    = ;
-// // 		    //reg_stack [context][top_new]._address = ; 
-// 		    }
-		  
-// // // 		  // Mouais bof .......
-// // // 		  reg_PREDICT_TOP [context] = index;
-// 		}
+	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"  * UPDATE [%d] : Transaction",i);
+
+              Tcontext_t context_id        = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;
+              Tcontrol_t flush             = PORT_READ(in_UPDATE_FLUSH             [i]);
+
+	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * context_id        : %d",context_id);
+	      log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * flush             : %d",flush     );
+              
+              // An miss prediction on call/return = Return Address Stack is corrupted.
+              if (flush)
+                {
+                  // All pointer is set at 0
+                  reg_TOP    [context_id] = 0;
+//                reg_BOTTOM [context_id] = 0;
+                  reg_NB_ELT [context_id] = 0;
+                  
+                  reg_PREDICT_TOP    [context_id] = 0;
+//                reg_PREDICT_BOTTOM [context_id] = 0;
+                  reg_PREDICT_NB_ELT [context_id] = 0;
+                }
+              else
+                {
+                  // if miss_prediction -> restore queue
+                  // else, the prediction is correct
+                  Tcontrol_t miss_prediction   = PORT_READ(in_UPDATE_MISS_PREDICTION   [i]);
+
+                  log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * miss_prediction   : %d",miss_prediction);
+
+#ifdef DEBUG_TEST
+                  Tptr_t     index             = PORT_READ(in_UPDATE_INDEX             [i]);
+                  Tcontrol_t prediction_ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]);
+                  log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * index             : %d",index);
+                  log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * prediction_ifetch : %d",prediction_ifetch);
+
+//                   if (prediction_ifetch)
+//                     {
+//                       if (index != reg_PREDICT_TOP [context_id])
+//                         throw ERRORMORPHEO(FUNCTION,_("Index is different of predict_top"));
+//                     }
+//                   else
+//                     {
+//                       if (index != reg_TOP [context_id])
+//                         throw ERRORMORPHEO(FUNCTION,_("Index is different of top"));
+//                     }
+                  
+#endif
+                  if (miss_prediction)
+                    {
+                      Tcontrol_t push              = PORT_READ(in_UPDATE_PUSH              [i]);
+                      log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * push              : %d",push);
+#ifndef DEBUG_TEST
+                      Tptr_t     index             = PORT_READ(in_UPDATE_INDEX             [i]);
+                      Tcontrol_t prediction_ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]);
+                      log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * index             : %d",index);
+                      log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * prediction_ifetch : %d",prediction_ifetch);
+#endif
+
+
+                      Tptr_t     top_old    = (prediction_ifetch)?reg_PREDICT_TOP    [context_id]:reg_TOP    [context_id];
+                      Tptr_t     top_new    = top_old;
+
+//                    Tptr_t     bottom_old = (prediction_ifetch)?reg_PREDICT_BOTTOM [context_id]:reg_BOTTOM [context_id];
+//                    Tptr_t     bottom_new = bottom_old;
+
+                      Tptr_t     nb_elt_old = (prediction_ifetch)?reg_PREDICT_NB_ELT [context_id]:reg_NB_ELT [context_id];
+                      Tptr_t     nb_elt_new = nb_elt_old;
+                      
+                      log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * before");
+                      if (prediction_ifetch)
+                        {
+                          log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_top     : %d",top_old);
+//                        log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_bottom  : %d",bottom_old);
+                          log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_nb_elt  : %d",nb_elt_old);
+                        }
+                      else
+                        {
+                          log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_top     : %d",top_old);
+//                        log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_bottom  : %d",bottom_old);
+                          log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_nb_elt  : %d",nb_elt_old);
+                        }
+
+                      // if previous is push, pop the value
+                      // else is previous is pop, push the poped value
+                      if (push)
+                        {
+                          // previous is push, now must be pop
+
+                          // Test if the stack is empty
+                          if (nb_elt_old>0) // ??
+                            {
+                              top_new = (top_old==0)?(_param->_size_queue[context_id]-1):(top_old-1);
+                              nb_elt_new --;
+                            }
+                        }
+                      else
+                        {
+                          // previous is pop, now must be push
+                          Taddress_t address           = PORT_READ(in_UPDATE_ADDRESS           [i]);
+
+                          // push : increase the top (circular)
+//                        if (nb_elt_old==_param->_size_queue[context_id])
+//                          bottom_new = (bottom_old+1)%_param->_size_queue[context_id];
+//                        else
+//                          nb_elt_new ++;
+
+                          if (nb_elt_old!=_param->_size_queue[context_id])
+                            nb_elt_new ++;
+
+                          top_new = index;
+                          
+                          reg_stack [context_id][index]._address = address;
+                        }
+
+                      log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * after");
+
+                      if (prediction_ifetch)
+                        {
+                          log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_top     : %d",top_new);
+//                        log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_bottom  : %d",bottom_new);
+                          log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_predict_nb_elt  : %d",nb_elt_new);
+
+                          reg_PREDICT_TOP    [context_id] = top_new   ;
+//                        reg_PREDICT_BOTTOM [context_id] = bottom_new;
+                          reg_PREDICT_NB_ELT [context_id] = nb_elt_new;
+                        }
+                      else
+                        {
+                          log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_top     : %d",top_new);
+//                        log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_bottom  : %d",bottom_new);
+                          log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_nb_elt  : %d",nb_elt_new);
+
+                          reg_TOP            [context_id] = top_new   ;
+//                        reg_BOTTOM         [context_id] = bottom_new;
+                          reg_NB_ELT         [context_id] = nb_elt_new;
+                        }
+                    }
+                }
 	    }
       }
+
+#if defined(DEBUG_Return_Address_Stack) and DEBUG>=DEBUG_TRACE
+    log_printf(TRACE,Return_Address_Stack,FUNCTION,"  * Dump RAS");
+    for (uint32_t i=0; i<_param->_nb_context; ++i)
+      {
+        log_printf(TRACE,Return_Address_Stack,FUNCTION,"    * Return Address Stack [%d]",i);
+        log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_TOP            : %d",reg_TOP            [i]);
+//      log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_BOTTOM         : %d",reg_BOTTOM         [i]);
+        log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_NB_ELT         : %d",reg_NB_ELT         [i]);
+        log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_PREDICT_TOP    : %d",reg_PREDICT_TOP    [i]);
+//      log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_PREDICT_BOTTOM : %d",reg_PREDICT_BOTTOM [i]);
+        log_printf(TRACE,Return_Address_Stack,FUNCTION,"      * reg_PREDICT_NB_ELT : %d",reg_PREDICT_NB_ELT [i]);
+
+        for (uint32_t j=0; j<_param->_size_queue[i]; ++j)
+          log_printf(TRACE,Return_Address_Stack,FUNCTION,"      [%d] %.8x (%.8x)",j,reg_stack [i][j]._address,reg_stack [i][j]._address<<2);
+      }
+#endif
 
 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)
@@ -250,5 +387,5 @@
 #endif
 
-    log_printf(FUNC,Return_Address_Stack,FUNCTION,"End");
+    log_end(Return_Address_Stack,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 100)
@@ -220,4 +220,6 @@
   private   : Tcounter_t                   ** reg_NB_INST_COMMIT_ALL               ;//[nb_front_end][nb_context]
   private   : Tcounter_t                   ** reg_NB_INST_COMMIT_MEM               ;//[nb_front_end][nb_context]
+
+  private   : Tevent_state_t               ** reg_EVENT_STATE                      ;//[nb_front_end][nb_context]
 										   
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	   
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h	(revision 100)
@@ -27,19 +27,21 @@
   typedef enum
     {
-      ROB_EMPTY                     , // 
-      ROB_BRANCH_WAIT_END           , // 
-      ROB_BRANCH_COMPLETE           , // 
-      ROB_STORE_WAIT_HEAD_OK        , // 
-//    ROB_STORE_WAIT_HEAD_KO        , // 
-      ROB_STORE_HEAD_OK             , // 
-      ROB_STORE_HEAD_KO             , // 
-      ROB_OTHER_WAIT_END            , // 
-      ROB_MISS_WAIT_END             , // 
-      ROB_END_OK_SPECULATIVE        , // 
-      ROB_END_OK                    , // 
-      ROB_END_KO_SPECULATIVE        , // 
-      ROB_END_KO                    , // 
-      ROB_END_MISS                  , // 
-      ROB_END_EXCEPTION_WAIT_HEAD   , // 
+      ROB_EMPTY                      , // 
+      ROB_BRANCH_WAIT_END            , // 
+      ROB_BRANCH_COMPLETE            , // 
+      ROB_STORE_WAIT_HEAD_OK         , // 
+//    ROB_STORE_WAIT_HEAD_KO         , // 
+      ROB_STORE_HEAD_OK              , // 
+      ROB_STORE_HEAD_KO              , // 
+      ROB_OTHER_WAIT_END             , // 
+      ROB_MISS_WAIT_END              , // 
+      ROB_END_OK_SPECULATIVE         , // 
+      ROB_END_OK                     , // 
+      ROB_END_KO_SPECULATIVE         , // 
+      ROB_END_KO                     , // 
+      ROB_END_BRANCH_MISS_SPECULATIVE, // 
+      ROB_END_BRANCH_MISS            , // 
+      ROB_END_MISS                   , // 
+      ROB_END_EXCEPTION_WAIT_HEAD    , // 
       ROB_END_EXCEPTION               // 
     } rob_state_t;
@@ -79,5 +81,4 @@
   public  : Tspecial_address_t num_reg_re_phy_new      ;
 
-  public  : Tevent_state_t     event_state             ;
   public  : Texception_t       exception               ;
   public  : Texception_t       exception_use           ;
@@ -161,19 +162,23 @@
     switch (x)
       {
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EMPTY                     : return "empty"                     ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_WAIT_END           : return "branch_wait_end"           ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_COMPLETE           : return "branch_complete"           ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_OK        : return "store_wait_head_ok"        ; break;
-//    case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_KO        : return "store_wait_head_ko"        ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_OK             : return "store_head_ok"             ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO             : return "store_head_ko"             ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END            : return "other_wait_end"            ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_MISS_WAIT_END             : return "miss_wait_end"             ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK_SPECULATIVE        : return "end_ok_speculative"        ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK                    : return "end_ok"                    ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO_SPECULATIVE        : return "end_ko_speculative"        ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO                    : return "end_ko"                    ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_WAIT_HEAD   : return "end_exception_wait_head"   ; break;
-      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION             : return "end_exception"             ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EMPTY                      : return "ROB_EMPTY"                       ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_WAIT_END            : return "ROB_BRANCH_WAIT_END"             ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_COMPLETE            : return "ROB_BRANCH_COMPLETE"             ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_OK         : return "ROB_STORE_WAIT_HEAD_OK"          ; break;
+//    case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_KO         : return "ROB_STORE_WAIT_HEAD_KO"          ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_OK              : return "ROB_STORE_HEAD_OK"               ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO              : return "ROB_STORE_HEAD_KO"               ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END             : return "ROB_OTHER_WAIT_END"              ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_MISS_WAIT_END              : return "ROB_MISS_WAIT_END"               ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK_SPECULATIVE         : return "ROB_END_OK_SPECULATIVE"          ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK                     : return "ROB_END_OK"                      ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO_SPECULATIVE         : return "ROB_END_KO_SPECULATIVE"          ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO                     : return "ROB_END_KO"                      ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_BRANCH_MISS_SPECULATIVE: return "ROB_END_BRANCH_MISS_SPECULATIVE" ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_BRANCH_MISS            : return "ROB_END_BRANCH_MISS"             ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_MISS                   : return "ROB_END_MISS"                    ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_WAIT_HEAD    : return "ROB_END_EXCEPTION_WAIT_HEAD"     ; break;
+      case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION              : return "ROB_END_EXCEPTION"               ; break;
+
       default    : return ""      ; break;
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 100)
@@ -272,16 +272,12 @@
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-    _rob = new std::list<entry_t*> [_param->_nb_bank];
+    ALLOC1(_rob                   ,std::list<entry_t*>,_param->_nb_bank);
     
-    reg_BANK_PTR           = new uint32_t     [_param->_nb_bank];
-
-    reg_NB_INST_COMMIT_ALL = new Tcounter_t * [_param->_nb_front_end];
-    reg_NB_INST_COMMIT_MEM = new Tcounter_t * [_param->_nb_front_end];
+    ALLOC1(reg_BANK_PTR           ,uint32_t      ,_param->_nb_bank);
+
+    ALLOC2(reg_NB_INST_COMMIT_ALL ,Tcounter_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
+    ALLOC2(reg_NB_INST_COMMIT_MEM ,Tcounter_t    ,_param->_nb_front_end,_param->_nb_context [it1]);
     
-    for (uint32_t i=0; i<_param->_nb_front_end; i++)
-      {
-	reg_NB_INST_COMMIT_ALL [i] = new Tcounter_t [_param->_nb_context [i]];
-	reg_NB_INST_COMMIT_MEM [i] = new Tcounter_t [_param->_nb_context [i]];
-      }
+    ALLOC2(reg_EVENT_STATE        ,Tevent_state_t,_param->_nb_front_end,_param->_nb_context [it1]);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 100)
@@ -178,15 +178,9 @@
         
         // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-        for (uint32_t i=0; i<_param->_nb_front_end; i++)
-          {
-            delete [] reg_NB_INST_COMMIT_ALL [i];
-            delete [] reg_NB_INST_COMMIT_MEM [i];
-          }
-        delete [] reg_NB_INST_COMMIT_ALL;
-        delete [] reg_NB_INST_COMMIT_MEM;
-        
-        delete [] reg_BANK_PTR;
-        
-        delete [] _rob;
+        DELETE1(_rob                   ,_param->_nb_bank);
+        DELETE1(reg_BANK_PTR           ,_param->_nb_bank);
+        DELETE2(reg_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context [it1]);
+        DELETE2(reg_EVENT_STATE        ,_param->_nb_front_end,_param->_nb_context [it1]);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp	(revision 100)
@@ -30,4 +30,5 @@
     uint32_t           bank_nb_access    [_param->_nb_bank];
     Tcontrol_t         commit_ack        [_param->_nb_inst_commit];
+
     // Initialisation
     for (uint32_t i=0; i<_param->_nb_bank; i++)
@@ -38,14 +39,15 @@
       }
 
-    // commit interface
+    // commit interface -> scan all entry (Out of Order)
     for (uint32_t i=0; i<_param->_nb_inst_commit; i++)
       {
         commit_ack        [i] = false;
 
-	// Test if have instruction
+	// Test if have valid instruction
 	if (PORT_READ(in_COMMIT_VAL [i]))
 	  {
-	    Tpacket_t packet          = (_param->_have_port_rob_ptr  )?PORT_READ(in_COMMIT_PACKET_ID [i]):0;
-	    uint32_t  num_bank        = packet >> _param->_shift_num_bank;
+            // packet_id number can 
+	    Tpacket_t packet_id       = (_param->_have_port_rob_ptr  )?PORT_READ(in_COMMIT_PACKET_ID [i]):0;
+	    uint32_t  num_bank        = packet_id >> _param->_shift_num_bank;
 	    uint32_t  num_bank_access = bank_nb_access [num_bank];
             
@@ -60,5 +62,5 @@
 		internal_BANK_COMMIT_NUM_INST [num_bank][num_bank_access] = i;
                 
-                Tpacket_t packet_id = packet & _param->_mask_size_bank;
+                Tpacket_t num_packet = packet_id & _param->_mask_size_bank;
                 
                 // find the good entry !!!
@@ -67,5 +69,5 @@
                      it!=_rob[num_bank].end();
                      it++)
-                  if ((*it)->ptr == packet_id)
+                  if ((*it)->ptr == num_packet)
                     {
                       entry = (*it);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp	(revision 100)
@@ -54,5 +54,6 @@
     std::list<generic::priority::select_t> * select_insert = _priority_insert ->select(); // same select for all insert
     std::list<generic::priority::select_t>::iterator it=select_insert ->begin();
- 
+
+    // Scan all bank ...
     for (uint32_t i=0; i<_param->_nb_bank; i++)
       {
@@ -64,4 +65,5 @@
 // 	log_printf(TRACE,Commit_unit,FUNCTION,"    * full : %d", bank_full [num_bank]);
 
+        // Scan all insert interface to find a valid transaction
 	while (it!=select_insert ->end())
 	  {
@@ -87,5 +89,5 @@
 		if (not bank_full [num_bank])
 		  {
-		    // find
+		    // find !!!
 		    insert_ack       [num_rename_unit][num_inst_insert] = true;
 
@@ -112,4 +114,5 @@
       }
     
+    // Write output
     for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
       for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp	(revision 100)
@@ -48,9 +48,13 @@
 	  retire_val [i][j] = false;
       }
-
     for (uint32_t i=0; i<_param->_nb_front_end; ++i)
       for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
-	spr_write_val [i][j] = 0;
-
+        {
+          spr_write_val [i][j] = 0;
+          spr_write_sr_f_val  [i][j] = 0;
+          spr_write_sr_cy_val [i][j] = 0;
+          spr_write_sr_ov_val [i][j] = 0;
+
+        }
     // Scan Top of each bank
     for (uint32_t i=0; i<_param->_nb_bank; i++)
@@ -64,5 +68,8 @@
 	    uint32_t   x     = entry->rename_unit_id;
 	    uint32_t   y     = num_inst_retire [x];
-	    
+	
+            // test if :
+            //  * can retire (all previous instruction is retired)
+            //  * all structure is ok (not busy)
 	    if (can_retire [x] and // in-order
 		(y < _param->_nb_inst_retire [x]) and
@@ -71,7 +78,8 @@
 		rob_state_t state = entry->state;
 		
-		if ((state == ROB_END_OK  ) or 
-		    (state == ROB_END_KO  ) or 
-		    (state == ROB_END_MISS)//  or 
+		if ((state == ROB_END_OK         ) or 
+		    (state == ROB_END_KO         ) or 
+		    (state == ROB_END_BRANCH_MISS) or 
+		    (state == ROB_END_MISS       )//  or 
 // 		    (state == ROB_END_EXCEPTION)
 		    )
@@ -85,5 +93,7 @@
 		    bool spr_write_ack = true;
 
+                    // Write in SR the good flag
 		    if ((state == ROB_END_OK  ) and write_re)
+                      // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE
 		      {
 			spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]);
@@ -138,5 +148,5 @@
 		    PORT_WRITE(out_RETIRE_CONTEXT_ID            [x][y], context_id                  );
 // 		    PORT_WRITE(out_RETIRE_RENAME_UNIT_ID        [x][y], entry->rename_unit_id       );
-		    PORT_WRITE(out_RETIRE_EVENT_STATE           [x][y], entry->event_state          );
+		    PORT_WRITE(out_RETIRE_EVENT_STATE           [x][y], reg_EVENT_STATE[front_end_id][context_id]);
 		    PORT_WRITE(out_RETIRE_USE_STORE_QUEUE       [x][y], entry->use_store_queue      );
 		    PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE        [x][y], entry->use_load_queue       );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 100)
@@ -28,4 +28,7 @@
     // ===================================================================
     {
+      // Store instruction comming Out Of Order in Load Store Unit. 
+      // Must be executed in no speculative mode. Also, send a signal when an Store is in head of ROB
+
       Tcontrol_t val = false;
 
@@ -35,4 +38,5 @@
 	  rob_state_t  state = entry->state;
 
+          // Test state
 	  val   = ((state == ROB_STORE_HEAD_OK) or
 		   (state == ROB_STORE_HEAD_KO));
@@ -40,4 +44,5 @@
 	  if (val)
 	    {
+              // Reexecute store
 	      if (_param->_have_port_context_id)
   	      PORT_WRITE(out_REEXECUTE_CONTEXT_ID            [0], entry->context_id           );
@@ -62,6 +67,8 @@
     // ===================================================================
     {
+      // Branchement must be send at the prediction unit
       uint32_t nb_scan_bank = 0;
 
+      // for each port, find a valid branchement.
       for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
 	{
@@ -72,4 +79,5 @@
 	      nb_scan_bank ++;
 
+              // translate bank number
 	      uint32_t num_bank = (reg_NUM_BANK_HEAD+j)%_param->_nb_bank;
 	      
@@ -124,16 +132,4 @@
 	}
     }
-
-//   public    : SC_OUT(Tcontrol_t         )   * out_UPDATE_VAL                        ;
-//   public    : SC_IN (Tcontrol_t         )   *  in_UPDATE_ACK                        ;
-//   public    : SC_OUT(Tcontext_t         )   * out_UPDATE_CONTEXT_ID                 ;
-//   public    : SC_OUT(Tcontext_t         )   * out_UPDATE_FRONT_END_ID               ;
-//   public    : SC_OUT(Tdepth_t           )   * out_UPDATE_DEPTH                      ;
-//   public    : SC_OUT(Tevent_type_t      )   * out_UPDATE_TYPE                       ;
-//   public    : SC_OUT(Tcontrol_t         )   * out_UPDATE_IS_DELAY_SLOT              ;
-//   public    : SC_OUT(Taddress_t         )   * out_UPDATE_ADDRESS                    ;
-//   public    : SC_OUT(Taddress_t         )   * out_UPDATE_ADDRESS_EPCR               ;
-//   public    : SC_OUT(Tcontrol_t         )   * out_UPDATE_ADDRESS_EEAR_VAL           ;
-//   public    : SC_OUT(Taddress_t         )   * out_UPDATE_ADDRESS_EEAR               ;
  
     // ===================================================================
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp	(revision 100)
@@ -57,4 +57,7 @@
       _stat->create_expr_average_by_cycle("average_inst_retire_ko", sum_nb_inst_retire_ko, "", _("Average instruction retire ko (event, miss) by cycle"));
       _stat->create_expr_average_by_cycle("average_inst_retire"   , "+ "+sum_nb_inst_retire_ok+" "+sum_nb_inst_retire_ko, "", _("Average instruction retire by cycle"));
+
+      _stat->create_expr                 ("IPC", "average_inst_retire_ok", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle");
+      _stat->create_expr                 ("CPI", "/ 1 IPC"               , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction");
     }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 100)
@@ -26,4 +26,5 @@
     if (PORT_READ(in_NRESET) == 0)
       {
+        // Clear all bank 
         for (uint32_t i=0; i<_param->_nb_bank; i++)
 	  {
@@ -32,7 +33,9 @@
 	  }
 
+        // Reset pointer
 	reg_NUM_BANK_HEAD = 0;
 	reg_NUM_BANK_TAIL = 0;
 
+        // Reset counter
 	for (uint32_t i=0; i<_param->_nb_front_end; i++)
 	  for (uint32_t j=0; j<_param->_nb_context [i]; j++)
@@ -40,12 +43,29 @@
 	      reg_NB_INST_COMMIT_ALL [i][j] = 0;
 	      reg_NB_INST_COMMIT_MEM [i][j] = 0;
+
+              reg_EVENT_STATE        [i][j] = EVENT_STATE_NO_EVENT;
 	    }
 
+        // Reset priority algorithm
 	_priority_insert->reset();
       }
     else
       {
-	// next priority
+	// Compute next priority
 	_priority_insert->transition();
+
+	// ===================================================================
+	// =====[ GARBAGE COLLECTOR ]=========================================
+	// ===================================================================
+	for (uint32_t i=0; i<_param->_nb_front_end; i++)
+	  for (uint32_t j=0; j<_param->_nb_context [i]; j++)
+            switch (reg_EVENT_STATE [i][j])
+              {
+              case EVENT_STATE_EVENT    : reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; break;
+              case EVENT_STATE_END      : reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; break;
+//            case EVENT_STATE_NO_EVENT : 
+//            case EVENT_STATE_WAITEND  : 
+              default : break;
+              }
 
 	// ===================================================================
@@ -55,4 +75,5 @@
 	  if (internal_BANK_INSERT_VAL [i])
 	    {
+              // get rename unit source and instruction.
 	      uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i];
 	      uint32_t y = internal_BANK_INSERT_NUM_INST        [i];
@@ -67,8 +88,11 @@
 #endif
 
+                  // get information
 		  Tcontext_t   front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0;
 		  Tcontext_t   context_id   = (_param->_have_port_context_id  )?PORT_READ(in_INSERT_CONTEXT_ID   [x][y]):0;
 		  Ttype_t      type         = PORT_READ(in_INSERT_TYPE         [x][y]);
                   Toperation_t operation    = PORT_READ(in_INSERT_OPERATION    [x][y]);
+                  bool         is_store     = is_operation_memory_store(operation);
+
 		  Texception_t exception    = PORT_READ(in_INSERT_EXCEPTION    [x][y]);
 
@@ -78,5 +102,6 @@
 		  log_printf(TRACE,Commit_unit,FUNCTION,"    * operation      : %d",operation );
 		  log_printf(TRACE,Commit_unit,FUNCTION,"    * exception      : %d",exception );
-
+                  
+                  // Create new entry.
 		  entry_t * entry = new entry_t;
 
@@ -92,6 +117,6 @@
 		  entry->exception               = exception;
 		  entry->exception_use           = PORT_READ(in_INSERT_EXCEPTION_USE         [x][y]);
-		  entry->use_store_queue         = (type == TYPE_MEMORY) and (    is_operation_memory_store(operation));
-		  entry->use_load_queue          = (type == TYPE_MEMORY) and (not is_operation_memory_store(operation));
+		  entry->use_store_queue         = (type == TYPE_MEMORY) and (    is_store);
+		  entry->use_load_queue          = (type == TYPE_MEMORY) and (not is_store);
 		  entry->store_queue_ptr_write   = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]);
 		  entry->load_queue_ptr_write    = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0;
@@ -114,4 +139,12 @@
 		  entry->num_reg_re_phy_new      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW    [x][y]);
 
+                  // Test if exception :
+                  //  * yes : no execute instruction, wait ROB Head
+                  //  * no  : test type
+                  //            * BRANCH : l.j   -> branch is ended
+                  //                       other -> wait the execution end of branchment
+                  //            * MEMORY : store -> wait store is at head of ROB
+                  //                       other -> wait end of instruction
+                  //            * OTHER
 		  if (exception == EXCEPTION_NONE)
 		    {
@@ -124,5 +157,5 @@
 			{
 			case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;}
-			case TYPE_MEMORY : {entry->state=ROB_STORE_WAIT_HEAD_OK; break;}
+			case TYPE_MEMORY : {entry->state=(is_store  ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;}
 			default          : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
 			}
@@ -130,4 +163,6 @@
 		  else
 		    {
+                      // Have an exception : wait head of ROB
+
                       // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
 
@@ -135,7 +170,8 @@
 		    }
 
+                  // Push in rob
 		  _rob[i].push_back(entry);
 
-		  // Update nb_inst
+		  // Update counter and pointer
 		  reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++;
 		  if (type == TYPE_MEMORY)
@@ -160,4 +196,6 @@
 	    if (internal_BANK_COMMIT_VAL [i][j])
 	      {
+                // An instruction is executed. Change state of this instruction
+
 		uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j];
 
@@ -171,93 +209,73 @@
 #endif
 
-// 		    Tpacket_t packet_id = (_param->_have_port_rob_ptr  )?(PORT_READ(in_COMMIT_PACKET_ID [x])&_param->_mask_size_bank):0;
-		    
 		    log_printf(TRACE,Commit_unit,FUNCTION,"    * num_bank   : %d",i);
-// 		    log_printf(TRACE,Commit_unit,FUNCTION,"    * packet_id  : %d",(_param->_have_port_rob_ptr  )?(PORT_READ(in_COMMIT_PACKET_ID [x])):0);
-// 		    log_printf(TRACE,Commit_unit,FUNCTION,"    * num_entry  : %d",packet_id);
-		    
-		    // test pandex with ptr_write.
-// 		    Tpacket_t index     = (packet_id<reg_BANK_PTR [i])?(reg_BANK_PTR [i]-packet_id):(_param->_size_bank+reg_BANK_PTR [i]-packet_id);
 
 		    // find the good entry !!!
-		    entry_t *       entry       = internal_BANK_COMMIT_ENTRY [i][j];
-
-		  //Toperation_t    operation   = PORT_READ(in_COMMIT_OPERATION   [x]);
-		  //Ttype_t         type        = PORT_READ(in_COMMIT_TYPE        [x]);
-		    Texception_t    exception   = PORT_READ(in_COMMIT_EXCEPTION   [x]);
-
-		    rob_state_t state        = entry->state;
-		    Tcontext_t  front_end_id = entry->front_end_id;
-		    Tcontext_t  context_id   = entry->context_id;
-
-		    // change state
+		    entry_t *       entry        = internal_BANK_COMMIT_ENTRY [i][j];
+                                                 
+		  //Toperation_t    operation    = PORT_READ(in_COMMIT_OPERATION   [x]);
+		  //Ttype_t         type         = PORT_READ(in_COMMIT_TYPE        [x]);
+		    Texception_t    exception    = PORT_READ(in_COMMIT_EXCEPTION   [x]);
+
+		    rob_state_t     state        = entry->state;
+		    Tcontext_t      front_end_id = entry->front_end_id;
+		    Tcontext_t      context_id   = entry->context_id;
+
+		    // change state : test exception_use
 		    //  * test if exception : exception and mask
 		    
-		    bool have_exception = false;
-		    
+		    bool have_exception        = false;
+                    bool have_miss_speculation = false;
+
 		    if (exception != EXCEPTION_NONE)
-		      switch (entry->exception_use)
-			{
-			case  EXCEPTION_USE_RANGE                    : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;}
-			case  EXCEPTION_USE_MEMORY_WITH_ALIGNMENT    : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
-											  (exception == EXCEPTION_DATA_TLB ) or
-											  (exception == EXCEPTION_DATA_PAGE) or
-											  (exception == EXCEPTION_ALIGNMENT)); break;};
-			case  EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
-											  (exception == EXCEPTION_DATA_TLB ) or
-											  (exception == EXCEPTION_DATA_PAGE)); break;};
-			case  EXCEPTION_USE_CUSTOM_0                 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; 
-			case  EXCEPTION_USE_CUSTOM_1                 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; 
-			case  EXCEPTION_USE_CUSTOM_2                 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; 
-			case  EXCEPTION_USE_CUSTOM_3                 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; 
-			case  EXCEPTION_USE_CUSTOM_4                 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; 
-			case  EXCEPTION_USE_CUSTOM_5                 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; 
-			case  EXCEPTION_USE_CUSTOM_6                 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; 
-			case  EXCEPTION_USE_TRAP                     : {have_exception = false; break;};
-			case  EXCEPTION_USE_NONE                     : {have_exception = false; break;}; 
-			case  EXCEPTION_USE_ILLEGAL_INSTRUCTION      : {have_exception = false; break;};
-			case  EXCEPTION_USE_SYSCALL                  : {have_exception = false; break;};
-			default :
-			  {
-			    throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n"));
-			    break;
-			  }
-			}
-
-		    if (not have_exception)
-		      {
-			switch (state)
-			  {
-			  case ROB_OTHER_WAIT_END  : {state = ROB_END_OK_SPECULATIVE; break;}
-			  case ROB_BRANCH_WAIT_END : {state = ROB_BRANCH_COMPLETE   ; break;}
-			  case ROB_MISS_WAIT_END   : {state = ROB_END_KO_SPECULATIVE; break;}
-			  default :
-			    {
-			      throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str()));
-			      break;
-			    }
-			  }
-			// can have an exception, but this instruction is not sensible a this exception
-			exception = EXCEPTION_NONE; 
-		      }
-		    else
-		      {
-#ifdef DEBUG_TEST
-			if ((entry->type == TYPE_MEMORY) and (exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
-			  throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception.\n"));
-#endif 
-
-			switch (state)
-			  {
-			  case ROB_OTHER_WAIT_END  : 
-			  case ROB_BRANCH_WAIT_END : {state = ROB_END_EXCEPTION_WAIT_HEAD; break;}
-			  case ROB_MISS_WAIT_END   : {state = ROB_END_KO_SPECULATIVE     ; break;}
-			  default :
-			    {
-			      throw ERRORMORPHEO(FUNCTION,_("Commit : invalid state value.\n"));
-			      break;
-			    }
-			  }
-		      }
+                      {
+                        // Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store)
+                        have_miss_speculation  = (exception == EXCEPTION_MEMORY_MISS_SPECULATION);
+
+                        switch (entry->exception_use)
+                          {
+                            // Have overflow exception if bit overflow enable is set.
+                          case  EXCEPTION_USE_RANGE                    : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;}
+                          case  EXCEPTION_USE_MEMORY_WITH_ALIGNMENT    : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
+                                                                                            (exception == EXCEPTION_DATA_TLB ) or
+                                                                                            (exception == EXCEPTION_DATA_PAGE) or
+                                                                                            (exception == EXCEPTION_ALIGNMENT)); break;};
+                          case  EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
+                                                                                            (exception == EXCEPTION_DATA_TLB ) or
+                                                                                            (exception == EXCEPTION_DATA_PAGE)); break;};
+                          case  EXCEPTION_USE_CUSTOM_0                 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; 
+                          case  EXCEPTION_USE_CUSTOM_1                 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; 
+                          case  EXCEPTION_USE_CUSTOM_2                 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; 
+                          case  EXCEPTION_USE_CUSTOM_3                 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; 
+                          case  EXCEPTION_USE_CUSTOM_4                 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; 
+                          case  EXCEPTION_USE_CUSTOM_5                 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; 
+                          case  EXCEPTION_USE_CUSTOM_6                 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; 
+                            // Case already manage (decod stage -> in insert in ROB)
+                          case  EXCEPTION_USE_TRAP                     : {have_exception = false; exception = EXCEPTION_NONE; break;};
+                          case  EXCEPTION_USE_NONE                     : {have_exception = false; exception = EXCEPTION_NONE; break;}; 
+                          case  EXCEPTION_USE_ILLEGAL_INSTRUCTION      : {have_exception = false; exception = EXCEPTION_NONE; break;};
+                          case  EXCEPTION_USE_SYSCALL                  : {have_exception = false; exception = EXCEPTION_NONE; break;};
+                          default :
+                            {
+                              throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n"));
+                              break;
+                            }
+                          }
+                      }
+                   
+                    switch (state)
+                      {
+                        // Branch ...
+                      case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;}
+                        // Store KO
+                      case ROB_MISS_WAIT_END   : {state = ROB_END_KO_SPECULATIVE; break;}
+                        // Store OK, Load and other instruction
+                      case ROB_OTHER_WAIT_END  : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_MISS:ROB_END_OK_SPECULATIVE); break;}
+                      default :
+                        {
+                          throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str()));
+                          break;
+                        }
+                      }
 
 		    // update Re Order Buffer
@@ -287,9 +305,9 @@
 
 	      entry_t *  entry        =  _rob [i].front();
+              rob_state_t state = entry->state;
+              
 #ifdef STATISTICS
               if (usage_is_set(_usage,USE_STATISTICS))
                 {
-                  rob_state_t state = entry->state;
-                  
                   if (state == ROB_END_OK)
                     (*_stat_nb_inst_retire_ok [x]) ++;
@@ -302,4 +320,11 @@
 	      Tcontext_t context_id   = entry->context_id  ;
 	      Ttype_t    type         = entry->type        ;
+
+              if (state == ROB_END_BRANCH_MISS)
+                {
+                  reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT;
+
+                  // !!!!!!!!!!! Compute address
+                }
 	      
 	      // Update nb_inst
@@ -307,5 +332,8 @@
 	      if (type == TYPE_MEMORY)
 		reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
-	      
+
+              if (reg_NB_INST_COMMIT_ALL [front_end_id][context_id] == 0)
+                reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_END;
+
 	      reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank;
 	      
@@ -350,10 +378,21 @@
 #endif
 
-	      entry->state = ROB_END_OK_SPECULATIVE;
+              entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_OK_SPECULATIVE:ROB_END_BRANCH_MISS_SPECULATIVE;
+//               entry->state = ROB_END_OK_SPECULATIVE;
 	    }
 
 	// ===================================================================
+	// =====[ UPDATE ]====================================================
+	// ===================================================================
+        {
+          // Not yet implemented
+        }
+
+	// ===================================================================
 	// =====[ EVENT ]=====================================================
 	// ===================================================================
+        {
+          // Not yet implemented
+        }
 
 	// ===================================================================
@@ -400,24 +439,26 @@
 		  switch (state)
 		    {
-		    case ROB_BRANCH_WAIT_END           : {state = ROB_MISS_WAIT_END; break;}
-		    case ROB_BRANCH_COMPLETE           : {state = ROB_END_MISS     ; break;}
-		    case ROB_STORE_WAIT_HEAD_OK        : {state = ROB_STORE_HEAD_KO; break;}
-		  //case ROB_STORE_WAIT_HEAD_KO        : {state = ; break;}
-		    case ROB_OTHER_WAIT_END            : {state = ROB_MISS_WAIT_END; break;}
-		    case ROB_END_OK_SPECULATIVE        : {state = ROB_END_MISS     ; break;}
-		    case ROB_END_KO_SPECULATIVE        : {state = ROB_END_MISS     ; break;}
-		    case ROB_END_EXCEPTION_WAIT_HEAD   : {state = ROB_END_MISS     ; break;}
-		      
-		      // don't change
-		    case ROB_STORE_HEAD_KO             : {break;}
-		    case ROB_MISS_WAIT_END             : {break;}
-		    case ROB_END_MISS                  : {break;}
-		      
-		      // can't have miss speculation
-		    case ROB_STORE_HEAD_OK             :
-		    case ROB_END_OK                    :
-		    case ROB_END_KO                    :
-		    case ROB_END_EXCEPTION             :
-		    default                            : 
+		    case ROB_BRANCH_WAIT_END             : {state = ROB_MISS_WAIT_END; break;}
+		    case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS     ; break;}
+                    case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS     ; break;}
+		    case ROB_STORE_WAIT_HEAD_OK          : {state = ROB_STORE_HEAD_KO; break;}
+		  //case ROB_STORE_WAIT_HEAD_KO          : {state = ; break;}
+		    case ROB_OTHER_WAIT_END              : {state = ROB_MISS_WAIT_END; break;}
+		    case ROB_END_OK_SPECULATIVE          : {state = ROB_END_MISS     ; break;}
+		    case ROB_END_KO_SPECULATIVE          : {state = ROB_END_MISS     ; break;}
+		    case ROB_END_EXCEPTION_WAIT_HEAD     : {state = ROB_END_MISS     ; break;}
+		                                         
+		      // don't change                    
+		    case ROB_STORE_HEAD_KO               : {break;}
+		    case ROB_MISS_WAIT_END               : {break;}
+		    case ROB_END_MISS                    : {break;}
+		                                         
+		      // can't have miss speculation     
+		    case ROB_STORE_HEAD_OK               :
+		    case ROB_END_OK                      :
+		    case ROB_END_KO                      :
+                    case ROB_END_BRANCH_MISS             :
+		    case ROB_END_EXCEPTION               :
+		    default                              : 
 		      {
 			throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n"));
@@ -434,6 +475,7 @@
 		  switch (state)
 		    {
-		    case ROB_END_OK_SPECULATIVE        : {state = ROB_END_OK                 ; break;}
-		    case ROB_END_KO_SPECULATIVE        : {state = ROB_END_KO                 ; break;}
+		    case ROB_END_OK_SPECULATIVE          : {state = ROB_END_OK                 ; break;}
+		    case ROB_END_KO_SPECULATIVE          : {state = ROB_END_KO                 ; break;}
+		    case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS        ; break;}
 		    default : {break;}
 		  }
@@ -519,11 +561,10 @@
                        (*it)->num_reg_re_phy_new      );
             
-            log_printf(TRACE,Commit_unit,FUNCTION,"             %.2d %.2d %.1d %.1d %.8x %s",
+            log_printf(TRACE,Commit_unit,FUNCTION,"             %.2d %.2d %.1d %.1d %.8x",
                        (*it)->exception     ,
                        (*it)->exception_use ,
                        (*it)->flags         ,
                        (*it)->no_sequence   ,
-                       (*it)->data_commit   ,
-                       toString((*it)->event_state).c_str()
+                       (*it)->data_commit   
                        );
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp	(revision 100)
@@ -113,5 +113,6 @@
             sensitive << (*(in_RENAME_CONTEXT_ID     [i]));
             
-            sensitive << (*(in_RENAME_NUM_REG_RA_LOG [i]))
+            sensitive << (*(in_RENAME_VAL            [i])) // Not necessary
+                      << (*(in_RENAME_NUM_REG_RA_LOG [i]))
                       << (*(in_RENAME_NUM_REG_RB_LOG [i]))
                       << (*(in_RENAME_NUM_REG_RC_LOG [i]))
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp	(revision 100)
@@ -29,19 +29,36 @@
       if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access
       {
+        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"  * RENAME [%d]",i);
+
 	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
 	Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
 
-        Tgeneral_address_t num_reg_ra_log = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register;
-        Tgeneral_address_t num_reg_rb_log = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register;
-        Tspecial_address_t num_reg_rc_log = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register;
-        Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register;
-        Tspecial_address_t num_reg_re_log = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register;
+        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * front_end_id       : %d",front_end_id);
+        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * context_id         : %d",context_id);
 
-	PORT_WRITE(out_RENAME_NUM_REG_RA_PHY     [i], rat_gpr[front_end_id][context_id][num_reg_ra_log]);
-	PORT_WRITE(out_RENAME_NUM_REG_RB_PHY     [i], rat_gpr[front_end_id][context_id][num_reg_rb_log]);
-	PORT_WRITE(out_RENAME_NUM_REG_RC_PHY     [i], rat_spr[front_end_id][context_id][num_reg_rc_log]);
-	PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], rat_gpr[front_end_id][context_id][num_reg_rd_log]);
-	PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], rat_spr[front_end_id][context_id][num_reg_re_log]);
-        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"yo6");
+        Tgeneral_address_t num_reg_ra_log    = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register;
+        Tgeneral_address_t num_reg_rb_log    = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register;
+        Tspecial_address_t num_reg_rc_log    = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register;
+        Tgeneral_address_t num_reg_rd_log    = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register;
+        Tspecial_address_t num_reg_re_log    = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register;
+                                            
+        Tgeneral_address_t num_reg_ra_phy    = rat_gpr[front_end_id][context_id][num_reg_ra_log];
+        Tgeneral_address_t num_reg_rb_phy    = rat_gpr[front_end_id][context_id][num_reg_rb_log];
+        Tspecial_address_t num_reg_rc_phy    = rat_spr[front_end_id][context_id][num_reg_rc_log];
+        Tgeneral_address_t num_reg_rd_phy_old= rat_gpr[front_end_id][context_id][num_reg_rd_log];
+        Tspecial_address_t num_reg_re_phy_old= rat_spr[front_end_id][context_id][num_reg_re_log];
+
+        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_ra         : %d -> %d",num_reg_ra_log,num_reg_ra_phy    );
+        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rb         : %d -> %d",num_reg_rb_log,num_reg_rb_phy    );
+        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rc         : %d -> %d",num_reg_rc_log,num_reg_rc_phy    );
+        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_rd         : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old);
+        log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"    * num_reg_re         : %d -> %d",num_reg_re_log,num_reg_re_phy_old);
+        
+
+	PORT_WRITE(out_RENAME_NUM_REG_RA_PHY     [i], num_reg_ra_phy    );
+	PORT_WRITE(out_RENAME_NUM_REG_RB_PHY     [i], num_reg_rb_phy    );
+	PORT_WRITE(out_RENAME_NUM_REG_RC_PHY     [i], num_reg_rc_phy    );
+	PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old);
+	PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp	(revision 100)
@@ -37,7 +37,13 @@
 
 	      for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
-		rat_gpr [i][j][k] = gpr++;
+                {
+                  rat_gpr             [i][j][k] = gpr++;
+//                rat_gpr_update_table[i][j][k] = 0;
+                }
 	      for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
-		rat_spr [i][j][k] = spr++;
+                {
+                  rat_spr             [i][j][k] = spr++;
+//                rat_spr_update_table[i][j][k] = 0;
+                }
 	    }
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp	(revision 100)
@@ -95,4 +95,10 @@
               if (PORT_READ(in_SPR_COMMIT_VAL [i][j])) // out_SPR_COMMIT_ACK [i][j]
                 {
+                  log_printf(TRACE,Special_Register_unit,FUNCTION,"  * SPR_COMMIT [%d][%d]",i,j);
+                  log_printf(TRACE,Special_Register_unit,FUNCTION,"    * F            : %d, %d",PORT_READ(in_SPR_COMMIT_SR_F_VAL  [i][j]),PORT_READ(in_SPR_COMMIT_SR_F  [i][j]));
+                  log_printf(TRACE,Special_Register_unit,FUNCTION,"    * CY           : %d, %d",PORT_READ(in_SPR_COMMIT_SR_CY_VAL [i][j]),PORT_READ(in_SPR_COMMIT_SR_CY [i][j]));
+                  log_printf(TRACE,Special_Register_unit,FUNCTION,"    * OV           : %d, %d",PORT_READ(in_SPR_COMMIT_SR_OV_VAL [i][j]),PORT_READ(in_SPR_COMMIT_SR_OV [i][j]));
+
+                  log_printf(TRACE,Special_Register_unit,FUNCTION,"    * SPR (before) : %.8x",_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]->read());
                   SR * sr = static_cast<SR*>(_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]);
 
@@ -105,8 +111,14 @@
                   if (PORT_READ(in_SPR_COMMIT_SR_OV_VAL [i][j]))
                     sr->ov = PORT_READ(in_SPR_COMMIT_SR_OV [i][j]);
+
+                  log_printf(TRACE,Special_Register_unit,FUNCTION,"    * SPR (after)  : %.8x",_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]->read());
+
                 }
 
               if (PORT_READ(in_SPR_EVENT_VAL [i][j])) // out_SPR_EVENT_ACK [i][j]
                 {
+                  log_printf(TRACE,Special_Register_unit,FUNCTION,"  * SPR_EVENT [%d][%d]",i,j);
+                  log_printf(TRACE,Special_Register_unit,FUNCTION,"    * SPR (before) : %.8x",_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]->read());
+
                   SR * sr = static_cast<SR*>(_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]);
                   sr->dsx = PORT_READ(in_SPR_EVENT_SR_DSX [i][j]);
@@ -117,4 +129,6 @@
                   if (PORT_READ(in_SPR_EVENT_SR_TO_ESR [i][j]))
                   _spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_ESR ]->write(sr->read());
+
+                  log_printf(TRACE,Special_Register_unit,FUNCTION,"    * SPR (after)  : %.8x",_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]->read());
                 }
             }
