- Timestamp:
- Jan 8, 2009, 2:06:27 PM (16 years ago)
- Location:
- trunk
- Files:
-
- 8 edited
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- Unmodified
- Added
- Removed
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trunk
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters.cpp
r88 r100 17 17 #define FUNCTION "Queue::Parameters" 18 18 Parameters::Parameters (uint32_t size_queue, 19 uint32_t size_data ): 20 _size_queue (size_queue), 21 _size_data (size_data ) 19 uint32_t size_data , 20 uint32_t nb_port_slot): 21 _size_queue (size_queue), 22 _size_data (size_data ), 23 _nb_port_slot (nb_port_slot) 22 24 { 23 25 log_printf(FUNC,Queue,FUNCTION,"Begin"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters_msg_error.cpp
r81 r100 23 23 Parameters_test test("Queue"); 24 24 25 if (_nb_port_slot > _size_queue) 26 test.error(_("nb_port_slot must be <= size_queue\n")); 27 25 28 log_printf(FUNC,Queue,FUNCTION,"End"); 26 29 … … 30 33 }; // end namespace queue 31 34 }; // end namespace generic 32 33 35 }; // end namespace behavioural 34 36 }; // end namespace morpheo -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp
r88 r100 7 7 8 8 #include "Behavioural/Generic/Queue/include/Queue.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 38 39 ,IN 39 40 ,SOUTH, 40 "Generalist interface"41 _("Generalist interface") 41 42 #endif 42 43 ); … … 48 49 // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 49 50 { 50 Interface_fifo * interface = _interfaces->set_interface("insert" 51 #ifdef POSITION 52 ,IN 53 ,WEST 54 ,"Insertion of data" 55 #endif 56 ); 51 ALLOC0_INTERFACE("insert", IN, WEST, _("Interface of data write.")); 57 52 58 in_INSERT_VAL = interface->set_signal_valack_in (VAL);59 out_INSERT_ACK = interface->set_signal_valack_out(ACK);60 in_INSERT_DATA = interface->set_signal_in <Tdata_t> ("data",_param->_size_data);53 ALLOC0_VALACK_IN ( in_INSERT_VAL ,VAL); 54 ALLOC0_VALACK_OUT(out_INSERT_ACK ,ACK); 55 ALLOC0_SIGNAL_IN ( in_INSERT_DATA ,"data",Tdata_t,_param->_size_data); 61 56 } 57 62 58 // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 63 59 { 64 Interface_fifo * interface = _interfaces->set_interface("retire" 65 #ifdef POSITION 66 ,IN 67 ,EAST 68 ,"Retire of data" 69 #endif 70 ); 60 ALLOC0_INTERFACE("retire", OUT, EAST, _("Interface of data read.")); 71 61 72 out_RETIRE_VAL = interface->set_signal_valack_out(VAL); 73 in_RETIRE_ACK = interface->set_signal_valack_in (ACK); 74 out_RETIRE_DATA = interface->set_signal_out <Tdata_t> ("data", _param->_size_data); 62 ALLOC0_VALACK_OUT(out_RETIRE_VAL ,VAL); 63 ALLOC0_VALACK_IN ( in_RETIRE_ACK ,ACK); 64 ALLOC0_SIGNAL_OUT(out_RETIRE_DATA ,"data",Tdata_t,_param->_size_data); 65 } 66 67 // ~~~~~[ Interface "slot" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 68 { 69 ALLOC1_INTERFACE("slot", OUT, EAST, _("Internal slot."),_param->_nb_port_slot); 70 71 ALLOC1_VALACK_OUT(out_SLOT_VAL ,VAL); 72 ALLOC1_SIGNAL_OUT(out_SLOT_DATA ,"data",Tdata_t,_param->_size_data); 75 73 } 76 74 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_deallocation.cpp
r88 r100 7 7 8 8 #include "Behavioural/Generic/Queue/include/Queue.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 24 25 delete in_CLOCK ; 25 26 delete in_NRESET; 26 27 delete in_INSERT_VAL ; 28 delete out_INSERT_ACK ; 29 delete in_INSERT_DATA; 30 31 delete out_RETIRE_VAL ; 32 delete in_RETIRE_ACK ; 33 delete out_RETIRE_DATA; 27 28 DELETE0_SIGNAL( in_INSERT_VAL ,1); 29 DELETE0_SIGNAL(out_INSERT_ACK ,1); 30 DELETE0_SIGNAL( in_INSERT_DATA ,_param->_size_data); 31 32 DELETE0_SIGNAL(out_RETIRE_VAL ,1); 33 DELETE0_SIGNAL( in_RETIRE_ACK ,1); 34 DELETE0_SIGNAL(out_RETIRE_DATA ,_param->_size_data); 35 36 DELETE1_SIGNAL(out_SLOT_VAL ,_param->_nb_port_slot,1); 37 DELETE1_SIGNAL(out_SLOT_DATA ,_param->_nb_port_slot,_param->_size_data); 34 38 35 39 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_genMoore.cpp
r81 r100 19 19 { 20 20 log_printf(FUNC,Queue,FUNCTION,"Begin"); 21 21 22 // Output 22 23 internal_INSERT_ACK = not _queue_control->full(); 23 24 internal_RETIRE_VAL = not _queue_control->empty(); … … 26 27 PORT_WRITE(out_RETIRE_VAL , internal_RETIRE_VAL); 27 28 PORT_WRITE(out_RETIRE_DATA,_queue_data[(*_queue_control)[0]]); 29 30 // Slot 31 // Note : Slot 0 is the same slot as retire interface. 32 uint32_t nb_elt = _queue_control->nb_elt(); 33 34 for (uint32_t i=0; i<_param->_nb_port_slot; ++i) 35 { 36 PORT_WRITE(out_SLOT_VAL [i], i<nb_elt); 37 PORT_WRITE(out_SLOT_DATA [i],_queue_data[(*_queue_control)[i]]); 38 } 28 39 29 40 log_printf(FUNC,Queue,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_vhdl_body.cpp
r81 r100 20 20 { 21 21 log_printf(FUNC,Queue,FUNCTION,"Begin"); 22 vhdl->set_body ("-----------------------------------------------------------------------------"); 23 vhdl->set_body ("-- Output"); 24 vhdl->set_body ("-----------------------------------------------------------------------------"); 25 vhdl->set_body ("out_INSERT_ACK <= not reg_FULL;"); 26 vhdl->set_body ("out_RETIRE_VAL <= not reg_EMPTY;"); 27 28 if (_param->_size_queue > 1) 29 vhdl->set_body ("out_RETIRE_DATA <= reg_DATA(conv_integer(reg_PTR_READ));"); 30 else 31 vhdl->set_body ("out_RETIRE_DATA <= reg_DATA(0);"); 32 33 vhdl->set_body (""); 34 vhdl->set_body ("-----------------------------------------------------------------------------"); 35 vhdl->set_body ("-- Signal"); 36 vhdl->set_body ("-----------------------------------------------------------------------------"); 37 vhdl->set_body (""); 38 vhdl->set_body ("signal_PTR_EQUAL <="); 39 if (_param->_size_queue > 1) 40 { 41 vhdl->set_body ("\t'1' when signal_NEXT_PTR_READ = signal_NEXT_PTR_WRITE else"); 42 vhdl->set_body ("\t'0';"); 43 } 44 else 45 vhdl->set_body ("\t'1';"); 46 vhdl->set_body ("signal_NEXT_FULL <="); 47 vhdl->set_body ("\t'1' when signal_WRITE='1' and signal_PTR_EQUAL='1' else"); 48 vhdl->set_body ("\t'0' when signal_READ ='1' else"); 49 vhdl->set_body ("\treg_FULL ;"); 50 vhdl->set_body ("signal_NEXT_EMPTY <="); 51 vhdl->set_body ("\t'1' when signal_READ ='1' and signal_PTR_EQUAL='1' else"); 52 vhdl->set_body ("\t'0' when signal_WRITE='1' else"); 53 vhdl->set_body ("\treg_EMPTY;"); 54 vhdl->set_body (""); 55 vhdl->set_body ("-- read"); 56 vhdl->set_body ("signal_READ <= (not reg_EMPTY) and in_RETIRE_ACK;"); 57 22 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 23 vhdl->set_comment(0," Output"); 24 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 25 vhdl->set_body (0,"out_INSERT_ACK <= not signal_FULL;"); 26 vhdl->set_body (0,"out_RETIRE_VAL <= not signal_EMPTY;"); 27 28 if (_param->_size_queue > 1) 29 vhdl->set_body (0,"out_RETIRE_DATA <= reg_DATA(conv_integer(signal_PTR_READ));"); 30 else 31 vhdl->set_body (0,"out_RETIRE_DATA <= reg_DATA(0);"); 32 33 vhdl->set_body (0,""); 34 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 35 vhdl->set_comment(0," Slot"); 36 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 37 vhdl->set_body (0,""); 38 if (_param->_nb_port_slot > 1) 39 for (uint32_t i=0; i<_param->_nb_port_slot; ++i) 40 if (i==0) 41 vhdl->set_body (0,"signal_SLOT_0 <= signal_PTR_READ;"); 42 else 43 { 44 if (is_power2(_param->_size_queue)) 45 vhdl->set_body (0,"signal_SLOT_"+toString(i)+" <= signal_PTR_READ+"+std_logic_cst(log2(_param->_size_queue),i)+";"); 46 else 47 vhdl->set_body (0,"signal_SLOT_"+toString(i)+" <= const_PTR_INIT when signal_SLOT_"+toString(i-1)+" = const_PTR_MAX else signal_SLOT_"+toString(i-1)+"+'1';"); 48 } 49 50 for (uint32_t i=0; i<_param->_nb_port_slot; ++i) 51 { 52 if (_param->_nb_port_slot > 1) 53 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_VAL <= '1' when reg_NB_ELT > "+std_logic_cst(log2(_param->_size_queue+1),i)+" else '0';"); 54 else 55 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_VAL <= not signal_EMPTY;"); 56 57 if (_param->_nb_port_slot > 1) 58 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <= reg_DATA(conv_integer(signal_SLOT_"+toString(i)+"));"); 59 else 60 if (_param->_size_queue > 1) 61 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <= reg_DATA(conv_integer(signal_PTR_READ));"); 62 else 63 vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <= reg_DATA(conv_integer(0));"); 64 } 65 66 vhdl->set_body (0,""); 67 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 68 vhdl->set_comment(0," Signal"); 69 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 70 vhdl->set_body (0,""); 71 vhdl->set_body (0,"signal_READ <= (not signal_EMPTY) and in_RETIRE_ACK;"); 72 vhdl->set_body (0,"signal_WRITE <= (not signal_FULL ) and in_INSERT_VAL;"); 73 vhdl->set_body (0,""); 74 if (_param->_nb_port_slot>1) 75 { 76 vhdl->set_body (0,"signal_EMPTY <= '1' when reg_NB_ELT = "+std_logic_cst(log2(_param->_size_queue+1),0)+" else '0';"); 77 if (is_power2(_param->_size_queue)) 78 vhdl->set_body (0,"signal_FULL <= reg_NB_ELT "+std_logic_range(log2(_param->_size_queue),log2(_param->_size_queue))+";"); 79 else 80 vhdl->set_body (0,"signal_FULL <= '1' when reg_NB_ELT = "+std_logic_cst(log2(_param->_size_queue+1),_param->_size_queue)+" else '0';"); 81 } 82 else 83 { 84 vhdl->set_body (0,"signal_EMPTY <= reg_EMPTY;"); 85 vhdl->set_body (0,"signal_FULL <= reg_FULL ;"); 86 } 87 vhdl->set_body (0,""); 88 if (_param->_size_queue > 1) 89 { 90 vhdl->set_body (0,"signal_PTR_READ <= reg_PTR_READ;"); 91 if (_param->_nb_port_slot>1) 92 { 93 if (is_power2(_param->_size_queue)) 94 vhdl->set_body (0,"signal_PTR_WRITE <= reg_PTR_READ + reg_NB_ELT"+std_logic_range(log2(_param->_size_queue))+";"); 95 else 96 vhdl->set_body (0,"signal_PTR_WRITE <= reg_PTR_READ + reg_NB_ELT"+std_logic_range(log2(_param->_size_queue))+" when reg_PTR_READ + reg_NB_ELT"+std_logic_range(log2(_param->_size_queue)) +" <= const_PTR_MAX else reg_PTR_READ + reg_NB_ELT"+std_logic_range(log2(_param->_size_queue))+" - const_PTR_MAX-'1';"); 97 } 98 else 99 vhdl->set_body (0,"signal_PTR_WRITE <= reg_PTR_WRITE;"); 100 } 101 vhdl->set_body (0,""); 102 103 if (_param->_nb_port_slot>1) 104 { 105 vhdl->set_body (0,""); 106 vhdl->set_comment(0," nb_elt"); 58 107 if (_param->_size_queue > 1) 59 108 { 60 vhdl->set_body ("signal_NEXT_PTR_READ <= "); 61 vhdl->set_body ("\treg_PTR_READ when signal_READ='0' else"); 62 if (is_log2(_param->_size_queue) == false) 63 vhdl->set_body ("\tconst_PTR_INIT when reg_PTR_READ = const_PTR_MAX else"); 64 65 if (_param->_size_queue > 2) 66 vhdl->set_body ("\treg_PTR_READ +'1';"); 67 else 68 vhdl->set_body ("\tnot reg_PTR_READ;"); 69 } 70 vhdl->set_body (""); 71 vhdl->set_body ("-- write"); 72 vhdl->set_body ("signal_WRITE <= (not reg_FULL ) and in_INSERT_VAL;"); 73 if (_param->_size_queue > 1) 74 { 75 vhdl->set_body ("signal_NEXT_PTR_WRITE <= "); 76 vhdl->set_body ("\treg_PTR_WRITE when signal_WRITE='0' else"); 77 if (is_log2(_param->_size_queue) == false) 78 vhdl->set_body ("\tconst_PTR_INIT when reg_PTR_WRITE = const_PTR_MAX else"); 79 if (_param->_size_queue > 2) 80 vhdl->set_body ("\treg_PTR_WRITE+'1';"); 81 else 82 vhdl->set_body ("\tnot reg_PTR_WRITE;"); 83 } 84 vhdl->set_body (""); 85 vhdl->set_body ("-----------------------------------------------------------------------------"); 86 vhdl->set_body ("-- Registers"); 87 vhdl->set_body ("-----------------------------------------------------------------------------"); 88 vhdl->set_body (""); 89 vhdl->set_body ("queue_write: process (in_CLOCK)"); 90 vhdl->set_body ("begin -- process queue_write"); 91 vhdl->set_body ("\tif in_CLOCK'event and in_CLOCK = '1' then"); 92 vhdl->set_body (""); 93 vhdl->set_body ("\t\tif (in_NRESET = '0') then"); 94 if (_param->_size_queue > 1) 95 { 96 vhdl->set_body ("\t\t\treg_PTR_READ <= const_PTR_INIT;"); 97 vhdl->set_body ("\t\t\treg_PTR_WRITE <= const_PTR_INIT;"); 98 } 99 vhdl->set_body ("\t\t\treg_FULL <= '0';"); 100 vhdl->set_body ("\t\t\treg_EMPTY <= '1';"); 101 vhdl->set_body ("\t\telse"); 102 if (_param->_size_queue > 1) 103 { 104 vhdl->set_body ("\t\t\treg_PTR_READ <= signal_NEXT_PTR_READ ;"); 105 vhdl->set_body ("\t\t\treg_PTR_WRITE <= signal_NEXT_PTR_WRITE;"); 106 } 107 vhdl->set_body ("\t\t\treg_FULL <= signal_NEXT_FULL ;"); 108 vhdl->set_body ("\t\t\treg_EMPTY <= signal_NEXT_EMPTY;"); 109 vhdl->set_body (""); 110 vhdl->set_body ("\t\t\tif (signal_WRITE = '1') then"); 111 if (_param->_size_queue > 1) 112 vhdl->set_body ("\t\t\t\treg_DATA(conv_integer(reg_PTR_WRITE)) <= in_INSERT_DATA;"); 113 else 114 vhdl->set_body ("\t\t\t\treg_DATA(0) <= in_INSERT_DATA;"); 115 vhdl->set_body ("\t\t\tend if;"); 116 vhdl->set_body ("\t\tend if;"); 117 vhdl->set_body (""); 118 vhdl->set_body ("\tend if;"); 119 vhdl->set_body ("end process queue_write;"); 109 vhdl->set_body (0,"signal_NEXT_NB_ELT <= "); 110 vhdl->set_body (1,"reg_NB_ELT when (signal_READ xor signal_WRITE) = '0' else"); 111 if (_param->_size_queue > 2) 112 { 113 vhdl->set_body (1,"reg_NB_ELT +'1' when signal_WRITE='1' else"); 114 vhdl->set_body (1,"reg_NB_ELT -'1';"); 115 } 116 else 117 vhdl->set_body (1,"not reg_NB_ELT;"); 118 } 119 } 120 else 121 { 122 vhdl->set_body (0,"signal_PTR_EQUAL <="); 123 if (_param->_size_queue > 1) 124 { 125 vhdl->set_body (1,"'1' when signal_NEXT_PTR_READ = signal_NEXT_PTR_WRITE else"); 126 vhdl->set_body (1,"'0';"); 127 } 128 else 129 vhdl->set_body (1,"'1';"); 130 vhdl->set_body (0,"signal_NEXT_FULL <="); 131 vhdl->set_body (1,"'1' when signal_WRITE='1' and signal_PTR_EQUAL='1' else"); 132 vhdl->set_body (1,"'0' when signal_READ ='1' else"); 133 vhdl->set_body (1,"reg_FULL ;"); 134 vhdl->set_body (0,"signal_NEXT_EMPTY <="); 135 vhdl->set_body (1,"'1' when signal_READ ='1' and signal_PTR_EQUAL='1' else"); 136 vhdl->set_body (1,"'0' when signal_WRITE='1' else"); 137 vhdl->set_body (1,"reg_EMPTY;"); 138 vhdl->set_body (0,""); 139 140 vhdl->set_comment(0," write"); 141 if (_param->_size_queue > 1) 142 { 143 vhdl->set_body (0,"signal_NEXT_PTR_WRITE <= "); 144 vhdl->set_body (1,"reg_PTR_WRITE when signal_WRITE='0' else"); 145 if (is_log2(_param->_size_queue) == false) 146 vhdl->set_body (1,"const_PTR_INIT when reg_PTR_WRITE = const_PTR_MAX else"); 147 if (_param->_size_queue > 2) 148 vhdl->set_body (1,"reg_PTR_WRITE+'1';"); 149 else 150 vhdl->set_body (1,"not reg_PTR_WRITE;"); 151 } 152 } 153 154 vhdl->set_body (0,""); 155 vhdl->set_comment(0," read"); 156 if (_param->_size_queue > 1) 157 { 158 vhdl->set_body (0,"signal_NEXT_PTR_READ <= "); 159 vhdl->set_body (1,"reg_PTR_READ when signal_READ='0' else"); 160 if (is_log2(_param->_size_queue) == false) 161 vhdl->set_body (1,"const_PTR_INIT when reg_PTR_READ = const_PTR_MAX else"); 162 163 if (_param->_size_queue > 2) 164 vhdl->set_body (1,"reg_PTR_READ +'1';"); 165 else 166 vhdl->set_body (1,"not reg_PTR_READ;"); 167 } 168 vhdl->set_body (0,""); 169 170 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 171 vhdl->set_comment(0," Registers"); 172 vhdl->set_comment(0,"---------------------------------------------------------------------------"); 173 vhdl->set_body (0,""); 174 vhdl->set_body (0,"queue_write: process (in_CLOCK)"); 175 vhdl->set_body (0,"begin -- process queue_write"); 176 vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); 177 vhdl->set_body (0,""); 178 vhdl->set_body (2,"if (in_NRESET = '0') then"); 179 if (_param->_size_queue > 1) 180 { 181 vhdl->set_body (3,"reg_PTR_READ <= const_PTR_INIT;"); 182 if (_param->_nb_port_slot>1) 183 vhdl->set_body (3,"reg_NB_ELT <= "+std_logic_cst(log2(_param->_size_queue+1),0)+";"); 184 else 185 vhdl->set_body (3,"reg_PTR_WRITE <= const_PTR_INIT;"); 186 } 187 if (_param->_nb_port_slot<=1) 188 { 189 vhdl->set_body (3,"reg_FULL <= '0';"); 190 vhdl->set_body (3,"reg_EMPTY <= '1';"); 191 } 192 vhdl->set_body (2,"else"); 193 if (_param->_size_queue > 1) 194 { 195 vhdl->set_body (3,"reg_PTR_READ <= signal_NEXT_PTR_READ ;"); 196 if (_param->_nb_port_slot>1) 197 vhdl->set_body (3,"reg_NB_ELT <= signal_NEXT_NB_ELT ;"); 198 else 199 vhdl->set_body (3,"reg_PTR_WRITE <= signal_NEXT_PTR_WRITE;"); 200 } 201 if (_param->_nb_port_slot<=1) 202 { 203 vhdl->set_body (3,"reg_FULL <= signal_NEXT_FULL ;"); 204 vhdl->set_body (3,"reg_EMPTY <= signal_NEXT_EMPTY;"); 205 } 206 vhdl->set_body (0,""); 207 vhdl->set_body (3,"if (signal_WRITE = '1') then"); 208 if (_param->_size_queue > 1) 209 vhdl->set_body (3,"\treg_DATA(conv_integer(signal_PTR_WRITE)) <= in_INSERT_DATA;"); 210 else 211 vhdl->set_body (3,"\treg_DATA(0) <= in_INSERT_DATA;"); 212 vhdl->set_body (3,"end if;"); 213 vhdl->set_body (2,"end if;"); 214 vhdl->set_body (0,""); 215 vhdl->set_body (1,"end if;"); 216 vhdl->set_body (0,"end process queue_write;"); 120 217 121 218 log_printf(FUNC,Queue,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_vhdl_declaration.cpp
r81 r100 24 24 25 25 vhdl->set_signal ("reg_DATA ", "Tqueue"); 26 vhdl->set_signal ("reg_FULL ", 1); 27 vhdl->set_signal ("reg_EMPTY ", 1); 28 if (_param->_size_queue > 1) 29 { 30 vhdl->set_signal ("reg_PTR_READ ", log2(_param->_size_queue)); 31 vhdl->set_signal ("reg_PTR_WRITE ", log2(_param->_size_queue)); 32 } 26 33 27 vhdl->set_signal ("signal_READ ", 1); 34 28 vhdl->set_signal ("signal_WRITE ", 1); 35 vhdl->set_signal ("signal_PTR_EQUAL ", 1); 29 vhdl->set_signal ("signal_EMPTY ", 1); 30 vhdl->set_signal ("signal_FULL ", 1); 36 31 37 32 if (_param->_size_queue > 1) 38 33 { 39 vhdl->set_signal ("signal_NEXT_PTR_READ ", log2(_param->_size_queue)); 40 vhdl->set_signal ("signal_NEXT_PTR_WRITE", log2(_param->_size_queue)); 34 vhdl->set_signal ("reg_PTR_READ ", log2(_param->_size_queue)); 35 vhdl->set_signal ("signal_NEXT_PTR_READ ", log2(_param->_size_queue)); 36 vhdl->set_signal ("signal_PTR_READ ", log2(_param->_size_queue)); 37 vhdl->set_signal ("signal_PTR_WRITE ", log2(_param->_size_queue)); 41 38 } 42 39 40 if (_param->_nb_port_slot>1) 41 { 42 vhdl->set_signal ("reg_NB_ELT ", log2(_param->_size_queue+1)); 43 vhdl->set_signal ("signal_NEXT_NB_ELT ", log2(_param->_size_queue+1)); 44 for (uint32_t i=0; i<_param->_nb_port_slot; ++i) 45 vhdl->set_signal ("signal_SLOT_"+toString(i), log2(_param->_size_queue)); 46 } 47 else 48 { 49 if (_param->_size_queue > 1) 50 { 51 vhdl->set_signal ("reg_PTR_WRITE ", log2(_param->_size_queue)); 52 vhdl->set_signal ("signal_NEXT_PTR_WRITE", log2(_param->_size_queue)); 53 } 54 vhdl->set_signal ("reg_FULL ", 1); 55 vhdl->set_signal ("reg_EMPTY ", 1); 43 56 vhdl->set_signal ("signal_NEXT_FULL ", 1); 44 57 vhdl->set_signal ("signal_NEXT_EMPTY ", 1); 45 58 vhdl->set_signal ("signal_PTR_EQUAL ", 1); 59 } 60 46 61 if (_param->_size_queue > 1) 47 62 {
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