Changeset 100 for trunk/IPs/systemC/processor/Morpheo/Behavioural/include
- Timestamp:
- Jan 8, 2009, 2:06:27 PM (16 years ago)
- Location:
- trunk
- Files:
-
- 3 edited
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. (modified) (1 prop)
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IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h (modified) (1 diff)
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IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (modified) (1 diff)
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trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h
r97 r100 299 299 300 300 // Exception Execution 301 # define EXCEPTION_IFETCH_NONE 0x00 // Fetch Unit generate none exception302 # define EXCEPTION_IFETCH_INSTRUCTION_TLB 0x0a // ITLB miss303 # define EXCEPTION_IFETCH_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables304 # define EXCEPTION_IFETCH_BUS_ERROR 0x02 // Access at a invalid physical address305 306 # define EXCEPTION_DECOD_NONE 0x00 // none exception307 # define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION 0x01 // Instruction is illegal (no implemented)308 # define EXCEPTION_DECOD_SYSCALL 0x02 // System Call309 //#define EXCEPTION_DECOD_TRAP 0x0e // L.trap or debug unit (note : must read SR !)310 # define EXCEPTION_DECOD_INSTRUCTION_TLB 0x0a // ITLB miss311 # define EXCEPTION_DECOD_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables312 # define EXCEPTION_DECOD_BUS_ERROR 0x02 // Access at a invalid physical address313 314 # define EXCEPTION_ALU_NONE 0x00 // Functionnal unit generate none exception315 # define EXCEPTION_ALU_RANGE 0x0b // 316 # define EXCEPTION_ALU_SPR_ACCESS_INVALID 0x12 // SPR present in ALU but not compatible privilege317 # define EXCEPTION_ALU_SPR_ACCESS_MUST_READ 0x13 // SPR not present in ALU318 # define EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE 0x14 // SPR not present in ALU319 320 # define EXCEPTION_MEMORY_NONE 0x00 // Load/Store generate none exception321 # define EXCEPTION_MEMORY_ALIGNMENT 0x06 // Load/Store access is not aligned322 # define EXCEPTION_MEMORY_DATA_TLB 0x09 // DTLB miss323 # define EXCEPTION_MEMORY_DATA_PAGE 0x03 // No matching or page violation protection in pages tables324 # define EXCEPTION_MEMORY_BUS_ERROR 0x02 // Access at a invalid physical address325 # define EXCEPTION_MEMORY_MISS_SPECULATION 0x10 // Load miss speculation326 # define EXCEPTION_MEMORY_LOAD_SPECULATIVE 0x11 // The load is speculative : write in register file, but don't commit327 328 # define EXCEPTION_CUSTOM_NONE 0x00 // Custom unit generate none exception329 # define EXCEPTION_CUSTOM_CUST_0 0x19 // Reserved for custom exceptions330 # define EXCEPTION_CUSTOM_CUST_1 0x1a // Reserved for custom exceptions331 # define EXCEPTION_CUSTOM_CUST_2 0x1b // Reserved for custom exceptions332 # define EXCEPTION_CUSTOM_CUST_3 0x1c // Reserved for custom exceptions333 # define EXCEPTION_CUSTOM_CUST_4 0x1d // Reserved for custom exceptions334 # define EXCEPTION_CUSTOM_CUST_5 0x1e // Reserved for custom exceptions335 # define EXCEPTION_CUSTOM_CUST_6 0x1f // Reserved for custom exceptions336 337 # define EXCEPTION_USE_NONE 0x00 // 338 # define EXCEPTION_USE_ILLEGAL_INSTRUCTION 0x01 // illegal_instruction339 # define EXCEPTION_USE_RANGE 0x02 // range340 # define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT 0x03 // TLB miss, page fault, bus error, alignment341 # define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT 0x04 // TLB miss, page fault, bus error342 # define EXCEPTION_USE_SYSCALL 0x05 // syscall343 # define EXCEPTION_USE_TRAP 0x06 // trap344 # define EXCEPTION_USE_CUSTOM_0 0x07 // 345 # define EXCEPTION_USE_CUSTOM_1 0x08 // 346 # define EXCEPTION_USE_CUSTOM_2 0x09 // 347 # define EXCEPTION_USE_CUSTOM_3 0x0a // 348 # define EXCEPTION_USE_CUSTOM_4 0x0b // 349 # define EXCEPTION_USE_CUSTOM_5 0x0c // 350 # define EXCEPTION_USE_CUSTOM_6 0x0d // 301 # define EXCEPTION_IFETCH_NONE 0x00 // Fetch Unit generate none exception 302 # define EXCEPTION_IFETCH_INSTRUCTION_TLB 0x0a // ITLB miss 303 # define EXCEPTION_IFETCH_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables 304 # define EXCEPTION_IFETCH_BUS_ERROR 0x02 // Access at a invalid physical address 305 306 # define EXCEPTION_DECOD_NONE 0x00 // none exception 307 # define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION 0x01 // Instruction is illegal (no implemented) 308 # define EXCEPTION_DECOD_SYSCALL 0x02 // System Call 309 //#define EXCEPTION_DECOD_TRAP 0x0e // L.trap or debug unit (note : must read SR !) 310 # define EXCEPTION_DECOD_INSTRUCTION_TLB 0x0a // ITLB miss 311 # define EXCEPTION_DECOD_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables 312 # define EXCEPTION_DECOD_BUS_ERROR 0x02 // Access at a invalid physical address 313 314 # define EXCEPTION_ALU_NONE 0x00 // Functionnal unit generate none exception 315 # define EXCEPTION_ALU_RANGE 0x0b // 316 # define EXCEPTION_ALU_SPR_ACCESS_INVALID 0x12 // * SPR present in ALU but not compatible privilege 317 # define EXCEPTION_ALU_SPR_ACCESS_MUST_READ 0x13 // * SPR not present in ALU 318 # define EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE 0x14 // * SPR not present in ALU 319 320 # define EXCEPTION_MEMORY_NONE 0x00 // Load/Store generate none exception 321 # define EXCEPTION_MEMORY_ALIGNMENT 0x06 // Load/Store access is not aligned 322 # define EXCEPTION_MEMORY_DATA_TLB 0x09 // DTLB miss 323 # define EXCEPTION_MEMORY_DATA_PAGE 0x03 // No matching or page violation protection in pages tables 324 # define EXCEPTION_MEMORY_BUS_ERROR 0x02 // Access at a invalid physical address 325 # define EXCEPTION_MEMORY_MISS_SPECULATION 0x10 // * Load miss speculation 326 # define EXCEPTION_MEMORY_LOAD_SPECULATIVE 0x11 // * The load is speculative : write in register file, but don't commit 327 328 # define EXCEPTION_CUSTOM_NONE 0x00 // Custom unit generate none exception 329 # define EXCEPTION_CUSTOM_CUST_0 0x19 // Reserved for custom exceptions 330 # define EXCEPTION_CUSTOM_CUST_1 0x1a // Reserved for custom exceptions 331 # define EXCEPTION_CUSTOM_CUST_2 0x1b // Reserved for custom exceptions 332 # define EXCEPTION_CUSTOM_CUST_3 0x1c // Reserved for custom exceptions 333 # define EXCEPTION_CUSTOM_CUST_4 0x1d // Reserved for custom exceptions 334 # define EXCEPTION_CUSTOM_CUST_5 0x1e // Reserved for custom exceptions 335 # define EXCEPTION_CUSTOM_CUST_6 0x1f // Reserved for custom exceptions 336 337 # define EXCEPTION_USE_NONE 0x00 // 338 # define EXCEPTION_USE_ILLEGAL_INSTRUCTION 0x01 // illegal_instruction 339 # define EXCEPTION_USE_RANGE 0x02 // range 340 # define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT 0x03 // TLB miss, page fault, bus error, alignment 341 # define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT 0x04 // TLB miss, page fault, bus error 342 # define EXCEPTION_USE_SYSCALL 0x05 // syscall 343 # define EXCEPTION_USE_TRAP 0x06 // trap 344 # define EXCEPTION_USE_CUSTOM_0 0x07 // 345 # define EXCEPTION_USE_CUSTOM_1 0x08 // 346 # define EXCEPTION_USE_CUSTOM_2 0x09 // 347 # define EXCEPTION_USE_CUSTOM_3 0x0a // 348 # define EXCEPTION_USE_CUSTOM_4 0x0b // 349 # define EXCEPTION_USE_CUSTOM_5 0x0c // 350 # define EXCEPTION_USE_CUSTOM_6 0x0d // 351 351 352 352 # define exception_ifetch_to_exception_decod(x) x -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h
r98 r100 10 10 #define MORPHEO_MAJOR_VERSION 0 11 11 #define MORPHEO_MINOR_VERSION 2 12 #define MORPHEO_REVISION " 98"12 #define MORPHEO_REVISION "100" 13 13 #define MORPHEO_CODENAME "Castor" 14 14 15 #define MORPHEO_DATE_DAY " 31"16 #define MORPHEO_DATE_MONTH " 12"17 #define MORPHEO_DATE_YEAR "200 8"15 #define MORPHEO_DATE_DAY "08" 16 #define MORPHEO_DATE_MONTH "01" 17 #define MORPHEO_DATE_YEAR "2009" 18 18 19 19 #define MORPHEO_VERSION morpheo::toString(MORPHEO_MAJOR_VERSION)+"."+morpheo::toString(MORPHEO_MINOR_VERSION)+"."+morpheo::toString(MORPHEO_REVISION)
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