Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h	(revision 100)
@@ -299,54 +299,54 @@
 
   // Exception Execution
-#  define EXCEPTION_IFETCH_NONE                    0x00       // Fetch Unit generate none exception
-#  define EXCEPTION_IFETCH_INSTRUCTION_TLB         0x0a       // ITLB miss
-#  define EXCEPTION_IFETCH_INSTRUCTION_PAGE        0x04       // No matching or page violation protection in pages tables
-#  define EXCEPTION_IFETCH_BUS_ERROR               0x02       // Access at a invalid physical address
-
-#  define EXCEPTION_DECOD_NONE                     0x00       // none exception
-#  define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION      0x01       // Instruction is illegal (no implemented)
-#  define EXCEPTION_DECOD_SYSCALL                  0x02       // System Call
-//#define EXCEPTION_DECOD_TRAP                     0x0e       // L.trap or debug unit (note : must read SR !)
-#  define EXCEPTION_DECOD_INSTRUCTION_TLB          0x0a       // ITLB miss
-#  define EXCEPTION_DECOD_INSTRUCTION_PAGE         0x04       // No matching or page violation protection in pages tables
-#  define EXCEPTION_DECOD_BUS_ERROR                0x02       // Access at a invalid physical address
-
-#  define EXCEPTION_ALU_NONE                       0x00       // Functionnal unit generate none exception
-#  define EXCEPTION_ALU_RANGE                      0x0b       // 
-#  define EXCEPTION_ALU_SPR_ACCESS_INVALID         0x12       // SPR     present in ALU but not compatible privilege
-#  define EXCEPTION_ALU_SPR_ACCESS_MUST_READ       0x13       // SPR not present in ALU
-#  define EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE      0x14       // SPR not present in ALU
-
-#  define EXCEPTION_MEMORY_NONE                    0x00       // Load/Store generate none exception
-#  define EXCEPTION_MEMORY_ALIGNMENT               0x06       // Load/Store access is not aligned
-#  define EXCEPTION_MEMORY_DATA_TLB                0x09       // DTLB miss
-#  define EXCEPTION_MEMORY_DATA_PAGE               0x03       // No matching or page violation protection in pages tables
-#  define EXCEPTION_MEMORY_BUS_ERROR               0x02       // Access at a invalid physical address
-#  define EXCEPTION_MEMORY_MISS_SPECULATION        0x10       // Load miss speculation
-#  define EXCEPTION_MEMORY_LOAD_SPECULATIVE        0x11       // The load is speculative : write in register file, but don't commit
-
-#  define EXCEPTION_CUSTOM_NONE                    0x00       // Custom unit generate none exception
-#  define EXCEPTION_CUSTOM_CUST_0                  0x19       // Reserved for custom exceptions
-#  define EXCEPTION_CUSTOM_CUST_1                  0x1a       // Reserved for custom exceptions
-#  define EXCEPTION_CUSTOM_CUST_2                  0x1b       // Reserved for custom exceptions
-#  define EXCEPTION_CUSTOM_CUST_3                  0x1c       // Reserved for custom exceptions
-#  define EXCEPTION_CUSTOM_CUST_4                  0x1d       // Reserved for custom exceptions
-#  define EXCEPTION_CUSTOM_CUST_5                  0x1e       // Reserved for custom exceptions
-#  define EXCEPTION_CUSTOM_CUST_6                  0x1f       // Reserved for custom exceptions
-
-#  define EXCEPTION_USE_NONE                       0x00       // 
-#  define EXCEPTION_USE_ILLEGAL_INSTRUCTION        0x01       // illegal_instruction
-#  define EXCEPTION_USE_RANGE                      0x02       // range
-#  define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT      0x03       // TLB miss, page fault, bus error, alignment
-#  define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT   0x04       // TLB miss, page fault, bus error
-#  define EXCEPTION_USE_SYSCALL                    0x05       // syscall
-#  define EXCEPTION_USE_TRAP                       0x06       // trap
-#  define EXCEPTION_USE_CUSTOM_0                   0x07       // 
-#  define EXCEPTION_USE_CUSTOM_1                   0x08       // 
-#  define EXCEPTION_USE_CUSTOM_2                   0x09       // 
-#  define EXCEPTION_USE_CUSTOM_3                   0x0a       // 
-#  define EXCEPTION_USE_CUSTOM_4                   0x0b       // 
-#  define EXCEPTION_USE_CUSTOM_5                   0x0c       // 
-#  define EXCEPTION_USE_CUSTOM_6                   0x0d       // 
+#  define EXCEPTION_IFETCH_NONE                    0x00       //   Fetch Unit generate none exception
+#  define EXCEPTION_IFETCH_INSTRUCTION_TLB         0x0a       //   ITLB miss
+#  define EXCEPTION_IFETCH_INSTRUCTION_PAGE        0x04       //   No matching or page violation protection in pages tables
+#  define EXCEPTION_IFETCH_BUS_ERROR               0x02       //   Access at a invalid physical address
+                                                                   
+#  define EXCEPTION_DECOD_NONE                     0x00       //   none exception
+#  define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION      0x01       //   Instruction is illegal (no implemented)
+#  define EXCEPTION_DECOD_SYSCALL                  0x02       //   System Call
+//#define EXCEPTION_DECOD_TRAP                     0x0e       //   L.trap or debug unit (note : must read SR !)
+#  define EXCEPTION_DECOD_INSTRUCTION_TLB          0x0a       //   ITLB miss
+#  define EXCEPTION_DECOD_INSTRUCTION_PAGE         0x04       //   No matching or page violation protection in pages tables
+#  define EXCEPTION_DECOD_BUS_ERROR                0x02       //   Access at a invalid physical address
+                                                                   
+#  define EXCEPTION_ALU_NONE                       0x00       //   Functionnal unit generate none exception
+#  define EXCEPTION_ALU_RANGE                      0x0b       //   
+#  define EXCEPTION_ALU_SPR_ACCESS_INVALID         0x12       // * SPR     present in ALU but not compatible privilege
+#  define EXCEPTION_ALU_SPR_ACCESS_MUST_READ       0x13       // * SPR not present in ALU
+#  define EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE      0x14       // * SPR not present in ALU
+                                                                   
+#  define EXCEPTION_MEMORY_NONE                    0x00       //   Load/Store generate none exception
+#  define EXCEPTION_MEMORY_ALIGNMENT               0x06       //   Load/Store access is not aligned
+#  define EXCEPTION_MEMORY_DATA_TLB                0x09       //   DTLB miss
+#  define EXCEPTION_MEMORY_DATA_PAGE               0x03       //   No matching or page violation protection in pages tables
+#  define EXCEPTION_MEMORY_BUS_ERROR               0x02       //   Access at a invalid physical address
+#  define EXCEPTION_MEMORY_MISS_SPECULATION        0x10       // * Load miss speculation
+#  define EXCEPTION_MEMORY_LOAD_SPECULATIVE        0x11       // * The load is speculative : write in register file, but don't commit
+                                                                   
+#  define EXCEPTION_CUSTOM_NONE                    0x00       //   Custom unit generate none exception
+#  define EXCEPTION_CUSTOM_CUST_0                  0x19       //   Reserved for custom exceptions
+#  define EXCEPTION_CUSTOM_CUST_1                  0x1a       //   Reserved for custom exceptions
+#  define EXCEPTION_CUSTOM_CUST_2                  0x1b       //   Reserved for custom exceptions
+#  define EXCEPTION_CUSTOM_CUST_3                  0x1c       //   Reserved for custom exceptions
+#  define EXCEPTION_CUSTOM_CUST_4                  0x1d       //   Reserved for custom exceptions
+#  define EXCEPTION_CUSTOM_CUST_5                  0x1e       //   Reserved for custom exceptions
+#  define EXCEPTION_CUSTOM_CUST_6                  0x1f       //   Reserved for custom exceptions
+                                                                   
+#  define EXCEPTION_USE_NONE                       0x00       //   
+#  define EXCEPTION_USE_ILLEGAL_INSTRUCTION        0x01       //   illegal_instruction
+#  define EXCEPTION_USE_RANGE                      0x02       //   range
+#  define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT      0x03       //   TLB miss, page fault, bus error, alignment
+#  define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT   0x04       //   TLB miss, page fault, bus error
+#  define EXCEPTION_USE_SYSCALL                    0x05       //   syscall
+#  define EXCEPTION_USE_TRAP                       0x06       //   trap
+#  define EXCEPTION_USE_CUSTOM_0                   0x07       //   
+#  define EXCEPTION_USE_CUSTOM_1                   0x08       //   
+#  define EXCEPTION_USE_CUSTOM_2                   0x09       //   
+#  define EXCEPTION_USE_CUSTOM_3                   0x0a       //   
+#  define EXCEPTION_USE_CUSTOM_4                   0x0b       //   
+#  define EXCEPTION_USE_CUSTOM_5                   0x0c       //   
+#  define EXCEPTION_USE_CUSTOM_6                   0x0d       //   
 
 #  define exception_ifetch_to_exception_decod(x) x
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h	(revision 100)
@@ -10,10 +10,10 @@
 #define MORPHEO_MAJOR_VERSION 0
 #define MORPHEO_MINOR_VERSION 2
-#define MORPHEO_REVISION      "98"
+#define MORPHEO_REVISION      "100"
 #define MORPHEO_CODENAME      "Castor"
 
-#define MORPHEO_DATE_DAY      "31"  
-#define MORPHEO_DATE_MONTH    "12"
-#define MORPHEO_DATE_YEAR     "2008" 
+#define MORPHEO_DATE_DAY      "08"  
+#define MORPHEO_DATE_MONTH    "01"
+#define MORPHEO_DATE_YEAR     "2009" 
 
 #define MORPHEO_VERSION       morpheo::toString(MORPHEO_MAJOR_VERSION)+"."+morpheo::toString(MORPHEO_MINOR_VERSION)+"."+morpheo::toString(MORPHEO_REVISION)
