Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp (revision 100) @@ -40,5 +40,7 @@ // Debug & Log File //-------------------------------------------------- - debug_init (fromString(_simulator->getParam("debug_level"))); + debug_init (fromString(_simulator->getParam("debug_level")), + fromString (_simulator->getParam("debug_cycle_start")), + fromString (_simulator->getParam("debug_cycle_stop"))); log_init(fromString(_simulator->getParam("debug_have_log_file")), @@ -79,6 +81,6 @@ // Parameters_Statistics //-------------------------------------------------- - _param_statistics = new Parameters_Statistics (fromString(_simulator->getParam("nb_cycle_before_begin")), - fromString(_simulator->getParam("period_save"))); + _param_statistics = new Parameters_Statistics (fromString(_simulator->getParam("statistics_cycle_start")), + fromString(_simulator->getParam("statistics_period"))); //-------------------------------------------------- Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp (revision 100) @@ -255,9 +255,9 @@ // Result op->_timing = param->_timing[op->_type][op->_operation]; - op->_data_rd = imm; + op->_data_rd = imm<<2; // add "00" //op->_data_re = 0; op->_exception = EXCEPTION_ALU_NONE; op->_no_sequence = 1; - op->_address = gpr; + op->_address = gpr>>2; // del "00" }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp (revision 100) @@ -279,7 +279,7 @@ - transaction_in.push_back(execute_transaction(_param,0,0,0, 31,OPERATION_BRANCH_L_JALR ,TYPE_BRANCH,0,0xdeadbeef,0x0 ,0x12345678,0 ,0,63,0xdeadbeef,0,15,FLAG_CY ,EXCEPTION_NONE ,1,0x12345678)); // jr - transaction_in.push_back(execute_transaction(_param,0,0,0, 32,OPERATION_BRANCH_L_JALR ,TYPE_BRANCH,1,0xdeadbeef,0x0 ,0x12345678,0 ,1,63,0xdeadbeef,0,15,FLAG_CY ,EXCEPTION_NONE ,1,0x12345678)); // jal - transaction_in.push_back(execute_transaction(_param,0,0,0, 33,OPERATION_BRANCH_L_JALR ,TYPE_BRANCH,1,0xdeadbeef,0x0 ,0x12345678,0 ,1,63,0xdeadbeef,0,15,FLAG_CY ,EXCEPTION_NONE ,1,0x12345678)); // jalr + transaction_in.push_back(execute_transaction(_param,0,0,0, 31,OPERATION_BRANCH_L_JALR ,TYPE_BRANCH,0,0xdeadbeef,0x0 ,0x12345678,0 ,0,63,0xdeadbeef,0,15,FLAG_CY ,EXCEPTION_NONE ,1,0x12345678>>2)); // jr + transaction_in.push_back(execute_transaction(_param,0,0,0, 32,OPERATION_BRANCH_L_JALR ,TYPE_BRANCH,1,0xdeadbeef,0x0 ,0x12345678,0 ,1,63,0xdeadbeef<<2,0,15,FLAG_CY ,EXCEPTION_NONE ,1,0x12345678>>2)); // jal + transaction_in.push_back(execute_transaction(_param,0,0,0, 33,OPERATION_BRANCH_L_JALR ,TYPE_BRANCH,1,0xdeadbeef,0x0 ,0x12345678,0 ,1,63,0xdeadbeef<<2,0,15,FLAG_CY ,EXCEPTION_NONE ,1,0x12345678>>2)); // jalr transaction_in.push_back(execute_transaction(_param,0,0,0, 34,OPERATION_EXTEND_L_EXTEND_S,TYPE_EXTEND,1,8 ,0x12345678,0x0 ,0 ,1,63,0x00000078,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp (revision 100) @@ -138,5 +138,5 @@ log_printf(TRACE,Functionnal_unit,FUNCTION," * exception : %d" ,_execute_operation_in->_exception ); log_printf(TRACE,Functionnal_unit,FUNCTION," * no_sequence : %d" ,_execute_operation_in->_no_sequence); - log_printf(TRACE,Functionnal_unit,FUNCTION," * address : %.8x",_execute_operation_in->_address ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * address : %.8x (%.8x)",_execute_operation_in->_address,_execute_operation_in->_address<<2); #ifdef STATISTICS Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl.cpp (revision 100) @@ -32,5 +32,6 @@ param_queue = new morpheo::behavioural::generic::queue::Parameters (_param->_size_queue, - _param->_size_internal_queue + _param->_size_internal_queue, + 0 ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl.cpp (revision 100) @@ -34,5 +34,6 @@ param_queue = new morpheo::behavioural::generic::queue::Parameters (_param->_size_queue, - _param->_size_internal_queue + _param->_size_internal_queue, + 0 ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp (revision 100) @@ -903,6 +903,6 @@ inst->_type = instruction_information(INSTRUCTION_L_JALR)._type ; //TYPE_BRANCH; inst->_operation = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR; - inst->_has_immediat = 0; - inst->_immediat = 0; // unnecessary + inst->_has_immediat = 1; + inst->_immediat = inst->_address_next+1; inst->_read_ra = 0; inst->_num_reg_ra = 0; //unnecessary Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/config_mono_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/config_mono_context.cfg (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/config_mono_context.cfg (revision 100) @@ -3,5 +3,5 @@ 1 1 *4 # nb_decod_unit 30 30 +32 # size_address -1 1 *4 # nb_instruction [0] [nb_context] +1 4 *2 # nb_instruction [0] [nb_context] 1 1 *4 # size_depth [0] [nb_context] 4 4 *4 # nb_inst_decod [0] [nb_decod_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp (revision 100) @@ -362,4 +362,8 @@ // Initialisation + const bool test1 = false; + const bool test2 = true ; + const bool test3 = false; + const bool test4 = false; const uint32_t seed = 0; @@ -402,4 +406,5 @@ LABEL("Iteration %d",iteration); + if (test1) { LABEL("Test sequential"); @@ -481,4 +486,5 @@ } + if (test2) { LABEL("Test no sequential - L.J"); @@ -489,11 +495,13 @@ for (uint32_t i=0; i<_param->_nb_instruction [context]; i++) { - Taddress_t addr = (1<<(_param->_nb_instruction[context]+4)); - Taddress_t addr_src = addr+i; + Taddress_t pc_current = (1<<(_param->_nb_instruction[context]+3)); + Taddress_t pc_previous = pc_current-1; + Taddress_t addr_src = pc_current+i; Taddress_t addr_dest = 0xdeadbeef; - - in_PREDICT_PC_PREVIOUS [context]->write(0); - in_PREDICT_PC_CURRENT [context]->write(addr); - in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]->write(0); + Tcontrol_t is_ds_take= rand()%2; + + in_PREDICT_PC_PREVIOUS [context]->write(pc_previous); + in_PREDICT_PC_CURRENT [context]->write(pc_current); + in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]->write(is_ds_take); bool find = false; @@ -515,5 +523,5 @@ LABEL(" * BTB address : 0x%x",out_PREDICT_BTB_ADDRESS [port]->read()); if ((out_PREDICT_BTB_CONTEXT_ID [port]->read() == context) and - (out_PREDICT_BTB_ADDRESS [port]->read() == addr )) + (out_PREDICT_BTB_ADDRESS [port]->read() == (is_ds_take)?pc_previous:pc_current )) { in_PREDICT_BTB_ACK [port]->write((rand()%100)read()); + LABEL ("PREDICT_ACK : %d",out_PREDICT_ACK[context]->read()); + if (in_PREDICT_VAL[context]->read() and out_PREDICT_ACK[context]->read()) { LABEL ("PREDICT [%d] - Transaction accepted",context); + LABEL (" * pc_previous: 0x%x",pc_previous ); + LABEL (" * pc_current : 0x%x",pc_current ); + LABEL (" * addr_src : 0x%x",addr_src ); + LABEL (" * addr_dest : 0x%x",addr_dest ); + LABEL (" * is_ds_take : %d" ,is_ds_take); + find = true; - - TEST(Taddress_t ,out_PREDICT_PC_NEXT [context]->read(),addr_dest); - TEST(Tcontrol_t ,out_PREDICT_PC_NEXT_IS_DS_TAKE [context]->read(),i==(_param->_nb_instruction [context]-1)); + + Tcontrol_t next_is_ds_take = (not is_ds_take and (i==(_param->_nb_instruction [context]-1))); + + TEST(Tcontrol_t ,out_PREDICT_PC_NEXT_IS_DS_TAKE [context]->read(), next_is_ds_take); + TEST(Taddress_t ,out_PREDICT_PC_NEXT [context]->read(),(next_is_ds_take)?(addr_src+1):addr_dest); TEST(Tinst_ifetch_ptr_t,out_PREDICT_INST_IFETCH_PTR [context]->read(),i); - TEST(Tbranch_state_t ,out_PREDICT_BRANCH_STATE [context]->read(),BRANCH_STATE_NSPEC_TAKE); + TEST(Tbranch_state_t ,out_PREDICT_BRANCH_STATE [context]->read(),(next_is_ds_take)?BRANCH_STATE_NONE:BRANCH_STATE_NSPEC_TAKE); // TEST(Tprediction_ptr_t ,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context]->read(),0); - uint32_t k=((addr_src%_param->_nb_instruction[context])==_param->_nb_instruction[context]-1)?_param->_nb_instruction[context]:((addr_src%_param->_nb_instruction[context])+2); + uint32_t k=((is_ds_take)?1:((next_is_ds_take)?_param->_nb_instruction[context]:((addr_src%_param->_nb_instruction [context])+2))); + + +// ((addr_src%_param->_nb_instruction[context])==_param->_nb_instruction[context]-1)?_param->_nb_instruction[context]:((addr_src%_param->_nb_instruction[context])+2); + LABEL("instruction enable : "); LABEL(" [0:%d[ = 1",k); - LABEL(" [%d:%d[ = 1",k,_param->_nb_instruction[context]); + LABEL(" [%d:%d[ = 0",k,_param->_nb_instruction[context]); for (uint32_t j=0; jread(),1); + TEST(Tcontrol_t ,out_PREDICT_INSTRUCTION_ENABLE [context][j]->read(),1); for (uint32_t j=k; j<_param->_nb_instruction[context]; j++) - TEST(Tcontrol_t ,out_PREDICT_INSTRUCTION_ENABLE [context][j]->read(),0); + TEST(Tcontrol_t ,out_PREDICT_INSTRUCTION_ENABLE [context][j]->read(),0); TEST(Tcontrol_t ,out_PREDICT_BTB_VAL [port]->read(),1); TEST(Tcontext_t ,out_PREDICT_BTB_CONTEXT_ID [port]->read(),context); - TEST(Taddress_t ,out_PREDICT_BTB_ADDRESS [port]->read(),addr); + TEST(Taddress_t ,out_PREDICT_BTB_ADDRESS [port]->read(),(is_ds_take)?pc_previous:pc_current); } @@ -571,5 +594,6 @@ } } - + + if (test3) { LABEL("Decod - Ok"); @@ -618,4 +642,5 @@ } + if (test4) { LABEL("Decod - Ko"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp (revision 100) @@ -27,5 +27,4 @@ if (PORT_READ(in_NRESET)) { - // Init Tcontrol_t ack [_param->_nb_context]; @@ -36,5 +35,6 @@ { log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * PREDICT [%d]",i); - + + // No access Tcontrol_t btb_val = false; Tcontrol_t dir_val = false; @@ -42,4 +42,5 @@ Tcontrol_t upt_val = false; + // Get ack Tcontrol_t btb_ack = PORT_READ(in_PREDICT_BTB_ACK [i]); Tcontrol_t dir_ack = PORT_READ(in_PREDICT_DIR_ACK [i]); @@ -47,11 +48,14 @@ Tcontrol_t upt_ack = PORT_READ(in_PREDICT_UPT_ACK [i]); + // Read context_id Tcontext_t context = (reg_PREDICT_PRIORITY+i)%_param->_nb_context; // priority log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * context : %d",context); + // Now : ack transaction ack [context] = 1; if (PORT_READ(in_PREDICT_VAL[context]) == 0) { + // Nothing log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * not valid ..."); @@ -63,12 +67,14 @@ else { + // Have transaction log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * valid ..."); + // Read information (PC) Taddress_t pc_previous = PORT_READ(in_PREDICT_PC_PREVIOUS [context]); Taddress_t pc_current = PORT_READ(in_PREDICT_PC_CURRENT [context]); Tcontrol_t pc_current_is_ds_take = PORT_READ(in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_previous : 0x%.8x",pc_previous ); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current : 0x%.8x",pc_current ); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_previous : 0x%.8x (0x%.8x)",pc_previous,pc_previous<<2); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current : 0x%.8x (0x%.8x)",pc_current ,pc_current <<2); log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current_is_ds_take : %d" ,pc_current_is_ds_take); @@ -80,30 +86,35 @@ // STEP (1) - Compute the address source - // if pc_current is a ds take, then pc_previous is a branchement + // -> if pc_current is a ds take, then pc_previous is a branchement + // get branchement address to send at the BTB Taddress_t address = (pc_current_is_ds_take)?pc_previous:pc_current; + // Address_lsb = position in fetch packet Taddress_t address_lsb = pc_current%_param->_nb_instruction [context]; //if pc_current_is_ds_take, then pc_current%_param->_nb_instruction [context] == 0 Taddress_t address_msb; - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%.8x",address); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%.8x (0x%.8x)",address,address<<2); log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_lsb : %d" ,address_lsb); // STEP (2) - Test if branch (access at branch_target_buffer) + // Access at the btb btb_val = true; + // Create the request if (_param->_have_port_context_id) PORT_WRITE(out_PREDICT_BTB_CONTEXT_ID [i],context); PORT_WRITE(out_PREDICT_BTB_ADDRESS [i],address); + // Transaction can be ack if btb is not busy ack [context] &= btb_ack; log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * btb_ack : %d" ,btb_ack); - // BTB_ack = 0 ? + // BTB_ack = 0 ? else can continue if (not btb_ack) continue; - // special case : - // if pc_current_is_ds, then pc_previous have branch, also hit must be set. - // else : a another branch have eject this branch : can't accurate + // Test a special case : + // if pc_current is a delay slot, then pc_previous is a branchement instruction, also hit must be set. + // else : an another branch instruction have eject this branch : can't accurate Tcontrol_t hit = PORT_READ(in_PREDICT_BTB_HIT[i]); Tcontrol_t is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and not (pc_current_is_ds_take and not hit); @@ -112,193 +123,214 @@ log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * is_accurate : %d" ,is_accurate); - // STEP (3) : Test if have branch in the packet + // STEP (3) : Test if BTB find a branch instruction in the packet if (hit == 1) { + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BTB hit : no sequential order"); + // STEP (3a) : branch - test condition bool use_dir = false; bool use_ras = false; bool use_upt = false; - - Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); - Taddress_t address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); - Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); - Tcontrol_t push ; - Tcontrol_t direction; - - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * condition : %s" ,toString(condition).c_str()); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x",address_src); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_dest : 0x%.8x",address_dest); - - switch (condition) - { - case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : // l.j - { - // use none unit (dir, upt and ras) - direction = true; - pc_next = address_dest; - branch_state = BRANCH_STATE_NSPEC_TAKE; - break; - } - case BRANCH_CONDITION_NONE_WITH_WRITE_STACK : // l.jal - { - use_upt = true; - use_ras = true; - push = true; - direction = true; - pc_next = address_dest; - branch_state = BRANCH_STATE_NSPEC_TAKE; - break; - } - case BRANCH_CONDITION_FLAG_UNSET : // l.bnf - case BRANCH_CONDITION_FLAG_SET : // l.bf - { - use_upt = true; - use_dir = true; - // Test direction - direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same - if (direction = 1) - { - branch_state = BRANCH_STATE_SPEC_TAKE; - pc_next = address_dest; - } - else - { - branch_state = BRANCH_STATE_SPEC_NTAKE; - pc_next = address_src+2; // +1 = delay slot - } - break; - } - case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : // l.jr (rb!=9) - { - use_upt = true; - use_ras = true; - push = true; - direction = true; - pc_next = address_dest; - branch_state = BRANCH_STATE_SPEC_TAKE; - break; - } - case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : // l.jalr - { - use_upt = true; - use_ras = true; - push = true; - direction = true; - pc_next = address_dest; - branch_state = BRANCH_STATE_NSPEC_TAKE; - break; - } - case BRANCH_CONDITION_READ_STACK : // l.jr (rb==9) - { - use_upt = true; - use_ras = true; - push = false; - direction = true; - pc_next = PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i]); - branch_state = BRANCH_STATE_SPEC_TAKE; - break; - } - default : - { - ERRORMORPHEO(FUNCTION,"Unknow Condition"); - break; - } - } - - if (use_dir) - { - ack[context] &= dir_ack; - PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src); - PORT_WRITE(out_PREDICT_DIR_STATIC [i], address_dest_have_port_context_id) - PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID [i], context); - PORT_WRITE(out_PREDICT_RAS_PUSH [i], push); - PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); - - is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate - } - - if (use_upt) - { - ack[context] &= upt_ack; - - if (_param->_have_port_context_id) - PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID [i],context); - PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC [i],address_src); - PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest); - PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],condition); - PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE [i],direction); - PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE [i],is_accurate); -// PORT_WRITE(out_PREDICT_UPT_DIR_HISTORY [i],PORT_READ(in_PREDICT_DIR_HISTORY [i])); - PORT_WRITE(out_PREDICT_UPT_RAS_ADDRESS [i],PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i])); -// PORT_WRITE(out_PREDICT_UPT_RAS_INDEX [i],PORT_READ(in_PREDICT_RAS_INDEX [i])); - } - - // ack = 1 if : - // * btb_ack - // * use_dir and dir_ack - // * use_ras and ras_ack - // * use_upt and upt_ack -// ack [context] = (btb_ack and -// (use_dir and dir_ack) and -// (use_ras and ras_ack) and -// (use_upt and upt_ack)); - - dir_val = (btb_ack and - use_dir and -// use_ras and -// use_upt and -// (not use_dir or (use_dir and dir_ack)) and - (not use_ras or (use_ras and ras_ack)) and - (not use_upt or (use_upt and upt_ack))); - - ras_val = (btb_ack and -// use_dir and - use_ras and -// use_upt and - (not use_dir or (use_dir and dir_ack)) and -// (not use_ras or (use_ras and ras_ack)) and - (not use_upt or (use_upt and upt_ack))); - - upt_val = (btb_ack and -// use_dir and -// use_ras and - use_upt and - (not use_dir or (use_dir and dir_ack)) and - (not use_ras or (use_ras and ras_ack))// and -// (not use_upt or (use_upt and upt_ack)) - ); - -// pc_next - is previously computed -// branch_state - is previously computed - - Taddress_t address_src_lsb = address_src%_param->_nb_instruction [context]; - - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%x",address_src); + + Taddress_t address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); + Taddress_t address_src_lsb = address_src%_param->_nb_instruction [context]; + + inst_ifetch_ptr = address_src_lsb; + + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x (0x%.8x)",address_src,address_src<<2); log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src_lsb : %d",address_src_lsb); - if (address_src_lsb == (_param->_nb_instruction [context]-1)) + // Special case : + // * BTB hit and the branchement is the PC current and it's the last slot. + // -> next pc must be the delay slot + if ((not pc_current_is_ds_take) and // if pc_current is ds_take, alors pc_next is the destination of branchement + (address_src_lsb == (_param->_nb_instruction [context]-1))) { // branch is in the last slot of the packet log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * branch is in the last slot of the packet"); + // Branch is the last slot : next paquet is the delay slot + pc_next = address_src+1; // sequencial + pc_next_is_ds_take = 1; address_msb = _param->_nb_instruction [context]; // == (address_src_lsb+1) - pc_next_is_ds_take = 1; + branch_state = BRANCH_STATE_NONE; } else { + Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); + Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); + Tcontrol_t push ; + Tcontrol_t direction; + + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * condition : %s" ,toString(condition).c_str()); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x (0x%.8x)",address_src ,address_src <<2); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_dest : 0x%.8x (0x%.8x)",address_dest,address_dest<<2); + + switch (condition) + { + case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : // l.j + { + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK"); + + // use none unit (dir, upt and ras) + direction = true; + pc_next = address_dest; + branch_state = BRANCH_STATE_NSPEC_TAKE; + break; + } + case BRANCH_CONDITION_NONE_WITH_WRITE_STACK : // l.jal + { + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITH_WRITE_STACK"); + + use_upt = true; + use_ras = true; + push = true; + direction = true; + pc_next = address_dest; + branch_state = BRANCH_STATE_NSPEC_TAKE; + break; + } + case BRANCH_CONDITION_FLAG_UNSET : // l.bnf + case BRANCH_CONDITION_FLAG_SET : // l.bf + { + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_FLAG"); + + use_upt = true; + use_dir = true; + // Test direction + direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same + if (direction = 1) + { + branch_state = BRANCH_STATE_SPEC_TAKE; + pc_next = address_dest; + } + else + { + branch_state = BRANCH_STATE_SPEC_NTAKE; + pc_next = address_src+2; // +1 = delay slot + } + break; + } + case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : // l.jr (rb!=9) + { + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK"); + + use_upt = true; + use_ras = true; + push = true; + direction = true; + pc_next = address_dest; + branch_state = BRANCH_STATE_SPEC_TAKE; + break; + } + case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : // l.jalr + { + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK"); + + use_upt = true; + use_ras = true; + push = true; + direction = true; + pc_next = address_dest; + branch_state = BRANCH_STATE_NSPEC_TAKE; + break; + } + case BRANCH_CONDITION_READ_STACK : // l.jr (rb==9) + { + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_STACK"); + use_upt = true; + use_ras = true; + push = false; + direction = true; + pc_next = PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i]); + branch_state = BRANCH_STATE_SPEC_TAKE; + break; + } + default : + { + ERRORMORPHEO(FUNCTION,"Unknow Condition"); + break; + } + } + + if (use_dir) + { + ack[context] &= dir_ack; + PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src); + PORT_WRITE(out_PREDICT_DIR_STATIC [i], address_dest_have_port_context_id) + PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID [i], context); + PORT_WRITE(out_PREDICT_RAS_PUSH [i], push); + PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); + + is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate + } + + if (use_upt) + { + ack[context] &= upt_ack; + + if (_param->_have_port_context_id) + PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID [i],context); + PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC [i],address_src); + PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest); + PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],condition); + PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE [i],direction); + PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE [i],is_accurate); +// PORT_WRITE(out_PREDICT_UPT_DIR_HISTORY [i],PORT_READ(in_PREDICT_DIR_HISTORY [i])); + PORT_WRITE(out_PREDICT_UPT_RAS_ADDRESS [i],PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i])); +// PORT_WRITE(out_PREDICT_UPT_RAS_INDEX [i],PORT_READ(in_PREDICT_RAS_INDEX [i])); + } + + // ack = 1 if : + // * btb_ack + // * use_dir and dir_ack + // * use_ras and ras_ack + // * use_upt and upt_ack +// ack [context] = (btb_ack and +// (use_dir and dir_ack) and +// (use_ras and ras_ack) and +// (use_upt and upt_ack)); + + dir_val = (btb_ack and + use_dir and +// use_ras and +// use_upt and +// (not use_dir or (use_dir and dir_ack)) and + (not use_ras or (use_ras and ras_ack)) and + (not use_upt or (use_upt and upt_ack))); + + ras_val = (btb_ack and +// use_dir and + use_ras and +// use_upt and + (not use_dir or (use_dir and dir_ack)) and +// (not use_ras or (use_ras and ras_ack)) and + (not use_upt or (use_upt and upt_ack))); + + upt_val = (btb_ack and +// use_dir and +// use_ras and + use_upt and + (not use_dir or (use_dir and dir_ack)) and + (not use_ras or (use_ras and ras_ack))// and +// (not use_upt or (use_upt and upt_ack)) + ); + +// pc_next - is previously computed +// branch_state - is previously computed + + // branch is in the last slot of the packet address_msb = (address_src_lsb+2); // +1 == delayed slot pc_next_is_ds_take = 0; } - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_msb : %d",address_msb); - - inst_ifetch_ptr = address_src_lsb; + // branch_update_prediction_id = (_param->_have_port_depth)?((PORT_READ(in_DEPTH_UPT_TAIL[context])+PORT_READ(in_DEPTH_UPT_NB_BRANCH [context]))%_param->_array_size_depth[context]):0; } @@ -308,5 +340,6 @@ log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BTB miss : sequential order"); - pc_next = address-address_lsb+_param->_nb_instruction [context]; // sequencial + // Take the address packet base and add new packet + pc_next = pc_current-address_lsb+_param->_nb_instruction [context]; // sequencial pc_next_is_ds_take = 0; // no branch, also no delay slot inst_ifetch_ptr = 0; @@ -316,28 +349,35 @@ address_msb = _param->_nb_instruction [context]; } - - PORT_WRITE(out_PREDICT_PC_NEXT [context] , pc_next ); - PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE [context] , pc_next_is_ds_take ); - - Taddress_t address_limit_min = address_lsb; - Taddress_t address_limit_max = ((pc_current_is_ds_take)?(address_lsb+1):address_msb); - - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * instruction enable :"); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * nb_inst : %d",_param->_nb_instruction [context]); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0" ,address_limit_min); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_limit_min,address_limit_max); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0",address_limit_max,_param->_nb_instruction [context]); - - for (uint32_t j=0; j_nb_instruction [context]; j++) - PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // After last address (branch) : not valid - if (_param->_have_port_inst_ifetch_ptr) - PORT_WRITE(out_PREDICT_INST_IFETCH_PTR [context] , inst_ifetch_ptr ); - PORT_WRITE(out_PREDICT_BRANCH_STATE [context] , branch_state ); - if (_param->_have_port_depth) - PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context] , PORT_READ(in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID [i])); + + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_msb : %d",address_msb); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_next : 0x%.8x (0x%.8x)",pc_next,pc_next<<2); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_next_is_ds_take : %d" ,pc_next_is_ds_take); + + // Write Output + PORT_WRITE(out_PREDICT_PC_NEXT [context] , pc_next ); + PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE [context] , pc_next_is_ds_take ); + + // Create enable mask + Taddress_t address_limit_min = address_lsb; + Taddress_t address_limit_max = ((pc_current_is_ds_take)?(address_lsb+1):address_msb); + + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * instruction enable :"); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * nb_inst : %d",_param->_nb_instruction [context]); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0" ,address_limit_min); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_limit_min,address_limit_max); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0",address_limit_max,_param->_nb_instruction [context]); + + for (uint32_t j=0; j_nb_instruction [context]; j++) + PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // After last address (branch) : not valid + + if (_param->_have_port_inst_ifetch_ptr) + PORT_WRITE(out_PREDICT_INST_IFETCH_PTR [context] , inst_ifetch_ptr ); + PORT_WRITE(out_PREDICT_BRANCH_STATE [context] , branch_state ); + if (_param->_have_port_depth) + PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context] , PORT_READ(in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID [i])); } @@ -348,5 +388,6 @@ PORT_WRITE(out_PREDICT_UPT_VAL [i], upt_val); } - + + // Write output for (uint32_t i=0; i<_param->_nb_context; i++) PORT_WRITE(out_PREDICT_ACK[i],ack[i]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp (revision 100) @@ -125,5 +125,9 @@ // Initialisation - + const bool test1 = true; + const bool test2 = true; + const bool test3 = true; + const bool test4 = true; + const uint32_t seed = 0; //const uint32_t seed = static_cast(time(NULL)); @@ -144,275 +148,447 @@ { LABEL("Iteration %d",iteration); - - if (1) + + if (test1) { - uint32_t port = rand()%_param->_nb_inst_predict; - - LABEL("PREDICT - PUSH"); + uint32_t port = rand()%_param->_nb_inst_predict; + + LABEL("PREDICT - PUSH"); + + in_PREDICT_VAL [port]->write(1); + in_PREDICT_PUSH [port]->write(1); + + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]; j++) + { + in_PREDICT_CONTEXT_ID [port]->write(i); + in_PREDICT_ADDRESS_PUSH [port]->write(0xdeadbeef+j); + + SC_START(0); + + TEST(Tcontrol_t, out_PREDICT_ACK [port]->read(), 1); + TEST(Tptr_t , out_PREDICT_INDEX[port]->read(),(j+1)%_param->_size_queue[i]); + + SC_START(1); + + } + in_PREDICT_VAL [port]->write(0); + + SC_START(1); + + in_PREDICT_VAL [port]->write(1); + in_PREDICT_PUSH [port]->write(1); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]; j++) + { + in_PREDICT_CONTEXT_ID [port]->write(i); + in_PREDICT_ADDRESS_PUSH [port]->write(0x21071981+j); + + SC_START(0); + + TEST(Tcontrol_t, out_PREDICT_ACK [port]->read(), 1); + TEST(Tptr_t , out_PREDICT_INDEX [port]->read(),(j+1)%_param->_size_queue[i]); + TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port]->read(),0xdeadbeef+j); + + SC_START(1); + } + in_PREDICT_VAL [port]->write(0); + + LABEL("PREDICT - POP"); + + in_PREDICT_VAL [port]->write(1); + in_PREDICT_PUSH [port]->write(0); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j< _param->_size_queue[i]; j++) + { + in_PREDICT_CONTEXT_ID [port]->write(i); + in_PREDICT_ADDRESS_PUSH [port]->write(0xbabedead); + + SC_START(0); + + TEST(Tcontrol_t, out_PREDICT_ACK [port]->read(), 1); + TEST(Tcontrol_t, out_PREDICT_HIT [port]->read(), 1); + uint32_t k=(_param->_size_queue[i]-j)%_param->_size_queue[i]; + TEST(Tptr_t , out_PREDICT_INDEX [port]->read(), k); + TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port]->read(),(0x21071981+((k==0)?(_param->_size_queue[i]-1):(k-1)))); + + SC_START(1); + } + in_PREDICT_VAL [port]->write(0); + + // Now, the stack is empty + } + + if (test2) + { + uint32_t port = rand()%_param->_nb_inst_decod; + + LABEL("DECOD - without predict"); + + LABEL("DECOD - PUSH"); + + in_DECOD_VAL [port]->write(1); + in_DECOD_PUSH [port]->write(1); + in_DECOD_MISS_PREDICTION [port]->write(0); + + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]; j++) + { + in_DECOD_CONTEXT_ID [port]->write(i); + in_DECOD_ADDRESS_PUSH [port]->write(0xbeefcaca+j); + + SC_START(0); + + TEST(Tcontrol_t, out_DECOD_ACK [port]->read(), 1); + TEST(Tptr_t , out_DECOD_INDEX[port]->read(),(j+1)%_param->_size_queue[i]); + + SC_START(1); + + } + in_DECOD_VAL [port]->write(0); - in_PREDICT_VAL [port]->write(1); - in_PREDICT_PUSH [port]->write(1); - for (uint32_t i=0; i<_param->_nb_context; i++) - for (uint32_t j=0; j<_param->_size_queue[i]; j++) - { - in_PREDICT_CONTEXT_ID [port]->write(i); - in_PREDICT_ADDRESS_PUSH [port]->write(0xdeadbeef+j); - - SC_START(0); - - TEST(Tcontrol_t, out_PREDICT_ACK [port]->read(), 1); - TEST(Tptr_t , out_PREDICT_INDEX[port]->read(),(j+1)%_param->_size_queue[i]); - - SC_START(1); - - } - in_PREDICT_VAL [port]->write(0); - - SC_START(1); - - in_PREDICT_VAL [port]->write(1); - in_PREDICT_PUSH [port]->write(1); - for (uint32_t i=0; i<_param->_nb_context; i++) - for (uint32_t j=0; j<_param->_size_queue[i]; j++) - { - in_PREDICT_CONTEXT_ID [port]->write(i); - in_PREDICT_ADDRESS_PUSH [port]->write(0x21071981+j); - - SC_START(0); - - TEST(Tcontrol_t, out_PREDICT_ACK [port]->read(), 1); - TEST(Tptr_t , out_PREDICT_INDEX [port]->read(),(j+1)%_param->_size_queue[i]); - TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port]->read(),0xdeadbeef+j); - - SC_START(1); - } - in_PREDICT_VAL [port]->write(0); - - LABEL("PREDICT - POP"); - - in_PREDICT_VAL [port]->write(1); - in_PREDICT_PUSH [port]->write(0); - for (uint32_t i=0; i<_param->_nb_context; i++) - for (uint32_t j=0; j< _param->_size_queue[i]; j++) - { - in_PREDICT_CONTEXT_ID [port]->write(i); - in_PREDICT_ADDRESS_PUSH [port]->write(0xbabedead); - - SC_START(0); - - TEST(Tcontrol_t, out_PREDICT_ACK [port]->read(), 1); - TEST(Tcontrol_t, out_PREDICT_HIT [port]->read(), 1); - uint32_t k=(_param->_size_queue[i]-j)%_param->_size_queue[i]; - TEST(Tptr_t , out_PREDICT_INDEX [port]->read(), k); - TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port]->read(),(0x21071981+((k==0)?(_param->_size_queue[i]-1):(k-1)))); - - SC_START(1); - } - in_PREDICT_VAL [port]->write(0); - } - - // Now, the stack is empty - - if (1) - { - uint32_t port1 = rand()%_param->_nb_inst_decod; - uint32_t port2 = rand()%_param->_nb_inst_predict; - - LABEL("DECOD - without predict"); - - LABEL("DECOD - PUSH"); - - in_DECOD_VAL [port1]->write(1); - in_DECOD_PUSH [port1]->write(1); - in_DECOD_MISS_PREDICTION [port1]->write(0); - - for (uint32_t i=0; i<_param->_nb_context; i++) - for (uint32_t j=0; j<_param->_size_queue[i]; j++) - { - in_DECOD_CONTEXT_ID [port1]->write(i); - in_DECOD_ADDRESS_PUSH [port1]->write(0xbeefcaca+j); - - SC_START(0); - - TEST(Tcontrol_t, out_DECOD_ACK [port1]->read(), 1); - TEST(Tptr_t , out_DECOD_INDEX[port1]->read(),(j+1)%_param->_size_queue[i]); - - SC_START(1); - - } - in_DECOD_VAL [port1]->write(0); - - SC_START(1); - - in_DECOD_VAL [port1]->write(1); - in_DECOD_PUSH [port1]->write(1); - for (uint32_t i=0; i<_param->_nb_context; i++) - for (uint32_t j=0; j<_param->_size_queue[i]; j++) - { - in_DECOD_CONTEXT_ID [port1]->write(i); - in_DECOD_ADDRESS_PUSH [port1]->write(0x21071981+j); - - SC_START(0); - - TEST(Tcontrol_t, out_DECOD_ACK [port1]->read(), 1); - TEST(Tptr_t , out_DECOD_INDEX [port1]->read(),(j+1)%_param->_size_queue[i]); - TEST(Taddress_t, out_DECOD_ADDRESS_POP[port1]->read(),0xbeefcaca+j); - - SC_START(1); - } - in_DECOD_VAL [port1]->write(0); - - LABEL("DECOD - POP"); - - in_DECOD_VAL [port1]->write(1); - in_DECOD_PUSH [port1]->write(0); - for (uint32_t i=0; i<_param->_nb_context; i++) - for (uint32_t j=0; j< _param->_size_queue[i]; j++) - { - in_DECOD_CONTEXT_ID [port1]->write(i); - in_DECOD_ADDRESS_PUSH [port1]->write(0xbabedead); - - SC_START(0); - - TEST(Tcontrol_t, out_DECOD_ACK [port1]->read(), 1); - TEST(Tcontrol_t, out_DECOD_HIT [port1]->read(), 1); - uint32_t k=(_param->_size_queue[i]-j)%_param->_size_queue[i]; - TEST(Tptr_t , out_DECOD_INDEX [port1]->read(), k); - TEST(Taddress_t, out_DECOD_ADDRESS_POP[port1]->read(),(0x21071981+((k==0)?(_param->_size_queue[i]-1):(k-1)))); - - SC_START(1); - } - in_DECOD_VAL [port1]->write(0); - - LABEL("DECOD - with predict"); - - LABEL("DECOD - PUSH (size_queue/2)"); - - in_DECOD_VAL [port1]->write(1); - in_DECOD_PUSH [port1]->write(1); - in_DECOD_MISS_PREDICTION [port1]->write(1); - - for (uint32_t i=0; i<_param->_nb_context; i++) - for (uint32_t j=0; j<_param->_size_queue[i]/2;j++) - { - in_DECOD_CONTEXT_ID [port1]->write(i); - in_DECOD_ADDRESS_PUSH [port1]->write(0x01234567+j); - - SC_START(0); - - TEST(Tcontrol_t, out_DECOD_ACK [port1]->read(), 1); - TEST(Tptr_t , out_DECOD_INDEX[port1]->read(),(j+1)%_param->_size_queue[i]); - - SC_START(1); - - } - in_DECOD_VAL [port1]->write(0); - - LABEL("PREDICT - PUSH (size_queue/2)"); - - in_PREDICT_VAL [port2]->write(1); - in_PREDICT_PUSH [port2]->write(1); - - for (uint32_t i=0; i<_param->_nb_context; i++) - for (uint32_t j=0; j<_param->_size_queue[i]/2;j++) - { - in_PREDICT_CONTEXT_ID [port2]->write(i); - in_PREDICT_ADDRESS_PUSH [port2]->write((0x89abcdef+j)+(_param->_size_queue[i]/2)); - - SC_START(0); - - TEST(Tcontrol_t, out_PREDICT_ACK [port2]->read(), 1); - TEST(Tptr_t , out_PREDICT_INDEX[port2]->read(),(j+1+(_param->_size_queue[i]/2))%_param->_size_queue[i]); - - SC_START(1); - } - - in_PREDICT_VAL [port2]->write(0); - - LABEL("PREDICT - POP (size_queue/2)"); - - in_PREDICT_VAL [port2]->write(1); - in_PREDICT_PUSH [port2]->write(0); - for (uint32_t i=0; i<_param->_nb_context; i++) - { - for (uint32_t j=0; j< _param->_size_queue[i]/2; j++) - { - in_PREDICT_CONTEXT_ID [port2]->write(i); - in_PREDICT_ADDRESS_PUSH [port2]->write(0xbabedead); - - SC_START(0); - - TEST(Tcontrol_t, out_PREDICT_ACK [port2]->read(), 1); - TEST(Tcontrol_t, out_PREDICT_HIT [port2]->read(), 1); - uint32_t k= (_param->_size_queue[i]-j)%_param->_size_queue[i]; - TEST(Tptr_t , out_PREDICT_INDEX [port2]->read(), k); - - Taddress_t res = (0x89abcdef+((k==0)?(_param->_size_queue[i]-1):(k-1))); - LABEL("k : %d",k); - LABEL("res : %x",res); - LABEL("@_pop : %x",out_PREDICT_ADDRESS_POP[port2]->read()); - - TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port2]->read(),res); - - SC_START(1); - } - - for (uint32_t j=0; j< _param->_size_queue[i]/2; j++) - { - in_PREDICT_CONTEXT_ID [port2]->write(i); - in_PREDICT_ADDRESS_PUSH [port2]->write(0xbabedead); - - SC_START(0); - - TEST(Tcontrol_t, out_PREDICT_ACK [port2]->read(), 1); - TEST(Tcontrol_t, out_PREDICT_HIT [port2]->read(), 1); - uint32_t k=(_param->_size_queue[i]/2-j)%_param->_size_queue[i]; - TEST(Tptr_t , out_PREDICT_INDEX [port2]->read(), k); - - Taddress_t res = (0x01234567+((k==0)?(_param->_size_queue[i]/2-1):(k-1))); - - LABEL("k : %d",k); - LABEL("res : %x",res); - LABEL("@_pop : %x",out_PREDICT_ADDRESS_POP[port2]->read()); - - TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port2]->read(),res); - - SC_START(1); - } - } - - in_PREDICT_VAL [port2]->write(0); - - in_DECOD_VAL [port1]->write(1); - in_DECOD_PUSH [port1]->write(0); - in_DECOD_MISS_PREDICTION [port1]->write(0); - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - for (uint32_t j=0; j< _param->_size_queue[i]/2; j++) - { - in_DECOD_CONTEXT_ID [port1]->write(i); - in_DECOD_ADDRESS_PUSH [port1]->write(0xbabedead); - - SC_START(0); - - TEST(Tcontrol_t, out_DECOD_ACK [port1]->read(), 1); - TEST(Tcontrol_t, out_DECOD_HIT [port1]->read(), 1); - uint32_t k=(_param->_size_queue[i]/2-j)%_param->_size_queue[i]; - TEST(Tptr_t , out_DECOD_INDEX [port1]->read(), k); - - Taddress_t res = (0x01234567+((k==0)?(_param->_size_queue[i]/2-1):(k-1))); - - LABEL("k : %d",k); - LABEL("res : %x",res); - LABEL("@_pop : %x",out_DECOD_ADDRESS_POP[port1]->read()); - - TEST(Taddress_t, out_DECOD_ADDRESS_POP[port1]->read(),res); - - SC_START(1); - } - } - - in_DECOD_VAL [port1]->write(0); + SC_START(1); + + in_DECOD_VAL [port]->write(1); + in_DECOD_PUSH [port]->write(1); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]; j++) + { + in_DECOD_CONTEXT_ID [port]->write(i); + in_DECOD_ADDRESS_PUSH [port]->write(0x21071981+j); + + SC_START(0); + + TEST(Tcontrol_t, out_DECOD_ACK [port]->read(), 1); + TEST(Tptr_t , out_DECOD_INDEX [port]->read(),(j+1)%_param->_size_queue[i]); + TEST(Taddress_t, out_DECOD_ADDRESS_POP[port]->read(),0xbeefcaca+j); + + SC_START(1); + } + in_DECOD_VAL [port]->write(0); + + LABEL("DECOD - POP"); + + in_DECOD_VAL [port]->write(1); + in_DECOD_PUSH [port]->write(0); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j< _param->_size_queue[i]; j++) + { + in_DECOD_CONTEXT_ID [port]->write(i); + in_DECOD_ADDRESS_PUSH [port]->write(0xbabedead); + + SC_START(0); + + TEST(Tcontrol_t, out_DECOD_ACK [port]->read(), 1); + TEST(Tcontrol_t, out_DECOD_HIT [port]->read(), 1); + uint32_t k=(_param->_size_queue[i]-j)%_param->_size_queue[i]; + TEST(Tptr_t , out_DECOD_INDEX [port]->read(), k); + TEST(Taddress_t, out_DECOD_ADDRESS_POP[port]->read(),(0x21071981+((k==0)?(_param->_size_queue[i]-1):(k-1)))); + + SC_START(1); + } + in_DECOD_VAL [port]->write(0); + // Now, the stack is empty + } + + if (test3) + { + uint32_t port1 = rand()%_param->_nb_inst_predict; + uint32_t port2 = rand()%_param->_nb_inst_decod; + uint32_t port3 = rand()%_param->_nb_inst_update; + + LABEL("Test UPDATE"); + + LABEL("Predict"); + in_PREDICT_VAL [port1]->write(1); + in_PREDICT_PUSH [port1]->write(1); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]; j++) + { + in_PREDICT_CONTEXT_ID [port1]->write(i); + in_PREDICT_ADDRESS_PUSH [port1]->write(0x25071959+j); + + SC_START(0); + + TEST(Tcontrol_t, out_PREDICT_ACK [port1]->read(), 1); + TEST(Tptr_t , out_PREDICT_INDEX [port1]->read(),(j+1)%_param->_size_queue[i]); +// TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port1]->read(),0xdeadbeef+j); + + SC_START(1); + } + in_PREDICT_VAL [port1]->write(0); + + LABEL("Decod"); + in_DECOD_VAL [port2]->write(1); + in_DECOD_PUSH [port2]->write(1); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) + { + in_DECOD_CONTEXT_ID [port2]->write(i); + in_DECOD_ADDRESS_PUSH [port2]->write(0x25071959+j); + in_DECOD_MISS_PREDICTION [port2]->write(0); + + SC_START(0); + + TEST(Tcontrol_t, out_DECOD_ACK [port2]->read(), 1); + TEST(Tptr_t , out_DECOD_INDEX [port2]->read(),(j+1)%_param->_size_queue[i]); + TEST(Taddress_t, out_DECOD_ADDRESS_POP[port2]->read(),0x25071959+j); + + SC_START(1); + } + in_DECOD_VAL [port2]->write(0); + + LABEL("Update Decod OK"); + in_UPDATE_VAL [port3]->write(1); + in_UPDATE_PUSH [port3]->write(1); + in_UPDATE_FLUSH[port3]->write(0); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) + { + uint32_t x=(_param->_size_queue[i]/2)-1; + in_UPDATE_CONTEXT_ID [port3]->write(i); + in_UPDATE_MISS_PREDICTION [port3]->write(0); + in_UPDATE_PREDICTION_IFETCH [port3]->write(0); + in_UPDATE_INDEX [port3]->write((x+1)%_param->_size_queue[i]); + in_UPDATE_ADDRESS [port3]->write(0x25071959+x); + + SC_START(0); + + TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); + + SC_START(1); + } + in_UPDATE_VAL [port3]->write(0); + + LABEL("Update FLUSH"); + in_UPDATE_VAL [port3]->write(1); + in_UPDATE_FLUSH[port3]->write(1); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) + { + in_UPDATE_CONTEXT_ID [port3]->write(i); + SC_START(1); + TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); + } + in_UPDATE_VAL [port3]->write(0); + + +// Tcontrol_t, in_UPDATE_VAL +// Tcontrol_t,out_UPDATE_ACK +// Tcontext_t, in_UPDATE_CONTEXT_ID +// Tcontrol_t, in_UPDATE_PUSH +// Tcontrol_t, in_UPDATE_FLUSH +// Tptr_t , in_UPDATE_INDEX +// Taddress_t, in_UPDATE_ADDRESS +// Tcontrol_t, in_UPDATE_MISS_PREDICTION +// Tcontrol_t, in_UPDATE_PREDICTION_IFETCH + + + } + + if (test4) + { + uint32_t port1 = rand()%_param->_nb_inst_predict; + uint32_t port2 = rand()%_param->_nb_inst_decod; + uint32_t port3 = rand()%_param->_nb_inst_update; + + LABEL("Test UPDATE"); + + LABEL("Predict"); + in_PREDICT_VAL [port1]->write(1); + in_PREDICT_PUSH [port1]->write(1); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]; j++) + { + in_PREDICT_CONTEXT_ID [port1]->write(i); + in_PREDICT_ADDRESS_PUSH [port1]->write(0x14011959+j); + + SC_START(0); + + TEST(Tcontrol_t, out_PREDICT_ACK [port1]->read(), 1); + TEST(Tptr_t , out_PREDICT_INDEX [port1]->read(),(j+1)%_param->_size_queue[i]); +// TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port1]->read(),0xdeadbeef+j); + + SC_START(1); + } + in_PREDICT_VAL [port1]->write(0); + + LABEL("Decod"); + in_DECOD_VAL [port2]->write(1); + in_DECOD_PUSH [port2]->write(1); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) + { + in_DECOD_CONTEXT_ID [port2]->write(i); + in_DECOD_ADDRESS_PUSH [port2]->write(0x14011959+j); + in_DECOD_MISS_PREDICTION [port2]->write(0); + + SC_START(0); + + TEST(Tcontrol_t, out_DECOD_ACK [port2]->read(), 1); + TEST(Tptr_t , out_DECOD_INDEX [port2]->read(),(j+1)%_param->_size_queue[i]); + TEST(Taddress_t, out_DECOD_ADDRESS_POP[port2]->read(),0x14011959+j); + + SC_START(1); + } + in_DECOD_VAL [port2]->write(0); + + LABEL("Update Decod KO"); + in_UPDATE_VAL [port3]->write(1); + in_UPDATE_PUSH [port3]->write(1); + in_UPDATE_FLUSH[port3]->write(0); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) + { + uint32_t x=(_param->_size_queue[i]/2); + in_UPDATE_CONTEXT_ID [port3]->write(i); + in_UPDATE_MISS_PREDICTION [port3]->write(1); + in_UPDATE_PREDICTION_IFETCH [port3]->write(0); + in_UPDATE_INDEX [port3]->write((x-j)%_param->_size_queue[i]); + in_UPDATE_ADDRESS [port3]->write(0xffffffff+x); + + SC_START(0); + + TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); + + SC_START(1); + } + in_UPDATE_VAL [port3]->write(0); + + LABEL("Decod"); + in_DECOD_VAL [port2]->write(1); + in_DECOD_PUSH [port2]->write(1); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) + { + in_DECOD_CONTEXT_ID [port2]->write(i); + in_DECOD_ADDRESS_PUSH [port2]->write(0x14011959+j); + in_DECOD_MISS_PREDICTION [port2]->write(0); + + SC_START(0); + + TEST(Tcontrol_t, out_DECOD_ACK [port2]->read(), 1); + TEST(Tptr_t , out_DECOD_INDEX [port2]->read(),(j+1)%_param->_size_queue[i]); + TEST(Taddress_t, out_DECOD_ADDRESS_POP[port2]->read(),0x14011959+j); + + SC_START(1); + } + in_DECOD_VAL [port2]->write(0); + + + LABEL("Update Decod KO"); + in_UPDATE_VAL [port3]->write(1); + in_UPDATE_PUSH [port3]->write(1); + in_UPDATE_FLUSH[port3]->write(0); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) + { + uint32_t x=(_param->_size_queue[i]/2); + in_UPDATE_CONTEXT_ID [port3]->write(i); + in_UPDATE_MISS_PREDICTION [port3]->write(1); + in_UPDATE_PREDICTION_IFETCH [port3]->write(0); + in_UPDATE_INDEX [port3]->write((x-j)%_param->_size_queue[i]); + in_UPDATE_ADDRESS [port3]->write(0xffffffff+x); + + SC_START(0); + + TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); + + SC_START(1); + } + in_UPDATE_VAL [port3]->write(0); + + LABEL("Update Predict KO"); + in_UPDATE_VAL [port3]->write(1); + in_UPDATE_PUSH [port3]->write(1); + in_UPDATE_FLUSH[port3]->write(0); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]; j++) + { + uint32_t x=(_param->_size_queue[i]); + in_UPDATE_CONTEXT_ID [port3]->write(i); + in_UPDATE_MISS_PREDICTION [port3]->write(1); + in_UPDATE_PREDICTION_IFETCH [port3]->write(1); + in_UPDATE_INDEX [port3]->write((x-j)%_param->_size_queue[i]); + in_UPDATE_ADDRESS [port3]->write(0xffffffff+x); + + SC_START(0); + + TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); + + SC_START(1); + } + in_UPDATE_VAL [port3]->write(0); + + LABEL("Predict"); + in_PREDICT_VAL [port1]->write(1); + in_PREDICT_PUSH [port1]->write(1); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]; j++) + { + in_PREDICT_CONTEXT_ID [port1]->write(i); + in_PREDICT_ADDRESS_PUSH [port1]->write(0x14011959+j); + + SC_START(0); + + TEST(Tcontrol_t, out_PREDICT_ACK [port1]->read(), 1); + TEST(Tptr_t , out_PREDICT_INDEX [port1]->read(),(j+1)%_param->_size_queue[i]); + TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port1]->read(),0x14011959+j); + + SC_START(1); + } + in_PREDICT_VAL [port1]->write(0); + + LABEL("Update Predict KO"); + in_UPDATE_VAL [port3]->write(1); + in_UPDATE_PUSH [port3]->write(0); + in_UPDATE_FLUSH[port3]->write(0); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]; j++) + { + uint32_t x=(_param->_size_queue[i]); + in_UPDATE_CONTEXT_ID [port3]->write(i); + in_UPDATE_MISS_PREDICTION [port3]->write(1); + in_UPDATE_PREDICTION_IFETCH [port3]->write(1); + in_UPDATE_INDEX [port3]->write((x+j+1)%_param->_size_queue[i]); + in_UPDATE_ADDRESS [port3]->write(0x87654321+j); + + SC_START(0); + + TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); + + SC_START(1); + } + in_UPDATE_VAL [port3]->write(0); + + LABEL("Predict"); + in_PREDICT_VAL [port1]->write(1); + in_PREDICT_PUSH [port1]->write(1); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]; j++) + { + in_PREDICT_CONTEXT_ID [port1]->write(i); + in_PREDICT_ADDRESS_PUSH [port1]->write(0x14011959+j); + + SC_START(0); + + TEST(Tcontrol_t, out_PREDICT_ACK [port1]->read(), 1); + TEST(Tptr_t , out_PREDICT_INDEX [port1]->read(),(j+1)%_param->_size_queue[i]); + TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port1]->read(),0x87654321+j); + + SC_START(1); + } + in_PREDICT_VAL [port1]->write(0); + + LABEL("Update FLUSH"); + in_UPDATE_VAL [port3]->write(1); + in_UPDATE_FLUSH[port3]->write(1); + for (uint32_t i=0; i<_param->_nb_context; i++) + for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) + { + in_UPDATE_CONTEXT_ID [port3]->write(i); + SC_START(1); + TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); + } + in_UPDATE_VAL [port3]->write(0); } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h (revision 100) @@ -88,5 +88,5 @@ public : SC_IN (Tcontext_t) ** in_UPDATE_CONTEXT_ID ; //[nb_inst_update] public : SC_IN (Tcontrol_t) ** in_UPDATE_PUSH ; //[nb_inst_update] 1 = push, else pop - public : SC_IN (Tcontrol_t) ** in_UPDATE_FLUSH ; //[nb_inst_update] 1 = push, else pop + public : SC_IN (Tcontrol_t) ** in_UPDATE_FLUSH ; //[nb_inst_update] public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ; //[nb_inst_update] public : SC_IN (Tptr_t ) ** in_UPDATE_INDEX ; //[nb_inst_update] @@ -99,8 +99,8 @@ private : ras_entry_t ** reg_stack ; //[nb_context][size_queue] private : Tptr_t * reg_TOP ; //[nb_context] - private : Tptr_t * reg_BOTTOM ; //[nb_context] +//private : Tptr_t * reg_BOTTOM ; //[nb_context] private : Tptr_t * reg_NB_ELT ; //[nb_context] private : Tptr_t * reg_PREDICT_TOP ; //[nb_context] - private : Tptr_t * reg_PREDICT_BOTTOM; //[nb_context] +//private : Tptr_t * reg_PREDICT_BOTTOM; //[nb_context] private : Tptr_t * reg_PREDICT_NB_ELT; //[nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Types.h (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Types.h (revision 100) @@ -21,7 +21,7 @@ class ras_entry_t { - public : bool _val ; - public : bool _predict; - public : bool _miss ; +//public : bool _val ; +//public : bool _predict; +//public : bool _miss ; public : Taddress_t _address; }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp (revision 100) @@ -107,9 +107,9 @@ reg_TOP = new Tptr_t [_param->_nb_context]; - reg_BOTTOM = new Tptr_t [_param->_nb_context]; +// reg_BOTTOM = new Tptr_t [_param->_nb_context]; reg_NB_ELT = new Tptr_t [_param->_nb_context]; reg_PREDICT_TOP = new Tptr_t [_param->_nb_context]; - reg_PREDICT_BOTTOM = new Tptr_t [_param->_nb_context]; +// reg_PREDICT_BOTTOM = new Tptr_t [_param->_nb_context]; reg_PREDICT_NB_ELT = new Tptr_t [_param->_nb_context]; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp (revision 100) @@ -64,8 +64,8 @@ delete [] reg_stack; delete [] reg_TOP; - delete [] reg_BOTTOM; +// delete [] reg_BOTTOM; delete [] reg_NB_ELT; delete [] reg_PREDICT_TOP; - delete [] reg_PREDICT_BOTTOM; +// delete [] reg_PREDICT_BOTTOM; delete [] reg_PREDICT_NB_ELT; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_decod.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_decod.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_decod.cpp (revision 100) @@ -22,7 +22,9 @@ void Return_Address_Stack::genMealy_decod (void) { - log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); + log_begin(Return_Address_Stack,FUNCTION); + log_function(Return_Address_Stack,FUNCTION,_name.c_str()); #ifdef DEBUG_TEST + // just to test if have many transaction on a same context bool context_valid [_param->_nb_context]; for (uint32_t i=0; i<_param->_nb_context; i++) @@ -32,4 +34,5 @@ for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { + // Read context number Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; @@ -49,5 +52,5 @@ // if pop : val and not miss // when the predictor : if hit = 0, wait (is not accurate) - internal_DECOD_HIT [i] = (push or (reg_stack[context][top]._val and not reg_stack[context][top]._miss and (reg_NB_ELT[context]>0))); + internal_DECOD_HIT [i] = (push or (reg_NB_ELT[context]>0)); PORT_WRITE(out_DECOD_HIT [i], internal_DECOD_HIT [i]); @@ -61,5 +64,5 @@ } - log_printf(FUNC,Return_Address_Stack,FUNCTION,"End"); + log_end(Return_Address_Stack,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_predict.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_predict.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_predict.cpp (revision 100) @@ -22,7 +22,9 @@ void Return_Address_Stack::genMealy_predict (void) { - log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); + log_begin(Return_Address_Stack,FUNCTION); + log_function(Return_Address_Stack,FUNCTION,_name.c_str()); #ifdef DEBUG_TEST + // just to test if have many transaction on a same context bool context_valid [_param->_nb_context]; for (uint32_t i=0; i<_param->_nb_context; i++) @@ -32,6 +34,7 @@ for (uint32_t i=0; i<_param->_nb_inst_predict; i++) { + // Read context number Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; - + #ifdef DEBUG_TEST if (PORT_READ(in_PREDICT_VAL [i])) @@ -42,15 +45,18 @@ } #endif - + + // Get top Tptr_t top = reg_PREDICT_TOP[context]; Tcontrol_t push = PORT_READ(in_PREDICT_PUSH [i]); - // if push : value is hit - // if pop : val and not miss - internal_PREDICT_HIT [i] = (push or (reg_stack[context][top]._val and not reg_stack[context][top]._miss and (reg_PREDICT_NB_ELT[context]>0))); + // Hit : + // * if push : value is hit + // * if pop : no empty + internal_PREDICT_HIT [i] = (push or (reg_PREDICT_NB_ELT[context]>0)); + PORT_WRITE(out_PREDICT_HIT [i], internal_PREDICT_HIT [i]); // if pop : address_pop = stack [top] - // if push : stock [top+1] = address_push; also stock [top+1] is erase ! give the old value at the update table + // if push : stock [top+1] = address_push; also stack [top+1] is erase ! save the old value in the update table if (push) top = (top+1)%_param->_size_queue[context]; @@ -60,5 +66,5 @@ } - log_printf(FUNC,Return_Address_Stack,FUNCTION,"End"); + log_end(Return_Address_Stack,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp (revision 100) @@ -22,24 +22,19 @@ void Return_Address_Stack::transition (void) { - log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); + log_begin(Return_Address_Stack,FUNCTION); + log_function(Return_Address_Stack,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET)==0) { + // Reset all structure for (uint32_t i=0; i<_param->_nb_context; i++) { reg_TOP [i] = 0; - reg_BOTTOM [i] = 0; +// reg_BOTTOM [i] = 0; reg_NB_ELT [i] = 0; reg_PREDICT_TOP [i] = 0; - reg_PREDICT_BOTTOM [i] = 0; +// reg_PREDICT_BOTTOM [i] = 0; reg_PREDICT_NB_ELT [i] = 0; - - for (uint32_t j=0; j<_param->_size_queue [i]; j++) - { - reg_stack[i][j]._val = false; - reg_stack[i][j]._predict = false; - reg_stack[i][j]._miss = false; - } } } @@ -52,67 +47,76 @@ if (PORT_READ(in_PREDICT_VAL [i]) and internal_PREDICT_ACK [i]) { - log_printf(TRACE,Return_Address_Stack,FUNCTION,"PREDICT[%d] : Transaction",i); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * PREDICT [%d] : Transaction",i); + + // Read information and pointer Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; Tcontrol_t push = PORT_READ(in_PREDICT_PUSH [i]); + Tptr_t top_old = reg_PREDICT_TOP [context]; Tptr_t top_new = top_old; - Tptr_t bottom_old = reg_PREDICT_BOTTOM [context]; - - log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); - - // Hit : push or (val and not miss and not empty) +// Tptr_t bottom_old = reg_PREDICT_BOTTOM [context]; +// Tptr_t bottom_new = bottom_old; + Tptr_t nb_elt_old = reg_PREDICT_NB_ELT [context]; + Tptr_t nb_elt_new = nb_elt_old; + + log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); + + // Hit : push or not empty // Miss : ifetch is stall, no update + + // Test if hit if (internal_PREDICT_HIT [i]) { - log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); - log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",reg_PREDICT_TOP [context]); - log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",reg_PREDICT_BOTTOM [context]); - log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",reg_PREDICT_NB_ELT [context]); - + log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_old); +// log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_old); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_old); + + // Test if push if (push) { + log_printf(TRACE,Return_Address_Stack,FUNCTION," * push (call procedure)"); + // push : increase the top (circular) top_new = (top_old+1)%_param->_size_queue[context]; - - reg_stack [context][top_new]._val = true; // New addr - reg_stack [context][top_new]._predict = true; // Is speculative (erase a old addr (or not)) - //reg_stack [context][top_new]._miss = ; + + // Write new value in Queue reg_stack [context][top_new]._address = PORT_READ(in_PREDICT_ADDRESS_PUSH [i]); - // the stack is full, erase the most old stack - // Test if full - if (reg_PREDICT_NB_ELT[context]==_param->_size_queue[context]) - reg_PREDICT_BOTTOM [context] = (bottom_old+1)%_param->_size_queue[context]; - // A new data is write : the stack is not empty - if (reg_PREDICT_NB_ELT[context]< _param->_size_queue[context]) - reg_PREDICT_NB_ELT[context]++; + // -> is full, the push erase the oldest value in stack, also nb_elt is the same + // -> is not full, increase nb_elt +// if (nb_elt_old==_param->_size_queue[context]) +// bottom_new = (bottom_old+1)%_param->_size_queue[context]; +// else +// nb_elt_new ++; + if (nb_elt_old!=_param->_size_queue[context]) + nb_elt_new ++; } else { // pop -// top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); - - //reg_stack [context][top_new]._val = ; - //reg_stack [context][top_new]._predict = ; - //reg_stack [context][top_new]._miss = ; - //reg_stack [context][top_new]._address = ; - - // the stack is empty - if (reg_PREDICT_NB_ELT[context]>0) + log_printf(TRACE,Return_Address_Stack,FUNCTION," * pop (return procedure)"); + + // Test if the stack is empty + if (nb_elt_old>0) { top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); - reg_PREDICT_NB_ELT[context] --; + nb_elt_new --; } + // no else : can't pop } - reg_PREDICT_TOP [context] = top_new; - - log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); - log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",reg_PREDICT_TOP [context]); - log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",reg_PREDICT_BOTTOM [context]); - log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",reg_PREDICT_NB_ELT [context]); - } - } + // Write new pointer + reg_PREDICT_TOP [context] = top_new; +// reg_PREDICT_BOTTOM [context] = bottom_new; + reg_PREDICT_NB_ELT [context] = nb_elt_new; + + log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_new); +// log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_new); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_new); + } + } // =================================================================== @@ -122,81 +126,96 @@ if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i]) { - log_printf(TRACE,Return_Address_Stack,FUNCTION,"DECOD[%d] : Transaction",i); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * DECOD [%d] : Transaction",i); + + // Read information Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; Tcontrol_t push = PORT_READ(in_DECOD_PUSH [i]); + + // Read pointer Tptr_t top_old = reg_TOP [context]; Tptr_t top_new = top_old; - Tptr_t bottom_old = reg_BOTTOM [context]; - //Tcontrol_t hit = internal_DECOD_HIT [i]; - Tcontrol_t miss = PORT_READ(in_DECOD_MISS_PREDICTION [i]); - - log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); - - log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); - log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",reg_TOP [context]); - log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",reg_BOTTOM [context]); - log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",reg_NB_ELT [context]); - - if (push) - { - // push : increase the top (circular) - top_new = (top_old+1)%_param->_size_queue[context]; - - reg_stack [context][top_new]._val = true; // New address - reg_stack [context][top_new]._predict = false; // No speculative - reg_stack [context][top_new]._miss = false; - reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]); - - // Test if full : if true, then icrease the bottom (erase the most old stack) - if (reg_NB_ELT[context]==_param->_size_queue[context]) - reg_BOTTOM [context] = (bottom_old+1)%_param->_size_queue[context]; - // A new data is write : the stack is not empty - if (reg_NB_ELT[context]< _param->_size_queue[context]) - reg_NB_ELT[context]++; - } - else - { - // pop -// top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); - - //reg_stack [context][top_new]._val = ; - //reg_stack [context][top_new]._predict = ; - //reg_stack [context][top_new]._miss = ; - //reg_stack [context][top_new]._address = ; - - // the stack is empty - if (reg_NB_ELT[context]>0) - { - top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); - reg_NB_ELT[context] --; - } - } - - reg_TOP [context] = top_new; - - log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); - log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",reg_TOP [context]); - log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",reg_BOTTOM [context]); - log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",reg_NB_ELT [context]); - +// Tptr_t bottom_old = reg_BOTTOM [context]; +// Tptr_t bottom_new = bottom_old; + Tptr_t nb_elt_old = reg_NB_ELT [context]; + Tptr_t nb_elt_new = nb_elt_old; + + log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); + + log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_old); +// log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_old); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_old); + + // Test if push + if (push) + { + log_printf(TRACE,Return_Address_Stack,FUNCTION," * push (call procedure)"); + + // push : increase the top (circular) + top_new = (top_old+1)%_param->_size_queue[context]; + + // Write new value in Queue + reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]); + + // Test if full + // -> is full, the push erase the oldest value in stack, also nb_elt is the same + // -> is not full, increase nb_elt +// if (nb_elt_old==_param->_size_queue[context]) +// bottom_new = (bottom_old+1)%_param->_size_queue[context]; +// else +// nb_elt_new ++; + if (nb_elt_old!=_param->_size_queue[context]) + nb_elt_new ++; + } + else + { + // pop + log_printf(TRACE,Return_Address_Stack,FUNCTION," * pop (return procedure)"); + + // Test if the stack is empty + if (nb_elt_old>0) + { + top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); + nb_elt_new --; + } + // no else : can't pop + } + + // Write new pointer + reg_TOP [context] = top_new; +// reg_BOTTOM [context] = bottom_new; + reg_NB_ELT [context] = nb_elt_new; + + log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_new); +// log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_new); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_new); + // have previous miss of ifetch ? // 2 miss : // 1) miss predict : is very limited (local at context), can be update very quickly // 2) miss decod : result is in commit stage ... - if (miss) - { - reg_PREDICT_BOTTOM [context] = reg_BOTTOM [context]; - reg_PREDICT_TOP [context] = reg_TOP [context]; - reg_PREDICT_NB_ELT [context] = reg_NB_ELT [context]; + + // manage by Update_Fetch_Prediction_Table and Update_Prediction_Table + // Note : + // if decod miss : ifetch can have predict call and return branchement. Also, the head of decod can be false + +// Tcontrol_t miss = PORT_READ(in_DECOD_MISS_PREDICTION [i]); + +// if (miss) +// { +// reg_PREDICT_BOTTOM [context] = reg_BOTTOM [context]; +// reg_PREDICT_TOP [context] = reg_TOP [context]; +// reg_PREDICT_NB_ELT [context] = reg_NB_ELT [context]; - // Scan full assoc !!! - for (uint32_t j=0; j<_param->_size_queue [context]; j++) - // Test if this slot is tagged with "predict" : if true, tagged as miss - if (reg_stack [context][j]._predict) - { - reg_stack [context][j]._predict = false; - reg_stack [context][j]._miss = true; - } - } +// // Scan full assoc !!! +// for (uint32_t j=0; j<_param->_size_queue [context]; j++) +// // Test if this slot is tagged with "predict" : if true, tagged as miss +// if (reg_stack [context][j]._predict) +// { +// reg_stack [context][j]._predict = false; +// reg_stack [context][j]._miss = true; +// } +// } } @@ -207,42 +226,160 @@ if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) { - throw ERRORMORPHEO(FUNCTION,"Fonction à implémenter !!!!!!!!!!!!"); - - -// Tcontrol_t miss = PORT_READ(in_UPDATE_MISS_PREDICTION [i]); -// // -// if (miss) -// { -// Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; -// Tcontrol_t ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); -// Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); -// Tcontrol_t flush = PORT_READ(in_UPDATE_FLUSH [i]); -// Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); -// Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); - -// if (push) -// { -// // // push -// // top_new = (top_old+1)%_param->_size_queue[context]; - -// // reg_stack [context][index]._val = true; -// // reg_stack [context][index]._predict = false; -// // reg_stack [context][index]._miss = false; -// // reg_stack [context][index]._address = PORT_READ(in_UPDATE_ADDRESS [i]); - -// } -// else -// { -// // //reg_stack [context][top_new]._val = ; -// // //reg_stack [context][top_new]._predict = ; -// // //reg_stack [context][top_new]._miss = ; -// // //reg_stack [context][top_new]._address = ; -// } - -// // // // Mouais bof ....... -// // // reg_PREDICT_TOP [context] = index; -// } + log_printf(TRACE,Return_Address_Stack,FUNCTION," * UPDATE [%d] : Transaction",i); + + Tcontext_t context_id = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; + Tcontrol_t flush = PORT_READ(in_UPDATE_FLUSH [i]); + + log_printf(TRACE,Return_Address_Stack,FUNCTION," * context_id : %d",context_id); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * flush : %d",flush ); + + // An miss prediction on call/return = Return Address Stack is corrupted. + if (flush) + { + // All pointer is set at 0 + reg_TOP [context_id] = 0; +// reg_BOTTOM [context_id] = 0; + reg_NB_ELT [context_id] = 0; + + reg_PREDICT_TOP [context_id] = 0; +// reg_PREDICT_BOTTOM [context_id] = 0; + reg_PREDICT_NB_ELT [context_id] = 0; + } + else + { + // if miss_prediction -> restore queue + // else, the prediction is correct + Tcontrol_t miss_prediction = PORT_READ(in_UPDATE_MISS_PREDICTION [i]); + + log_printf(TRACE,Return_Address_Stack,FUNCTION," * miss_prediction : %d",miss_prediction); + +#ifdef DEBUG_TEST + Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); + Tcontrol_t prediction_ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * index : %d",index); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * prediction_ifetch : %d",prediction_ifetch); + +// if (prediction_ifetch) +// { +// if (index != reg_PREDICT_TOP [context_id]) +// throw ERRORMORPHEO(FUNCTION,_("Index is different of predict_top")); +// } +// else +// { +// if (index != reg_TOP [context_id]) +// throw ERRORMORPHEO(FUNCTION,_("Index is different of top")); +// } + +#endif + if (miss_prediction) + { + Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * push : %d",push); +#ifndef DEBUG_TEST + Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); + Tcontrol_t prediction_ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * index : %d",index); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * prediction_ifetch : %d",prediction_ifetch); +#endif + + + Tptr_t top_old = (prediction_ifetch)?reg_PREDICT_TOP [context_id]:reg_TOP [context_id]; + Tptr_t top_new = top_old; + +// Tptr_t bottom_old = (prediction_ifetch)?reg_PREDICT_BOTTOM [context_id]:reg_BOTTOM [context_id]; +// Tptr_t bottom_new = bottom_old; + + Tptr_t nb_elt_old = (prediction_ifetch)?reg_PREDICT_NB_ELT [context_id]:reg_NB_ELT [context_id]; + Tptr_t nb_elt_new = nb_elt_old; + + log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); + if (prediction_ifetch) + { + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_old); +// log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_old); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_old); + } + else + { + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",top_old); +// log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",bottom_old); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",nb_elt_old); + } + + // if previous is push, pop the value + // else is previous is pop, push the poped value + if (push) + { + // previous is push, now must be pop + + // Test if the stack is empty + if (nb_elt_old>0) // ?? + { + top_new = (top_old==0)?(_param->_size_queue[context_id]-1):(top_old-1); + nb_elt_new --; + } + } + else + { + // previous is pop, now must be push + Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); + + // push : increase the top (circular) +// if (nb_elt_old==_param->_size_queue[context_id]) +// bottom_new = (bottom_old+1)%_param->_size_queue[context_id]; +// else +// nb_elt_new ++; + + if (nb_elt_old!=_param->_size_queue[context_id]) + nb_elt_new ++; + + top_new = index; + + reg_stack [context_id][index]._address = address; + } + + log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); + + if (prediction_ifetch) + { + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_new); +// log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_new); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_new); + + reg_PREDICT_TOP [context_id] = top_new ; +// reg_PREDICT_BOTTOM [context_id] = bottom_new; + reg_PREDICT_NB_ELT [context_id] = nb_elt_new; + } + else + { + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",top_new); +// log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",bottom_new); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",nb_elt_new); + + reg_TOP [context_id] = top_new ; +// reg_BOTTOM [context_id] = bottom_new; + reg_NB_ELT [context_id] = nb_elt_new; + } + } + } } } + +#if defined(DEBUG_Return_Address_Stack) and DEBUG>=DEBUG_TRACE + log_printf(TRACE,Return_Address_Stack,FUNCTION," * Dump RAS"); + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + log_printf(TRACE,Return_Address_Stack,FUNCTION," * Return Address Stack [%d]",i); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_TOP : %d",reg_TOP [i]); +// log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_BOTTOM : %d",reg_BOTTOM [i]); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_NB_ELT : %d",reg_NB_ELT [i]); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_PREDICT_TOP : %d",reg_PREDICT_TOP [i]); +// log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_PREDICT_BOTTOM : %d",reg_PREDICT_BOTTOM [i]); + log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_PREDICT_NB_ELT : %d",reg_PREDICT_NB_ELT [i]); + + for (uint32_t j=0; j<_param->_size_queue[i]; ++j) + log_printf(TRACE,Return_Address_Stack,FUNCTION," [%d] %.8x (%.8x)",j,reg_stack [i][j]._address,reg_stack [i][j]._address<<2); + } +#endif #if defined(STATISTICS) or defined(VHDL_TESTBENCH) @@ -250,5 +387,5 @@ #endif - log_printf(FUNC,Return_Address_Stack,FUNCTION,"End"); + log_end(Return_Address_Stack,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 100) @@ -220,4 +220,6 @@ private : Tcounter_t ** reg_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context] private : Tcounter_t ** reg_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] + + private : Tevent_state_t ** reg_EVENT_STATE ;//[nb_front_end][nb_context] // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h (revision 100) @@ -27,19 +27,21 @@ typedef enum { - ROB_EMPTY , // - ROB_BRANCH_WAIT_END , // - ROB_BRANCH_COMPLETE , // - ROB_STORE_WAIT_HEAD_OK , // -// ROB_STORE_WAIT_HEAD_KO , // - ROB_STORE_HEAD_OK , // - ROB_STORE_HEAD_KO , // - ROB_OTHER_WAIT_END , // - ROB_MISS_WAIT_END , // - ROB_END_OK_SPECULATIVE , // - ROB_END_OK , // - ROB_END_KO_SPECULATIVE , // - ROB_END_KO , // - ROB_END_MISS , // - ROB_END_EXCEPTION_WAIT_HEAD , // + ROB_EMPTY , // + ROB_BRANCH_WAIT_END , // + ROB_BRANCH_COMPLETE , // + ROB_STORE_WAIT_HEAD_OK , // +// ROB_STORE_WAIT_HEAD_KO , // + ROB_STORE_HEAD_OK , // + ROB_STORE_HEAD_KO , // + ROB_OTHER_WAIT_END , // + ROB_MISS_WAIT_END , // + ROB_END_OK_SPECULATIVE , // + ROB_END_OK , // + ROB_END_KO_SPECULATIVE , // + ROB_END_KO , // + ROB_END_BRANCH_MISS_SPECULATIVE, // + ROB_END_BRANCH_MISS , // + ROB_END_MISS , // + ROB_END_EXCEPTION_WAIT_HEAD , // ROB_END_EXCEPTION // } rob_state_t; @@ -79,5 +81,4 @@ public : Tspecial_address_t num_reg_re_phy_new ; - public : Tevent_state_t event_state ; public : Texception_t exception ; public : Texception_t exception_use ; @@ -161,19 +162,23 @@ switch (x) { - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EMPTY : return "empty" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_WAIT_END : return "branch_wait_end" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_COMPLETE : return "branch_complete" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_OK : return "store_wait_head_ok" ; break; -// case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_KO : return "store_wait_head_ko" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_OK : return "store_head_ok" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO : return "store_head_ko" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END : return "other_wait_end" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_MISS_WAIT_END : return "miss_wait_end" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK_SPECULATIVE : return "end_ok_speculative" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK : return "end_ok" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO_SPECULATIVE : return "end_ko_speculative" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO : return "end_ko" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_WAIT_HEAD : return "end_exception_wait_head" ; break; - case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION : return "end_exception" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EMPTY : return "ROB_EMPTY" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_WAIT_END : return "ROB_BRANCH_WAIT_END" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_COMPLETE : return "ROB_BRANCH_COMPLETE" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_OK : return "ROB_STORE_WAIT_HEAD_OK" ; break; +// case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_KO : return "ROB_STORE_WAIT_HEAD_KO" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_OK : return "ROB_STORE_HEAD_OK" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO : return "ROB_STORE_HEAD_KO" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END : return "ROB_OTHER_WAIT_END" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_MISS_WAIT_END : return "ROB_MISS_WAIT_END" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK_SPECULATIVE : return "ROB_END_OK_SPECULATIVE" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK : return "ROB_END_OK" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO_SPECULATIVE : return "ROB_END_KO_SPECULATIVE" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO : return "ROB_END_KO" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_BRANCH_MISS_SPECULATIVE: return "ROB_END_BRANCH_MISS_SPECULATIVE" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_BRANCH_MISS : return "ROB_END_BRANCH_MISS" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_MISS : return "ROB_END_MISS" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_WAIT_HEAD : return "ROB_END_EXCEPTION_WAIT_HEAD" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION : return "ROB_END_EXCEPTION" ; break; + default : return "" ; break; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 100) @@ -272,16 +272,12 @@ // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - _rob = new std::list [_param->_nb_bank]; + ALLOC1(_rob ,std::list,_param->_nb_bank); - reg_BANK_PTR = new uint32_t [_param->_nb_bank]; - - reg_NB_INST_COMMIT_ALL = new Tcounter_t * [_param->_nb_front_end]; - reg_NB_INST_COMMIT_MEM = new Tcounter_t * [_param->_nb_front_end]; + ALLOC1(reg_BANK_PTR ,uint32_t ,_param->_nb_bank); + + ALLOC2(reg_NB_INST_COMMIT_ALL ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]); + ALLOC2(reg_NB_INST_COMMIT_MEM ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]); - for (uint32_t i=0; i<_param->_nb_front_end; i++) - { - reg_NB_INST_COMMIT_ALL [i] = new Tcounter_t [_param->_nb_context [i]]; - reg_NB_INST_COMMIT_MEM [i] = new Tcounter_t [_param->_nb_context [i]]; - } + ALLOC2(reg_EVENT_STATE ,Tevent_state_t,_param->_nb_front_end,_param->_nb_context [it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 100) @@ -178,15 +178,9 @@ // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - for (uint32_t i=0; i<_param->_nb_front_end; i++) - { - delete [] reg_NB_INST_COMMIT_ALL [i]; - delete [] reg_NB_INST_COMMIT_MEM [i]; - } - delete [] reg_NB_INST_COMMIT_ALL; - delete [] reg_NB_INST_COMMIT_MEM; - - delete [] reg_BANK_PTR; - - delete [] _rob; + DELETE1(_rob ,_param->_nb_bank); + DELETE1(reg_BANK_PTR ,_param->_nb_bank); + DELETE2(reg_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context [it1]); + DELETE2(reg_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context [it1]); + DELETE2(reg_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context [it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp (revision 100) @@ -30,4 +30,5 @@ uint32_t bank_nb_access [_param->_nb_bank]; Tcontrol_t commit_ack [_param->_nb_inst_commit]; + // Initialisation for (uint32_t i=0; i<_param->_nb_bank; i++) @@ -38,14 +39,15 @@ } - // commit interface + // commit interface -> scan all entry (Out of Order) for (uint32_t i=0; i<_param->_nb_inst_commit; i++) { commit_ack [i] = false; - // Test if have instruction + // Test if have valid instruction if (PORT_READ(in_COMMIT_VAL [i])) { - Tpacket_t packet = (_param->_have_port_rob_ptr )?PORT_READ(in_COMMIT_PACKET_ID [i]):0; - uint32_t num_bank = packet >> _param->_shift_num_bank; + // packet_id number can + Tpacket_t packet_id = (_param->_have_port_rob_ptr )?PORT_READ(in_COMMIT_PACKET_ID [i]):0; + uint32_t num_bank = packet_id >> _param->_shift_num_bank; uint32_t num_bank_access = bank_nb_access [num_bank]; @@ -60,5 +62,5 @@ internal_BANK_COMMIT_NUM_INST [num_bank][num_bank_access] = i; - Tpacket_t packet_id = packet & _param->_mask_size_bank; + Tpacket_t num_packet = packet_id & _param->_mask_size_bank; // find the good entry !!! @@ -67,5 +69,5 @@ it!=_rob[num_bank].end(); it++) - if ((*it)->ptr == packet_id) + if ((*it)->ptr == num_packet) { entry = (*it); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp (revision 100) @@ -54,5 +54,6 @@ std::list * select_insert = _priority_insert ->select(); // same select for all insert std::list::iterator it=select_insert ->begin(); - + + // Scan all bank ... for (uint32_t i=0; i<_param->_nb_bank; i++) { @@ -64,4 +65,5 @@ // log_printf(TRACE,Commit_unit,FUNCTION," * full : %d", bank_full [num_bank]); + // Scan all insert interface to find a valid transaction while (it!=select_insert ->end()) { @@ -87,5 +89,5 @@ if (not bank_full [num_bank]) { - // find + // find !!! insert_ack [num_rename_unit][num_inst_insert] = true; @@ -112,4 +114,5 @@ } + // Write output for (uint32_t i=0; i<_param->_nb_rename_unit; i++) for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp (revision 100) @@ -48,9 +48,13 @@ retire_val [i][j] = false; } - for (uint32_t i=0; i<_param->_nb_front_end; ++i) for (uint32_t j=0; j<_param->_nb_context[i]; ++j) - spr_write_val [i][j] = 0; - + { + spr_write_val [i][j] = 0; + spr_write_sr_f_val [i][j] = 0; + spr_write_sr_cy_val [i][j] = 0; + spr_write_sr_ov_val [i][j] = 0; + + } // Scan Top of each bank for (uint32_t i=0; i<_param->_nb_bank; i++) @@ -64,5 +68,8 @@ uint32_t x = entry->rename_unit_id; uint32_t y = num_inst_retire [x]; - + + // test if : + // * can retire (all previous instruction is retired) + // * all structure is ok (not busy) if (can_retire [x] and // in-order (y < _param->_nb_inst_retire [x]) and @@ -71,7 +78,8 @@ rob_state_t state = entry->state; - if ((state == ROB_END_OK ) or - (state == ROB_END_KO ) or - (state == ROB_END_MISS)// or + if ((state == ROB_END_OK ) or + (state == ROB_END_KO ) or + (state == ROB_END_BRANCH_MISS) or + (state == ROB_END_MISS )// or // (state == ROB_END_EXCEPTION) ) @@ -85,5 +93,7 @@ bool spr_write_ack = true; + // Write in SR the good flag if ((state == ROB_END_OK ) and write_re) + // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE { spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]); @@ -138,5 +148,5 @@ PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id ); // PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id ); - PORT_WRITE(out_RETIRE_EVENT_STATE [x][y], entry->event_state ); + PORT_WRITE(out_RETIRE_EVENT_STATE [x][y], reg_EVENT_STATE[front_end_id][context_id]); PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue ); PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp (revision 100) @@ -28,4 +28,7 @@ // =================================================================== { + // Store instruction comming Out Of Order in Load Store Unit. + // Must be executed in no speculative mode. Also, send a signal when an Store is in head of ROB + Tcontrol_t val = false; @@ -35,4 +38,5 @@ rob_state_t state = entry->state; + // Test state val = ((state == ROB_STORE_HEAD_OK) or (state == ROB_STORE_HEAD_KO)); @@ -40,4 +44,5 @@ if (val) { + // Reexecute store if (_param->_have_port_context_id) PORT_WRITE(out_REEXECUTE_CONTEXT_ID [0], entry->context_id ); @@ -62,6 +67,8 @@ // =================================================================== { + // Branchement must be send at the prediction unit uint32_t nb_scan_bank = 0; + // for each port, find a valid branchement. for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) { @@ -72,4 +79,5 @@ nb_scan_bank ++; + // translate bank number uint32_t num_bank = (reg_NUM_BANK_HEAD+j)%_param->_nb_bank; @@ -124,16 +132,4 @@ } } - -// public : SC_OUT(Tcontrol_t ) * out_UPDATE_VAL ; -// public : SC_IN (Tcontrol_t ) * in_UPDATE_ACK ; -// public : SC_OUT(Tcontext_t ) * out_UPDATE_CONTEXT_ID ; -// public : SC_OUT(Tcontext_t ) * out_UPDATE_FRONT_END_ID ; -// public : SC_OUT(Tdepth_t ) * out_UPDATE_DEPTH ; -// public : SC_OUT(Tevent_type_t ) * out_UPDATE_TYPE ; -// public : SC_OUT(Tcontrol_t ) * out_UPDATE_IS_DELAY_SLOT ; -// public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS ; -// public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EPCR ; -// public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EEAR_VAL ; -// public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EEAR ; // =================================================================== Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp (revision 100) @@ -57,4 +57,7 @@ _stat->create_expr_average_by_cycle("average_inst_retire_ko", sum_nb_inst_retire_ko, "", _("Average instruction retire ko (event, miss) by cycle")); _stat->create_expr_average_by_cycle("average_inst_retire" , "+ "+sum_nb_inst_retire_ok+" "+sum_nb_inst_retire_ko, "", _("Average instruction retire by cycle")); + + _stat->create_expr ("IPC", "average_inst_retire_ok", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle"); + _stat->create_expr ("CPI", "/ 1 IPC" , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction"); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 100) @@ -26,4 +26,5 @@ if (PORT_READ(in_NRESET) == 0) { + // Clear all bank for (uint32_t i=0; i<_param->_nb_bank; i++) { @@ -32,7 +33,9 @@ } + // Reset pointer reg_NUM_BANK_HEAD = 0; reg_NUM_BANK_TAIL = 0; + // Reset counter for (uint32_t i=0; i<_param->_nb_front_end; i++) for (uint32_t j=0; j<_param->_nb_context [i]; j++) @@ -40,12 +43,29 @@ reg_NB_INST_COMMIT_ALL [i][j] = 0; reg_NB_INST_COMMIT_MEM [i][j] = 0; + + reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; } + // Reset priority algorithm _priority_insert->reset(); } else { - // next priority + // Compute next priority _priority_insert->transition(); + + // =================================================================== + // =====[ GARBAGE COLLECTOR ]========================================= + // =================================================================== + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context [i]; j++) + switch (reg_EVENT_STATE [i][j]) + { + case EVENT_STATE_EVENT : reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; break; + case EVENT_STATE_END : reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; break; +// case EVENT_STATE_NO_EVENT : +// case EVENT_STATE_WAITEND : + default : break; + } // =================================================================== @@ -55,4 +75,5 @@ if (internal_BANK_INSERT_VAL [i]) { + // get rename unit source and instruction. uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i]; uint32_t y = internal_BANK_INSERT_NUM_INST [i]; @@ -67,8 +88,11 @@ #endif + // get information Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0; Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0; Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]); Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]); + bool is_store = is_operation_memory_store(operation); + Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]); @@ -78,5 +102,6 @@ log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); - + + // Create new entry. entry_t * entry = new entry_t; @@ -92,6 +117,6 @@ entry->exception = exception; entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); - entry->use_store_queue = (type == TYPE_MEMORY) and ( is_operation_memory_store(operation)); - entry->use_load_queue = (type == TYPE_MEMORY) and (not is_operation_memory_store(operation)); + entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store); + entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store); entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]); entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0; @@ -114,4 +139,12 @@ entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); + // Test if exception : + // * yes : no execute instruction, wait ROB Head + // * no : test type + // * BRANCH : l.j -> branch is ended + // other -> wait the execution end of branchment + // * MEMORY : store -> wait store is at head of ROB + // other -> wait end of instruction + // * OTHER if (exception == EXCEPTION_NONE) { @@ -124,5 +157,5 @@ { case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;} - case TYPE_MEMORY : {entry->state=ROB_STORE_WAIT_HEAD_OK; break;} + case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;} default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} } @@ -130,4 +163,6 @@ else { + // Have an exception : wait head of ROB + // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap @@ -135,7 +170,8 @@ } + // Push in rob _rob[i].push_back(entry); - // Update nb_inst + // Update counter and pointer reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++; if (type == TYPE_MEMORY) @@ -160,4 +196,6 @@ if (internal_BANK_COMMIT_VAL [i][j]) { + // An instruction is executed. Change state of this instruction + uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j]; @@ -171,93 +209,73 @@ #endif -// Tpacket_t packet_id = (_param->_have_port_rob_ptr )?(PORT_READ(in_COMMIT_PACKET_ID [x])&_param->_mask_size_bank):0; - log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i); -// log_printf(TRACE,Commit_unit,FUNCTION," * packet_id : %d",(_param->_have_port_rob_ptr )?(PORT_READ(in_COMMIT_PACKET_ID [x])):0); -// log_printf(TRACE,Commit_unit,FUNCTION," * num_entry : %d",packet_id); - - // test pandex with ptr_write. -// Tpacket_t index = (packet_id_size_bank+reg_BANK_PTR [i]-packet_id); // find the good entry !!! - entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j]; - - //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); - //Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]); - Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]); - - rob_state_t state = entry->state; - Tcontext_t front_end_id = entry->front_end_id; - Tcontext_t context_id = entry->context_id; - - // change state + entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j]; + + //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); + //Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]); + Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]); + + rob_state_t state = entry->state; + Tcontext_t front_end_id = entry->front_end_id; + Tcontext_t context_id = entry->context_id; + + // change state : test exception_use // * test if exception : exception and mask - bool have_exception = false; - + bool have_exception = false; + bool have_miss_speculation = false; + if (exception != EXCEPTION_NONE) - switch (entry->exception_use) - { - case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} - case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or - (exception == EXCEPTION_DATA_TLB ) or - (exception == EXCEPTION_DATA_PAGE) or - (exception == EXCEPTION_ALIGNMENT)); break;}; - case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or - (exception == EXCEPTION_DATA_TLB ) or - (exception == EXCEPTION_DATA_PAGE)); break;}; - case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; - case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; - case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; - case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; - case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; - case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; - case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; - case EXCEPTION_USE_TRAP : {have_exception = false; break;}; - case EXCEPTION_USE_NONE : {have_exception = false; break;}; - case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; break;}; - case EXCEPTION_USE_SYSCALL : {have_exception = false; break;}; - default : - { - throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); - break; - } - } - - if (not have_exception) - { - switch (state) - { - case ROB_OTHER_WAIT_END : {state = ROB_END_OK_SPECULATIVE; break;} - case ROB_BRANCH_WAIT_END : {state = ROB_BRANCH_COMPLETE ; break;} - case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} - default : - { - throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str())); - break; - } - } - // can have an exception, but this instruction is not sensible a this exception - exception = EXCEPTION_NONE; - } - else - { -#ifdef DEBUG_TEST - if ((entry->type == TYPE_MEMORY) and (exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) - throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception.\n")); -#endif - - switch (state) - { - case ROB_OTHER_WAIT_END : - case ROB_BRANCH_WAIT_END : {state = ROB_END_EXCEPTION_WAIT_HEAD; break;} - case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE ; break;} - default : - { - throw ERRORMORPHEO(FUNCTION,_("Commit : invalid state value.\n")); - break; - } - } - } + { + // Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store) + have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION); + + switch (entry->exception_use) + { + // Have overflow exception if bit overflow enable is set. + case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} + case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or + (exception == EXCEPTION_DATA_TLB ) or + (exception == EXCEPTION_DATA_PAGE) or + (exception == EXCEPTION_ALIGNMENT)); break;}; + case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or + (exception == EXCEPTION_DATA_TLB ) or + (exception == EXCEPTION_DATA_PAGE)); break;}; + case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; + case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; + case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; + case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; + case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; + case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; + case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; + // Case already manage (decod stage -> in insert in ROB) + case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;}; + case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;}; + case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;}; + case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;}; + default : + { + throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); + break; + } + } + } + + switch (state) + { + // Branch ... + case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;} + // Store KO + case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} + // Store OK, Load and other instruction + case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_MISS:ROB_END_OK_SPECULATIVE); break;} + default : + { + throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str())); + break; + } + } // update Re Order Buffer @@ -287,9 +305,9 @@ entry_t * entry = _rob [i].front(); + rob_state_t state = entry->state; + #ifdef STATISTICS if (usage_is_set(_usage,USE_STATISTICS)) { - rob_state_t state = entry->state; - if (state == ROB_END_OK) (*_stat_nb_inst_retire_ok [x]) ++; @@ -302,4 +320,11 @@ Tcontext_t context_id = entry->context_id ; Ttype_t type = entry->type ; + + if (state == ROB_END_BRANCH_MISS) + { + reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; + + // !!!!!!!!!!! Compute address + } // Update nb_inst @@ -307,5 +332,8 @@ if (type == TYPE_MEMORY) reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; - + + if (reg_NB_INST_COMMIT_ALL [front_end_id][context_id] == 0) + reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_END; + reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank; @@ -350,10 +378,21 @@ #endif - entry->state = ROB_END_OK_SPECULATIVE; + entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_OK_SPECULATIVE:ROB_END_BRANCH_MISS_SPECULATIVE; +// entry->state = ROB_END_OK_SPECULATIVE; } // =================================================================== + // =====[ UPDATE ]==================================================== + // =================================================================== + { + // Not yet implemented + } + + // =================================================================== // =====[ EVENT ]===================================================== // =================================================================== + { + // Not yet implemented + } // =================================================================== @@ -400,24 +439,26 @@ switch (state) { - case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} - case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} - case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} - //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} - case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} - case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} - case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} - case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} - - // don't change - case ROB_STORE_HEAD_KO : {break;} - case ROB_MISS_WAIT_END : {break;} - case ROB_END_MISS : {break;} - - // can't have miss speculation - case ROB_STORE_HEAD_OK : - case ROB_END_OK : - case ROB_END_KO : - case ROB_END_EXCEPTION : - default : + case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} + case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} + case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} + case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} + //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} + case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} + case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} + case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} + case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} + + // don't change + case ROB_STORE_HEAD_KO : {break;} + case ROB_MISS_WAIT_END : {break;} + case ROB_END_MISS : {break;} + + // can't have miss speculation + case ROB_STORE_HEAD_OK : + case ROB_END_OK : + case ROB_END_KO : + case ROB_END_BRANCH_MISS : + case ROB_END_EXCEPTION : + default : { throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n")); @@ -434,6 +475,7 @@ switch (state) { - case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} - case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} + case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} + case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} + case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} default : {break;} } @@ -519,11 +561,10 @@ (*it)->num_reg_re_phy_new ); - log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x %s", + log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x", (*it)->exception , (*it)->exception_use , (*it)->flags , (*it)->no_sequence , - (*it)->data_commit , - toString((*it)->event_state).c_str() + (*it)->data_commit ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp (revision 100) @@ -113,5 +113,6 @@ sensitive << (*(in_RENAME_CONTEXT_ID [i])); - sensitive << (*(in_RENAME_NUM_REG_RA_LOG [i])) + sensitive << (*(in_RENAME_VAL [i])) // Not necessary + << (*(in_RENAME_NUM_REG_RA_LOG [i])) << (*(in_RENAME_NUM_REG_RB_LOG [i])) << (*(in_RENAME_NUM_REG_RC_LOG [i])) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp (revision 100) @@ -29,19 +29,36 @@ if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access { + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RENAME [%d]",i); + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; - Tgeneral_address_t num_reg_ra_log = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register; - Tgeneral_address_t num_reg_rb_log = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register; - Tspecial_address_t num_reg_rc_log = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register; - Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register; - Tspecial_address_t num_reg_re_log = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register; + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id); - PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], rat_gpr[front_end_id][context_id][num_reg_ra_log]); - PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], rat_gpr[front_end_id][context_id][num_reg_rb_log]); - PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], rat_spr[front_end_id][context_id][num_reg_rc_log]); - PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], rat_gpr[front_end_id][context_id][num_reg_rd_log]); - PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], rat_spr[front_end_id][context_id][num_reg_re_log]); - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"yo6"); + Tgeneral_address_t num_reg_ra_log = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register; + Tgeneral_address_t num_reg_rb_log = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register; + Tspecial_address_t num_reg_rc_log = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register; + Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register; + Tspecial_address_t num_reg_re_log = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register; + + Tgeneral_address_t num_reg_ra_phy = rat_gpr[front_end_id][context_id][num_reg_ra_log]; + Tgeneral_address_t num_reg_rb_phy = rat_gpr[front_end_id][context_id][num_reg_rb_log]; + Tspecial_address_t num_reg_rc_phy = rat_spr[front_end_id][context_id][num_reg_rc_log]; + Tgeneral_address_t num_reg_rd_phy_old= rat_gpr[front_end_id][context_id][num_reg_rd_log]; + Tspecial_address_t num_reg_re_phy_old= rat_spr[front_end_id][context_id][num_reg_re_log]; + + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_ra : %d -> %d",num_reg_ra_log,num_reg_ra_phy ); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rb : %d -> %d",num_reg_rb_log,num_reg_rb_phy ); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rc : %d -> %d",num_reg_rc_log,num_reg_rc_phy ); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re : %d -> %d",num_reg_re_log,num_reg_re_phy_old); + + + PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], num_reg_ra_phy ); + PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], num_reg_rb_phy ); + PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], num_reg_rc_phy ); + PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old); + PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp (revision 100) @@ -37,7 +37,13 @@ for (uint32_t k=1; k<_param->_nb_general_register_logic; k++) - rat_gpr [i][j][k] = gpr++; + { + rat_gpr [i][j][k] = gpr++; +// rat_gpr_update_table[i][j][k] = 0; + } for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) - rat_spr [i][j][k] = spr++; + { + rat_spr [i][j][k] = spr++; +// rat_spr_update_table[i][j][k] = 0; + } } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp (revision 100) @@ -95,4 +95,10 @@ if (PORT_READ(in_SPR_COMMIT_VAL [i][j])) // out_SPR_COMMIT_ACK [i][j] { + log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR_COMMIT [%d][%d]",i,j); + log_printf(TRACE,Special_Register_unit,FUNCTION," * F : %d, %d",PORT_READ(in_SPR_COMMIT_SR_F_VAL [i][j]),PORT_READ(in_SPR_COMMIT_SR_F [i][j])); + log_printf(TRACE,Special_Register_unit,FUNCTION," * CY : %d, %d",PORT_READ(in_SPR_COMMIT_SR_CY_VAL [i][j]),PORT_READ(in_SPR_COMMIT_SR_CY [i][j])); + log_printf(TRACE,Special_Register_unit,FUNCTION," * OV : %d, %d",PORT_READ(in_SPR_COMMIT_SR_OV_VAL [i][j]),PORT_READ(in_SPR_COMMIT_SR_OV [i][j])); + + log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR (before) : %.8x",_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]->read()); SR * sr = static_cast(_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]); @@ -105,8 +111,14 @@ if (PORT_READ(in_SPR_COMMIT_SR_OV_VAL [i][j])) sr->ov = PORT_READ(in_SPR_COMMIT_SR_OV [i][j]); + + log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR (after) : %.8x",_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]->read()); + } if (PORT_READ(in_SPR_EVENT_VAL [i][j])) // out_SPR_EVENT_ACK [i][j] { + log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR_EVENT [%d][%d]",i,j); + log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR (before) : %.8x",_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]->read()); + SR * sr = static_cast(_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]); sr->dsx = PORT_READ(in_SPR_EVENT_SR_DSX [i][j]); @@ -117,4 +129,6 @@ if (PORT_READ(in_SPR_EVENT_SR_TO_ESR [i][j])) _spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_ESR ]->write(sr->read()); + + log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR (after) : %.8x",_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]->read()); } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/Makefile.deps (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/Makefile.deps (revision 100) @@ -26,19 +26,17 @@ $(Behavioural_DIR_LIBRARY) -Queue_DEPENDENCIES = Queue_Control_library \ - Behavioural_library - -Queue_CLEAN = Queue_Control_library_clean \ - Behavioural_library_clean - #-----[ Rules ]-------------------------------------------- #.NOTPARALLEL : Queue_library Queue_library_clean -Queue_library : $(Queue_DEPENDENCIES) +Queue_library : @\ + $(MAKE) Behavioural_library;\ + $(MAKE) Queue_Control_library;\ $(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/Queue --makefile=Makefile; -Queue_library_clean : $(Queue_CLEAN) +Queue_library_clean : @\ + $(MAKE) Behavioural_library_clean;\ + $(MAKE) Queue_Control_library_clean;\ $(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Generic/Queue --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_min.cfg (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_min.cfg (revision 100) @@ -0,0 +1,4 @@ +Queue +1 1 *2 #_size_queue +1 1 *2 #_size_data +0 1 +1 #_nb_port_slot Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_size_queue_log2.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_size_queue_log2.cfg (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_size_queue_log2.cfg (revision 100) @@ -2,2 +2,3 @@ 1 32 *2 #_size_queue 32 32 *2 #_size_data +0 0 *2 #_nb_port_slot Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_size_queue_no_log2.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_size_queue_no_log2.cfg (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_size_queue_no_log2.cfg (revision 100) @@ -2,2 +2,3 @@ 3 256 *4 #_size_queue 32 32 *2 #_size_data +0 0 *2 #_nb_port_slot Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_slot_out_size_queue_log2.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_slot_out_size_queue_log2.cfg (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_slot_out_size_queue_log2.cfg (revision 100) @@ -0,0 +1,4 @@ +Queue +8 8 *2 #_size_queue +32 32 *2 #_size_data +1 8 *2 #_nb_port_slot Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_slot_out_size_queue_no_log2.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_slot_out_size_queue_no_log2.cfg (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/config_slot_out_size_queue_no_log2.cfg (revision 100) @@ -0,0 +1,4 @@ +Queue +11 11 *4 #_size_queue +32 32 *2 #_size_data +1 8 *2 #_nb_port_slot Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/include/test.h (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/include/test.h (revision 100) @@ -16,4 +16,5 @@ #include "Behavioural/Generic/Queue/include/Queue.h" +#include "Common/include/Time.h" using namespace std; @@ -26,34 +27,2 @@ void test (string name, morpheo::behavioural::generic::queue::Parameters * param); - -class Time -{ -private : timeval time_begin; -// private : timeval time_end; - -public : Time () - { - gettimeofday(&time_begin ,NULL); - }; - -public : ~Time () - { - cout << *this; - }; - -public : friend ostream& operator<< (ostream& output_stream, - const Time & x) - { - timeval time_end; - - gettimeofday(&time_end ,NULL); - - uint32_t nb_cycles = static_cast(sc_simulation_time()); - - double average = static_cast(nb_cycles) / static_cast(time_end.tv_sec-x.time_begin.tv_sec); - - output_stream << nb_cycles << "\t(" << average << " cycles / seconds )" << endl; - - return output_stream; - } -}; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/src/main.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/src/main.cpp (revision 100) @@ -8,5 +8,5 @@ #include "Behavioural/Generic/Queue/SelfTest/include/test.h" -#define NB_PARAMS 2 +#define NB_PARAMS 3 void usage (int argc, char * argv[]) @@ -14,6 +14,7 @@ cerr << " " << argv[0] << " name_instance list_params" << endl << "list_params is :" << endl - << " - size_queue (uint32_t)" << endl - << " - size_data (uint32_t)" << endl + << " - size_queue (uint32_t)" << endl + << " - size_data (uint32_t)" << endl + << " - nb_port_slot (uint32_t)" << endl << "" << endl; @@ -36,7 +37,8 @@ uint32_t x = 1; - const string name = argv[x++]; - const uint32_t size_queue = atoi(argv[x++]); - const uint32_t size_data = atoi(argv[x++]); + const string name = argv[x++]; + const uint32_t size_queue = atoi(argv[x++]); + const uint32_t size_data = atoi(argv[x++]); + const uint32_t nb_port_slot = atoi(argv[x++]); try @@ -44,5 +46,6 @@ morpheo::behavioural::generic::queue::Parameters * param = new morpheo::behavioural::generic::queue::Parameters (size_queue, - size_data + size_data , + nb_port_slot ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/src/test.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/src/test.cpp (revision 100) @@ -11,4 +11,5 @@ #include "Behavioural/Generic/Queue/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" #include "Common/include/Test.h" @@ -48,10 +49,13 @@ sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); sc_signal * in_NRESET = new sc_signal ("NRESET"); - sc_signal * in_INSERT_VAL = new sc_signal ( "in_INSERT_VAL" ); - sc_signal * out_INSERT_ACK = new sc_signal ("out_INSERT_ACK" ); - sc_signal * in_INSERT_DATA = new sc_signal ( "in_INSERT_DATA"); - sc_signal * out_RETIRE_VAL = new sc_signal ("out_RETIRE_VAL" ); - sc_signal * in_RETIRE_ACK = new sc_signal ( "in_RETIRE_ACK" ); - sc_signal * out_RETIRE_DATA = new sc_signal ("out_RETIRE_DATA"); + + ALLOC0_SC_SIGNAL( in_INSERT_VAL , "in_INSERT_VAL" ,Tcontrol_t); + ALLOC0_SC_SIGNAL(out_INSERT_ACK ,"out_INSERT_ACK" ,Tcontrol_t); + ALLOC0_SC_SIGNAL( in_INSERT_DATA, "in_INSERT_DATA",Tdata_t ); + ALLOC0_SC_SIGNAL(out_RETIRE_VAL ,"out_RETIRE_VAL" ,Tcontrol_t); + ALLOC0_SC_SIGNAL( in_RETIRE_ACK , "in_RETIRE_ACK" ,Tcontrol_t); + ALLOC0_SC_SIGNAL(out_RETIRE_DATA,"out_RETIRE_DATA",Tdata_t ); + ALLOC1_SC_SIGNAL(out_SLOT_VAL ,"out_SLOT_VAL" ,Tcontrol_t,_param->_nb_port_slot); + ALLOC1_SC_SIGNAL(out_SLOT_DATA ,"out_SLOT_DATA" ,Tdata_t ,_param->_nb_port_slot); /******************************************************** @@ -64,10 +68,12 @@ (*(_Queue->in_NRESET)) (*(in_NRESET)); - (*(_Queue-> in_INSERT_VAL )) (*( in_INSERT_VAL )); - (*(_Queue->out_INSERT_ACK )) (*(out_INSERT_ACK )); - (*(_Queue-> in_INSERT_DATA)) (*( in_INSERT_DATA)); - (*(_Queue->out_RETIRE_VAL )) (*(out_RETIRE_VAL )); - (*(_Queue-> in_RETIRE_ACK )) (*( in_RETIRE_ACK )); - (*(_Queue->out_RETIRE_DATA)) (*(out_RETIRE_DATA)); + INSTANCE0_SC_SIGNAL(_Queue, in_INSERT_VAL ); + INSTANCE0_SC_SIGNAL(_Queue,out_INSERT_ACK ); + INSTANCE0_SC_SIGNAL(_Queue, in_INSERT_DATA); + INSTANCE0_SC_SIGNAL(_Queue,out_RETIRE_VAL ); + INSTANCE0_SC_SIGNAL(_Queue, in_RETIRE_ACK ); + INSTANCE0_SC_SIGNAL(_Queue,out_RETIRE_DATA); + INSTANCE1_SC_SIGNAL(_Queue,out_SLOT_VAL ,_param->_nb_port_slot); + INSTANCE1_SC_SIGNAL(_Queue,out_SLOT_DATA ,_param->_nb_port_slot); cout << "<" << name << "> Start Simulation ............" << endl; @@ -103,4 +109,5 @@ uint32_t data_in = 0; uint32_t data_out = 0; + uint32_t nb_elt = 0; for (uint32_t iteration=0; iteration_nb_port_slot; ++i) + { + TEST(Tcontrol_t, out_SLOT_VAL [i]->read(), (iread(), data_out+i); + + } + if ( in_INSERT_VAL->read() and out_INSERT_ACK->read()) { LABEL ("Transaction with interface : INSERT"); data_in ++; + nb_elt ++; } if (out_RETIRE_VAL->read() and in_RETIRE_ACK->read()) @@ -126,4 +142,5 @@ TEST(Tdata_t, out_RETIRE_DATA->read(), data_out); data_out++; + nb_elt --; } @@ -142,4 +159,14 @@ delete in_CLOCK; delete in_NRESET; + + DELETE0_SC_SIGNAL( in_INSERT_VAL ); + DELETE0_SC_SIGNAL(out_INSERT_ACK ); + DELETE0_SC_SIGNAL( in_INSERT_DATA); + DELETE0_SC_SIGNAL(out_RETIRE_VAL ); + DELETE0_SC_SIGNAL( in_RETIRE_ACK ); + DELETE0_SC_SIGNAL(out_RETIRE_DATA); + DELETE1_SC_SIGNAL(out_SLOT_VAL ,_param->_nb_port_slot); + DELETE1_SC_SIGNAL(out_SLOT_DATA ,_param->_nb_port_slot); + #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Parameters.h (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Parameters.h (revision 100) @@ -22,11 +22,13 @@ { //-----[ fields ]------------------------------------------------------------ - public : const uint32_t _size_queue; - public : const uint32_t _size_data ; - + public : const uint32_t _size_queue ; + public : const uint32_t _size_data ; + public : const uint32_t _nb_port_slot; //-----[ methods ]----------------------------------------------------------- public : Parameters (uint32_t size_queue, - uint32_t size_data ); + uint32_t size_data , + uint32_t nb_port_slot); + // public : Parameters (Parameters & param) ; public : ~Parameters () ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Queue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Queue.h (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Queue.h (revision 100) @@ -74,4 +74,8 @@ public : SC_OUT(Tdata_t ) * out_RETIRE_DATA; + // ~~~~~[ Interface "slot" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t) ** out_SLOT_VAL ; + public : SC_OUT(Tdata_t ) ** out_SLOT_DATA; + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ protected : morpheo::behavioural::generic::queue_control::Queue_Control * _queue_control; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters.cpp (revision 100) @@ -17,7 +17,9 @@ #define FUNCTION "Queue::Parameters" Parameters::Parameters (uint32_t size_queue, - uint32_t size_data ): - _size_queue (size_queue), - _size_data (size_data ) + uint32_t size_data , + uint32_t nb_port_slot): + _size_queue (size_queue), + _size_data (size_data ), + _nb_port_slot (nb_port_slot) { log_printf(FUNC,Queue,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters_msg_error.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters_msg_error.cpp (revision 100) @@ -23,4 +23,7 @@ Parameters_test test("Queue"); + if (_nb_port_slot > _size_queue) + test.error(_("nb_port_slot must be <= size_queue\n")); + log_printf(FUNC,Queue,FUNCTION,"End"); @@ -30,5 +33,4 @@ }; // end namespace queue }; // end namespace generic - }; // end namespace behavioural }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp (revision 100) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/Queue/include/Queue.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -38,5 +39,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -48,29 +49,26 @@ // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - Interface_fifo * interface = _interfaces->set_interface("insert" -#ifdef POSITION - ,IN - ,WEST - ,"Insertion of data" -#endif - ); + ALLOC0_INTERFACE("insert", IN, WEST, _("Interface of data write.")); - in_INSERT_VAL = interface->set_signal_valack_in (VAL); - out_INSERT_ACK = interface->set_signal_valack_out(ACK); - in_INSERT_DATA = interface->set_signal_in ("data", _param->_size_data); + ALLOC0_VALACK_IN ( in_INSERT_VAL ,VAL); + ALLOC0_VALACK_OUT(out_INSERT_ACK ,ACK); + ALLOC0_SIGNAL_IN ( in_INSERT_DATA ,"data",Tdata_t,_param->_size_data); } + // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - Interface_fifo * interface = _interfaces->set_interface("retire" -#ifdef POSITION - ,IN - ,EAST - ,"Retire of data" -#endif - ); + ALLOC0_INTERFACE("retire", OUT, EAST, _("Interface of data read.")); - out_RETIRE_VAL = interface->set_signal_valack_out(VAL); - in_RETIRE_ACK = interface->set_signal_valack_in (ACK); - out_RETIRE_DATA = interface->set_signal_out ("data", _param->_size_data); + ALLOC0_VALACK_OUT(out_RETIRE_VAL ,VAL); + ALLOC0_VALACK_IN ( in_RETIRE_ACK ,ACK); + ALLOC0_SIGNAL_OUT(out_RETIRE_DATA ,"data",Tdata_t,_param->_size_data); + } + + // ~~~~~[ Interface "slot" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("slot", OUT, EAST, _("Internal slot."),_param->_nb_port_slot); + + ALLOC1_VALACK_OUT(out_SLOT_VAL ,VAL); + ALLOC1_SIGNAL_OUT(out_SLOT_DATA ,"data",Tdata_t,_param->_size_data); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_deallocation.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_deallocation.cpp (revision 100) @@ -7,4 +7,5 @@ #include "Behavioural/Generic/Queue/include/Queue.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -24,12 +25,15 @@ delete in_CLOCK ; delete in_NRESET; - - delete in_INSERT_VAL ; - delete out_INSERT_ACK ; - delete in_INSERT_DATA; - - delete out_RETIRE_VAL ; - delete in_RETIRE_ACK ; - delete out_RETIRE_DATA; + + DELETE0_SIGNAL( in_INSERT_VAL ,1); + DELETE0_SIGNAL(out_INSERT_ACK ,1); + DELETE0_SIGNAL( in_INSERT_DATA ,_param->_size_data); + + DELETE0_SIGNAL(out_RETIRE_VAL ,1); + DELETE0_SIGNAL( in_RETIRE_ACK ,1); + DELETE0_SIGNAL(out_RETIRE_DATA ,_param->_size_data); + + DELETE1_SIGNAL(out_SLOT_VAL ,_param->_nb_port_slot,1); + DELETE1_SIGNAL(out_SLOT_DATA ,_param->_nb_port_slot,_param->_size_data); // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_genMoore.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_genMoore.cpp (revision 100) @@ -19,5 +19,6 @@ { log_printf(FUNC,Queue,FUNCTION,"Begin"); - + + // Output internal_INSERT_ACK = not _queue_control->full(); internal_RETIRE_VAL = not _queue_control->empty(); @@ -26,4 +27,14 @@ PORT_WRITE(out_RETIRE_VAL , internal_RETIRE_VAL); PORT_WRITE(out_RETIRE_DATA,_queue_data[(*_queue_control)[0]]); + + // Slot + // Note : Slot 0 is the same slot as retire interface. + uint32_t nb_elt = _queue_control->nb_elt(); + + for (uint32_t i=0; i<_param->_nb_port_slot; ++i) + { + PORT_WRITE(out_SLOT_VAL [i], iset_body ("-----------------------------------------------------------------------------"); - vhdl->set_body ("-- Output"); - vhdl->set_body ("-----------------------------------------------------------------------------"); - vhdl->set_body ("out_INSERT_ACK <= not reg_FULL;"); - vhdl->set_body ("out_RETIRE_VAL <= not reg_EMPTY;"); - - if (_param->_size_queue > 1) - vhdl->set_body ("out_RETIRE_DATA <= reg_DATA(conv_integer(reg_PTR_READ));"); - else - vhdl->set_body ("out_RETIRE_DATA <= reg_DATA(0);"); - - vhdl->set_body (""); - vhdl->set_body ("-----------------------------------------------------------------------------"); - vhdl->set_body ("-- Signal"); - vhdl->set_body ("-----------------------------------------------------------------------------"); - vhdl->set_body (""); - vhdl->set_body ("signal_PTR_EQUAL <="); - if (_param->_size_queue > 1) - { - vhdl->set_body ("\t'1' when signal_NEXT_PTR_READ = signal_NEXT_PTR_WRITE else"); - vhdl->set_body ("\t'0';"); - } - else - vhdl->set_body ("\t'1';"); - vhdl->set_body ("signal_NEXT_FULL <="); - vhdl->set_body ("\t'1' when signal_WRITE='1' and signal_PTR_EQUAL='1' else"); - vhdl->set_body ("\t'0' when signal_READ ='1' else"); - vhdl->set_body ("\treg_FULL ;"); - vhdl->set_body ("signal_NEXT_EMPTY <="); - vhdl->set_body ("\t'1' when signal_READ ='1' and signal_PTR_EQUAL='1' else"); - vhdl->set_body ("\t'0' when signal_WRITE='1' else"); - vhdl->set_body ("\treg_EMPTY;"); - vhdl->set_body (""); - vhdl->set_body ("-- read"); - vhdl->set_body ("signal_READ <= (not reg_EMPTY) and in_RETIRE_ACK;"); - + vhdl->set_comment(0,"---------------------------------------------------------------------------"); + vhdl->set_comment(0," Output"); + vhdl->set_comment(0,"---------------------------------------------------------------------------"); + vhdl->set_body (0,"out_INSERT_ACK <= not signal_FULL;"); + vhdl->set_body (0,"out_RETIRE_VAL <= not signal_EMPTY;"); + + if (_param->_size_queue > 1) + vhdl->set_body (0,"out_RETIRE_DATA <= reg_DATA(conv_integer(signal_PTR_READ));"); + else + vhdl->set_body (0,"out_RETIRE_DATA <= reg_DATA(0);"); + + vhdl->set_body (0,""); + vhdl->set_comment(0,"---------------------------------------------------------------------------"); + vhdl->set_comment(0," Slot"); + vhdl->set_comment(0,"---------------------------------------------------------------------------"); + vhdl->set_body (0,""); + if (_param->_nb_port_slot > 1) + for (uint32_t i=0; i<_param->_nb_port_slot; ++i) + if (i==0) + vhdl->set_body (0,"signal_SLOT_0 <= signal_PTR_READ;"); + else + { + if (is_power2(_param->_size_queue)) + vhdl->set_body (0,"signal_SLOT_"+toString(i)+" <= signal_PTR_READ+"+std_logic_cst(log2(_param->_size_queue),i)+";"); + else + vhdl->set_body (0,"signal_SLOT_"+toString(i)+" <= const_PTR_INIT when signal_SLOT_"+toString(i-1)+" = const_PTR_MAX else signal_SLOT_"+toString(i-1)+"+'1';"); + } + + for (uint32_t i=0; i<_param->_nb_port_slot; ++i) + { + if (_param->_nb_port_slot > 1) + vhdl->set_body (0,"out_SLOT_"+toString(i)+"_VAL <= '1' when reg_NB_ELT > "+std_logic_cst(log2(_param->_size_queue+1),i)+" else '0';"); + else + vhdl->set_body (0,"out_SLOT_"+toString(i)+"_VAL <= not signal_EMPTY;"); + + if (_param->_nb_port_slot > 1) + vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <= reg_DATA(conv_integer(signal_SLOT_"+toString(i)+"));"); + else + if (_param->_size_queue > 1) + vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <= reg_DATA(conv_integer(signal_PTR_READ));"); + else + vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <= reg_DATA(conv_integer(0));"); + } + + vhdl->set_body (0,""); + vhdl->set_comment(0,"---------------------------------------------------------------------------"); + vhdl->set_comment(0," Signal"); + vhdl->set_comment(0,"---------------------------------------------------------------------------"); + vhdl->set_body (0,""); + vhdl->set_body (0,"signal_READ <= (not signal_EMPTY) and in_RETIRE_ACK;"); + vhdl->set_body (0,"signal_WRITE <= (not signal_FULL ) and in_INSERT_VAL;"); + vhdl->set_body (0,""); + if (_param->_nb_port_slot>1) + { + vhdl->set_body (0,"signal_EMPTY <= '1' when reg_NB_ELT = "+std_logic_cst(log2(_param->_size_queue+1),0)+" else '0';"); + if (is_power2(_param->_size_queue)) + vhdl->set_body (0,"signal_FULL <= reg_NB_ELT "+std_logic_range(log2(_param->_size_queue),log2(_param->_size_queue))+";"); + else + vhdl->set_body (0,"signal_FULL <= '1' when reg_NB_ELT = "+std_logic_cst(log2(_param->_size_queue+1),_param->_size_queue)+" else '0';"); + } + else + { + vhdl->set_body (0,"signal_EMPTY <= reg_EMPTY;"); + vhdl->set_body (0,"signal_FULL <= reg_FULL ;"); + } + vhdl->set_body (0,""); + if (_param->_size_queue > 1) + { + vhdl->set_body (0,"signal_PTR_READ <= reg_PTR_READ;"); + if (_param->_nb_port_slot>1) + { + if (is_power2(_param->_size_queue)) + vhdl->set_body (0,"signal_PTR_WRITE <= reg_PTR_READ + reg_NB_ELT"+std_logic_range(log2(_param->_size_queue))+";"); + else + vhdl->set_body (0,"signal_PTR_WRITE <= reg_PTR_READ + reg_NB_ELT"+std_logic_range(log2(_param->_size_queue))+" when reg_PTR_READ + reg_NB_ELT"+std_logic_range(log2(_param->_size_queue)) +" <= const_PTR_MAX else reg_PTR_READ + reg_NB_ELT"+std_logic_range(log2(_param->_size_queue))+" - const_PTR_MAX-'1';"); + } + else + vhdl->set_body (0,"signal_PTR_WRITE <= reg_PTR_WRITE;"); + } + vhdl->set_body (0,""); + + if (_param->_nb_port_slot>1) + { + vhdl->set_body (0,""); + vhdl->set_comment(0," nb_elt"); if (_param->_size_queue > 1) { - vhdl->set_body ("signal_NEXT_PTR_READ <= "); - vhdl->set_body ("\treg_PTR_READ when signal_READ='0' else"); - if (is_log2(_param->_size_queue) == false) - vhdl->set_body ("\tconst_PTR_INIT when reg_PTR_READ = const_PTR_MAX else"); - - if (_param->_size_queue > 2) - vhdl->set_body ("\treg_PTR_READ +'1';"); - else - vhdl->set_body ("\tnot reg_PTR_READ;"); - } - vhdl->set_body (""); - vhdl->set_body ("-- write"); - vhdl->set_body ("signal_WRITE <= (not reg_FULL ) and in_INSERT_VAL;"); - if (_param->_size_queue > 1) - { - vhdl->set_body ("signal_NEXT_PTR_WRITE <= "); - vhdl->set_body ("\treg_PTR_WRITE when signal_WRITE='0' else"); - if (is_log2(_param->_size_queue) == false) - vhdl->set_body ("\tconst_PTR_INIT when reg_PTR_WRITE = const_PTR_MAX else"); - if (_param->_size_queue > 2) - vhdl->set_body ("\treg_PTR_WRITE+'1';"); - else - vhdl->set_body ("\tnot reg_PTR_WRITE;"); - } - vhdl->set_body (""); - vhdl->set_body ("-----------------------------------------------------------------------------"); - vhdl->set_body ("-- Registers"); - vhdl->set_body ("-----------------------------------------------------------------------------"); - vhdl->set_body (""); - vhdl->set_body ("queue_write: process (in_CLOCK)"); - vhdl->set_body ("begin -- process queue_write"); - vhdl->set_body ("\tif in_CLOCK'event and in_CLOCK = '1' then"); - vhdl->set_body (""); - vhdl->set_body ("\t\tif (in_NRESET = '0') then"); - if (_param->_size_queue > 1) - { - vhdl->set_body ("\t\t\treg_PTR_READ <= const_PTR_INIT;"); - vhdl->set_body ("\t\t\treg_PTR_WRITE <= const_PTR_INIT;"); - } - vhdl->set_body ("\t\t\treg_FULL <= '0';"); - vhdl->set_body ("\t\t\treg_EMPTY <= '1';"); - vhdl->set_body ("\t\telse"); - if (_param->_size_queue > 1) - { - vhdl->set_body ("\t\t\treg_PTR_READ <= signal_NEXT_PTR_READ ;"); - vhdl->set_body ("\t\t\treg_PTR_WRITE <= signal_NEXT_PTR_WRITE;"); - } - vhdl->set_body ("\t\t\treg_FULL <= signal_NEXT_FULL ;"); - vhdl->set_body ("\t\t\treg_EMPTY <= signal_NEXT_EMPTY;"); - vhdl->set_body (""); - vhdl->set_body ("\t\t\tif (signal_WRITE = '1') then"); - if (_param->_size_queue > 1) - vhdl->set_body ("\t\t\t\treg_DATA(conv_integer(reg_PTR_WRITE)) <= in_INSERT_DATA;"); - else - vhdl->set_body ("\t\t\t\treg_DATA(0) <= in_INSERT_DATA;"); - vhdl->set_body ("\t\t\tend if;"); - vhdl->set_body ("\t\tend if;"); - vhdl->set_body (""); - vhdl->set_body ("\tend if;"); - vhdl->set_body ("end process queue_write;"); + vhdl->set_body (0,"signal_NEXT_NB_ELT <= "); + vhdl->set_body (1,"reg_NB_ELT when (signal_READ xor signal_WRITE) = '0' else"); + if (_param->_size_queue > 2) + { + vhdl->set_body (1,"reg_NB_ELT +'1' when signal_WRITE='1' else"); + vhdl->set_body (1,"reg_NB_ELT -'1';"); + } + else + vhdl->set_body (1,"not reg_NB_ELT;"); + } + } + else + { + vhdl->set_body (0,"signal_PTR_EQUAL <="); + if (_param->_size_queue > 1) + { + vhdl->set_body (1,"'1' when signal_NEXT_PTR_READ = signal_NEXT_PTR_WRITE else"); + vhdl->set_body (1,"'0';"); + } + else + vhdl->set_body (1,"'1';"); + vhdl->set_body (0,"signal_NEXT_FULL <="); + vhdl->set_body (1,"'1' when signal_WRITE='1' and signal_PTR_EQUAL='1' else"); + vhdl->set_body (1,"'0' when signal_READ ='1' else"); + vhdl->set_body (1,"reg_FULL ;"); + vhdl->set_body (0,"signal_NEXT_EMPTY <="); + vhdl->set_body (1,"'1' when signal_READ ='1' and signal_PTR_EQUAL='1' else"); + vhdl->set_body (1,"'0' when signal_WRITE='1' else"); + vhdl->set_body (1,"reg_EMPTY;"); + vhdl->set_body (0,""); + + vhdl->set_comment(0," write"); + if (_param->_size_queue > 1) + { + vhdl->set_body (0,"signal_NEXT_PTR_WRITE <= "); + vhdl->set_body (1,"reg_PTR_WRITE when signal_WRITE='0' else"); + if (is_log2(_param->_size_queue) == false) + vhdl->set_body (1,"const_PTR_INIT when reg_PTR_WRITE = const_PTR_MAX else"); + if (_param->_size_queue > 2) + vhdl->set_body (1,"reg_PTR_WRITE+'1';"); + else + vhdl->set_body (1,"not reg_PTR_WRITE;"); + } + } + + vhdl->set_body (0,""); + vhdl->set_comment(0," read"); + if (_param->_size_queue > 1) + { + vhdl->set_body (0,"signal_NEXT_PTR_READ <= "); + vhdl->set_body (1,"reg_PTR_READ when signal_READ='0' else"); + if (is_log2(_param->_size_queue) == false) + vhdl->set_body (1,"const_PTR_INIT when reg_PTR_READ = const_PTR_MAX else"); + + if (_param->_size_queue > 2) + vhdl->set_body (1,"reg_PTR_READ +'1';"); + else + vhdl->set_body (1,"not reg_PTR_READ;"); + } + vhdl->set_body (0,""); + + vhdl->set_comment(0,"---------------------------------------------------------------------------"); + vhdl->set_comment(0," Registers"); + vhdl->set_comment(0,"---------------------------------------------------------------------------"); + vhdl->set_body (0,""); + vhdl->set_body (0,"queue_write: process (in_CLOCK)"); + vhdl->set_body (0,"begin -- process queue_write"); + vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); + vhdl->set_body (0,""); + vhdl->set_body (2,"if (in_NRESET = '0') then"); + if (_param->_size_queue > 1) + { + vhdl->set_body (3,"reg_PTR_READ <= const_PTR_INIT;"); + if (_param->_nb_port_slot>1) + vhdl->set_body (3,"reg_NB_ELT <= "+std_logic_cst(log2(_param->_size_queue+1),0)+";"); + else + vhdl->set_body (3,"reg_PTR_WRITE <= const_PTR_INIT;"); + } + if (_param->_nb_port_slot<=1) + { + vhdl->set_body (3,"reg_FULL <= '0';"); + vhdl->set_body (3,"reg_EMPTY <= '1';"); + } + vhdl->set_body (2,"else"); + if (_param->_size_queue > 1) + { + vhdl->set_body (3,"reg_PTR_READ <= signal_NEXT_PTR_READ ;"); + if (_param->_nb_port_slot>1) + vhdl->set_body (3,"reg_NB_ELT <= signal_NEXT_NB_ELT ;"); + else + vhdl->set_body (3,"reg_PTR_WRITE <= signal_NEXT_PTR_WRITE;"); + } + if (_param->_nb_port_slot<=1) + { + vhdl->set_body (3,"reg_FULL <= signal_NEXT_FULL ;"); + vhdl->set_body (3,"reg_EMPTY <= signal_NEXT_EMPTY;"); + } + vhdl->set_body (0,""); + vhdl->set_body (3,"if (signal_WRITE = '1') then"); + if (_param->_size_queue > 1) + vhdl->set_body (3,"\treg_DATA(conv_integer(signal_PTR_WRITE)) <= in_INSERT_DATA;"); + else + vhdl->set_body (3,"\treg_DATA(0) <= in_INSERT_DATA;"); + vhdl->set_body (3,"end if;"); + vhdl->set_body (2,"end if;"); + vhdl->set_body (0,""); + vhdl->set_body (1,"end if;"); + vhdl->set_body (0,"end process queue_write;"); log_printf(FUNC,Queue,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_vhdl_declaration.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_vhdl_declaration.cpp (revision 100) @@ -24,24 +24,39 @@ vhdl->set_signal ("reg_DATA ", "Tqueue"); - vhdl->set_signal ("reg_FULL ", 1); - vhdl->set_signal ("reg_EMPTY ", 1); - if (_param->_size_queue > 1) - { - vhdl->set_signal ("reg_PTR_READ ", log2(_param->_size_queue)); - vhdl->set_signal ("reg_PTR_WRITE ", log2(_param->_size_queue)); - } + vhdl->set_signal ("signal_READ ", 1); vhdl->set_signal ("signal_WRITE ", 1); - vhdl->set_signal ("signal_PTR_EQUAL ", 1); + vhdl->set_signal ("signal_EMPTY ", 1); + vhdl->set_signal ("signal_FULL ", 1); if (_param->_size_queue > 1) { - vhdl->set_signal ("signal_NEXT_PTR_READ ", log2(_param->_size_queue)); - vhdl->set_signal ("signal_NEXT_PTR_WRITE", log2(_param->_size_queue)); + vhdl->set_signal ("reg_PTR_READ ", log2(_param->_size_queue)); + vhdl->set_signal ("signal_NEXT_PTR_READ ", log2(_param->_size_queue)); + vhdl->set_signal ("signal_PTR_READ ", log2(_param->_size_queue)); + vhdl->set_signal ("signal_PTR_WRITE ", log2(_param->_size_queue)); } + if (_param->_nb_port_slot>1) + { + vhdl->set_signal ("reg_NB_ELT ", log2(_param->_size_queue+1)); + vhdl->set_signal ("signal_NEXT_NB_ELT ", log2(_param->_size_queue+1)); + for (uint32_t i=0; i<_param->_nb_port_slot; ++i) + vhdl->set_signal ("signal_SLOT_"+toString(i), log2(_param->_size_queue)); + } + else + { + if (_param->_size_queue > 1) + { + vhdl->set_signal ("reg_PTR_WRITE ", log2(_param->_size_queue)); + vhdl->set_signal ("signal_NEXT_PTR_WRITE", log2(_param->_size_queue)); + } + vhdl->set_signal ("reg_FULL ", 1); + vhdl->set_signal ("reg_EMPTY ", 1); vhdl->set_signal ("signal_NEXT_FULL ", 1); vhdl->set_signal ("signal_NEXT_EMPTY ", 1); - + vhdl->set_signal ("signal_PTR_EQUAL ", 1); + } + if (_param->_size_queue > 1) { Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.mkf (revision 100) @@ -3,5 +3,8 @@ # -all: _Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest +all: _Generic/Queue/SelfTest _Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest + +_Generic/Queue/SelfTest: + gmake all -C Generic/Queue/SelfTest _Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest: @@ -9,4 +12,5 @@ clean: + gmake clean -C Generic/Queue/SelfTest gmake clean -C Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest @@ -14,4 +18,5 @@ install: + gmake install -C Generic/Queue/SelfTest gmake install -C Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h (revision 100) @@ -299,54 +299,54 @@ // Exception Execution -# define EXCEPTION_IFETCH_NONE 0x00 // Fetch Unit generate none exception -# define EXCEPTION_IFETCH_INSTRUCTION_TLB 0x0a // ITLB miss -# define EXCEPTION_IFETCH_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables -# define EXCEPTION_IFETCH_BUS_ERROR 0x02 // Access at a invalid physical address - -# define EXCEPTION_DECOD_NONE 0x00 // none exception -# define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION 0x01 // Instruction is illegal (no implemented) -# define EXCEPTION_DECOD_SYSCALL 0x02 // System Call -//#define EXCEPTION_DECOD_TRAP 0x0e // L.trap or debug unit (note : must read SR !) -# define EXCEPTION_DECOD_INSTRUCTION_TLB 0x0a // ITLB miss -# define EXCEPTION_DECOD_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables -# define EXCEPTION_DECOD_BUS_ERROR 0x02 // Access at a invalid physical address - -# define EXCEPTION_ALU_NONE 0x00 // Functionnal unit generate none exception -# define EXCEPTION_ALU_RANGE 0x0b // -# define EXCEPTION_ALU_SPR_ACCESS_INVALID 0x12 // SPR present in ALU but not compatible privilege -# define EXCEPTION_ALU_SPR_ACCESS_MUST_READ 0x13 // SPR not present in ALU -# define EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE 0x14 // SPR not present in ALU - -# define EXCEPTION_MEMORY_NONE 0x00 // Load/Store generate none exception -# define EXCEPTION_MEMORY_ALIGNMENT 0x06 // Load/Store access is not aligned -# define EXCEPTION_MEMORY_DATA_TLB 0x09 // DTLB miss -# define EXCEPTION_MEMORY_DATA_PAGE 0x03 // No matching or page violation protection in pages tables -# define EXCEPTION_MEMORY_BUS_ERROR 0x02 // Access at a invalid physical address -# define EXCEPTION_MEMORY_MISS_SPECULATION 0x10 // Load miss speculation -# define EXCEPTION_MEMORY_LOAD_SPECULATIVE 0x11 // The load is speculative : write in register file, but don't commit - -# define EXCEPTION_CUSTOM_NONE 0x00 // Custom unit generate none exception -# define EXCEPTION_CUSTOM_CUST_0 0x19 // Reserved for custom exceptions -# define EXCEPTION_CUSTOM_CUST_1 0x1a // Reserved for custom exceptions -# define EXCEPTION_CUSTOM_CUST_2 0x1b // Reserved for custom exceptions -# define EXCEPTION_CUSTOM_CUST_3 0x1c // Reserved for custom exceptions -# define EXCEPTION_CUSTOM_CUST_4 0x1d // Reserved for custom exceptions -# define EXCEPTION_CUSTOM_CUST_5 0x1e // Reserved for custom exceptions -# define EXCEPTION_CUSTOM_CUST_6 0x1f // Reserved for custom exceptions - -# define EXCEPTION_USE_NONE 0x00 // -# define EXCEPTION_USE_ILLEGAL_INSTRUCTION 0x01 // illegal_instruction -# define EXCEPTION_USE_RANGE 0x02 // range -# define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT 0x03 // TLB miss, page fault, bus error, alignment -# define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT 0x04 // TLB miss, page fault, bus error -# define EXCEPTION_USE_SYSCALL 0x05 // syscall -# define EXCEPTION_USE_TRAP 0x06 // trap -# define EXCEPTION_USE_CUSTOM_0 0x07 // -# define EXCEPTION_USE_CUSTOM_1 0x08 // -# define EXCEPTION_USE_CUSTOM_2 0x09 // -# define EXCEPTION_USE_CUSTOM_3 0x0a // -# define EXCEPTION_USE_CUSTOM_4 0x0b // -# define EXCEPTION_USE_CUSTOM_5 0x0c // -# define EXCEPTION_USE_CUSTOM_6 0x0d // +# define EXCEPTION_IFETCH_NONE 0x00 // Fetch Unit generate none exception +# define EXCEPTION_IFETCH_INSTRUCTION_TLB 0x0a // ITLB miss +# define EXCEPTION_IFETCH_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables +# define EXCEPTION_IFETCH_BUS_ERROR 0x02 // Access at a invalid physical address + +# define EXCEPTION_DECOD_NONE 0x00 // none exception +# define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION 0x01 // Instruction is illegal (no implemented) +# define EXCEPTION_DECOD_SYSCALL 0x02 // System Call +//#define EXCEPTION_DECOD_TRAP 0x0e // L.trap or debug unit (note : must read SR !) +# define EXCEPTION_DECOD_INSTRUCTION_TLB 0x0a // ITLB miss +# define EXCEPTION_DECOD_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables +# define EXCEPTION_DECOD_BUS_ERROR 0x02 // Access at a invalid physical address + +# define EXCEPTION_ALU_NONE 0x00 // Functionnal unit generate none exception +# define EXCEPTION_ALU_RANGE 0x0b // +# define EXCEPTION_ALU_SPR_ACCESS_INVALID 0x12 // * SPR present in ALU but not compatible privilege +# define EXCEPTION_ALU_SPR_ACCESS_MUST_READ 0x13 // * SPR not present in ALU +# define EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE 0x14 // * SPR not present in ALU + +# define EXCEPTION_MEMORY_NONE 0x00 // Load/Store generate none exception +# define EXCEPTION_MEMORY_ALIGNMENT 0x06 // Load/Store access is not aligned +# define EXCEPTION_MEMORY_DATA_TLB 0x09 // DTLB miss +# define EXCEPTION_MEMORY_DATA_PAGE 0x03 // No matching or page violation protection in pages tables +# define EXCEPTION_MEMORY_BUS_ERROR 0x02 // Access at a invalid physical address +# define EXCEPTION_MEMORY_MISS_SPECULATION 0x10 // * Load miss speculation +# define EXCEPTION_MEMORY_LOAD_SPECULATIVE 0x11 // * The load is speculative : write in register file, but don't commit + +# define EXCEPTION_CUSTOM_NONE 0x00 // Custom unit generate none exception +# define EXCEPTION_CUSTOM_CUST_0 0x19 // Reserved for custom exceptions +# define EXCEPTION_CUSTOM_CUST_1 0x1a // Reserved for custom exceptions +# define EXCEPTION_CUSTOM_CUST_2 0x1b // Reserved for custom exceptions +# define EXCEPTION_CUSTOM_CUST_3 0x1c // Reserved for custom exceptions +# define EXCEPTION_CUSTOM_CUST_4 0x1d // Reserved for custom exceptions +# define EXCEPTION_CUSTOM_CUST_5 0x1e // Reserved for custom exceptions +# define EXCEPTION_CUSTOM_CUST_6 0x1f // Reserved for custom exceptions + +# define EXCEPTION_USE_NONE 0x00 // +# define EXCEPTION_USE_ILLEGAL_INSTRUCTION 0x01 // illegal_instruction +# define EXCEPTION_USE_RANGE 0x02 // range +# define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT 0x03 // TLB miss, page fault, bus error, alignment +# define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT 0x04 // TLB miss, page fault, bus error +# define EXCEPTION_USE_SYSCALL 0x05 // syscall +# define EXCEPTION_USE_TRAP 0x06 // trap +# define EXCEPTION_USE_CUSTOM_0 0x07 // +# define EXCEPTION_USE_CUSTOM_1 0x08 // +# define EXCEPTION_USE_CUSTOM_2 0x09 // +# define EXCEPTION_USE_CUSTOM_3 0x0a // +# define EXCEPTION_USE_CUSTOM_4 0x0b // +# define EXCEPTION_USE_CUSTOM_5 0x0c // +# define EXCEPTION_USE_CUSTOM_6 0x0d // # define exception_ifetch_to_exception_decod(x) x Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 100) @@ -10,10 +10,10 @@ #define MORPHEO_MAJOR_VERSION 0 #define MORPHEO_MINOR_VERSION 2 -#define MORPHEO_REVISION "98" +#define MORPHEO_REVISION "100" #define MORPHEO_CODENAME "Castor" -#define MORPHEO_DATE_DAY "31" -#define MORPHEO_DATE_MONTH "12" -#define MORPHEO_DATE_YEAR "2008" +#define MORPHEO_DATE_DAY "08" +#define MORPHEO_DATE_MONTH "01" +#define MORPHEO_DATE_YEAR "2009" #define MORPHEO_VERSION morpheo::toString(MORPHEO_MAJOR_VERSION)+"."+morpheo::toString(MORPHEO_MINOR_VERSION)+"."+morpheo::toString(MORPHEO_REVISION) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/mkf.info (revision 100) @@ -15,5 +15,5 @@ # build src directory content -#target_dep all Generic/Queue/SelfTest +target_dep all Generic/Queue/SelfTest #target_dep all Generic/RegisterFile/RegisterFile_Monolithic/SelfTest #target_dep all Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Types.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Types.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Types.cpp (revision 100) @@ -19,7 +19,7 @@ { case INSTRUCTION_L_ADD : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_ADD ,ORBIS32,1); - case INSTRUCTION_L_ADDC : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_ADD ,ORBIS32,1); + case INSTRUCTION_L_ADDC : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_ADDC ,ORBIS32,1); case INSTRUCTION_L_ADDI : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_ADD ,ORBIS32,1); - case INSTRUCTION_L_ADDIC : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_ADD ,ORBIS32,1); + case INSTRUCTION_L_ADDIC : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_ADDC ,ORBIS32,1); case INSTRUCTION_L_AND : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_AND ,ORBIS32,1); case INSTRUCTION_L_ANDI : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_AND ,ORBIS32,1); Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Debug.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Debug.h (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Debug.h (revision 100) @@ -47,9 +47,24 @@ extern debug_verbosity_t debug; - -void debug_init (void); -void debug_init (debug_verbosity_t level); + extern bool debug_cycle_test; + extern double debug_cycle_start; + extern double debug_cycle_stop ; + + void debug_init (void); + void debug_init (debug_verbosity_t level, + double cycle_start, + double cycle_stop ); + +#ifdef SYSTEMC +#define debug_test_simulation_time \ + (not debug_cycle_test or \ + ( (sc_simulation_time() >= debug_cycle_start) and \ + ((sc_simulation_time() <= debug_cycle_stop) or \ + (debug_cycle_stop == -1)))) +#else +#define debug_test_simulation_time true +#endif + #ifdef DEBUG - # define log_printf(level, component, func, str... ) \ do \ @@ -57,40 +72,41 @@ debug_init(); \ \ - if ((debug == DEBUG_ALL ) or \ - (DEBUG_ ## level == DEBUG_NONE) or \ - (( DEBUG_ ## level <= debug) and \ - ( DEBUG_ ## component == true )) ) \ - { \ - if (DEBUG_ ## level <= DEBUG_INFO) \ - { \ - msg("%s ",MSG_INFORMATION); \ - } \ - else \ - { \ - msg("%s ",MSG_DEBUG); \ - } \ + if (debug_test_simulation_time) \ + if ((debug == DEBUG_ALL ) or \ + (DEBUG_ ## level == DEBUG_NONE) or \ + (( DEBUG_ ## level <= debug) and \ + ( DEBUG_ ## component == true )) ) \ + { \ + if (DEBUG_ ## level <= DEBUG_INFO) \ + { \ + msg("%s ",MSG_INFORMATION); \ + } \ + else \ + { \ + msg("%s ",MSG_DEBUG); \ + } \ \ - if (debug >= DEBUG_ALL ) \ - { \ - switch (DEBUG_ ## level) \ - { \ - case DEBUG_NONE : msg(_("(none ) ")); break; \ - case DEBUG_INFO : msg(_("(information) ")); break; \ - case DEBUG_TRACE : msg(_("(trace ) ")); break; \ - case DEBUG_FUNC : msg(_("(function ) ")); break; \ - case DEBUG_ALL : msg(_("(all ) ")); break; \ - default : msg(_("(undefine ) ")); break; \ - } \ - } \ - if (debug >= DEBUG_FUNC) \ - { \ - msg( "<%s> " ,func); \ - msg(_("In file %s, "),__FILE__); \ - msg(_("at line %d " ),__LINE__); \ - msg( ": " ); \ - } \ - msg(str); \ - msg("\n"); \ - } \ + if (debug >= DEBUG_ALL ) \ + { \ + switch (DEBUG_ ## level) \ + { \ + case DEBUG_NONE : msg(_("(none ) ")); break; \ + case DEBUG_INFO : msg(_("(information) ")); break; \ + case DEBUG_TRACE : msg(_("(trace ) ")); break; \ + case DEBUG_FUNC : msg(_("(function ) ")); break; \ + case DEBUG_ALL : msg(_("(all ) ")); break; \ + default : msg(_("(undefine ) ")); break; \ + } \ + } \ + if (debug >= DEBUG_FUNC) \ + { \ + msg( "<%s> " ,func); \ + msg(_("In file %s, "),__FILE__); \ + msg(_("at line %d " ),__LINE__); \ + msg( ": " ); \ + } \ + msg(str); \ + msg("\n"); \ + } \ } while(0) Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Filename.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Filename.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Filename.h (revision 100) @@ -0,0 +1,91 @@ +#ifndef Morpheo_Filename_h +#define Morpheo_Filename_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/ToString.h" +#include +#include +#include +#include + +namespace morpheo { + + std::string filename (std::string directory, + std::string filename_prefix, + std::string filename_suffix, + std::string extension, + bool with_date, + bool with_pid, + bool overwrite + ) + { + std::string str = directory+"/"+filename_prefix; + + if (with_date) + { + time_t current_time; + time (¤t_time); + + struct tm * _localtime = localtime (¤t_time); + + int year = 1900+_localtime->tm_year; + int mon = 1+_localtime->tm_mon ; + int mday = _localtime->tm_mday; + int hour = _localtime->tm_hour; + int min = _localtime->tm_min ; + int sec = _localtime->tm_sec ; + + str+= "_"+ toString(year) + +((mon <10)?"0":"") + toString(mon ) + +((mday<10)?"0":"") + toString(mday) + +"_"+((hour<10)?"0":"") + toString(hour) + +((min <10)?"0":"") + toString(min ) + +((sec <10)?"0":"") + toString(sec ); + } + + if (with_pid) + { + str+="_"+toString(getpid()); + } + + str+=filename_suffix; + + if (not overwrite) + { + int it = 0; + bool find; + do + { + find = false; + + std::ifstream inputStream; + std::string name = str+((it!=0)?("_"+toString(it)):""); + + inputStream.open(name.c_str(),std::ios_base::in); + + if (inputStream) + { + find = true; + it ++; + } + inputStream.close(); + } + while (find); + + str+= str+((it!=0)?("_"+toString(it)):""); + } + + str+="."+extension; + + return str; + } + +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Common/src/Debug.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/src/Debug.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Common/src/Debug.cpp (revision 100) @@ -15,4 +15,7 @@ #endif debug_verbosity_t debug; +bool debug_cycle_test; +double debug_cycle_start; +double debug_cycle_stop ; #undef FUNCTION @@ -24,6 +27,6 @@ { debug = DEBUG; - -// debug_initialized = true; + debug_cycle_test = false; +// debug_initialized = true; } #endif @@ -32,5 +35,7 @@ #undef FUNCTION #define FUNCTION "debug_init" -void debug_init (debug_verbosity_t level) +void debug_init (debug_verbosity_t level, + double cycle_start, + double cycle_stop ) { #ifdef DEBUG @@ -39,5 +44,13 @@ // Take min debug = (level < DEBUG)?level:DEBUG; - + +#ifdef SYSTEMC + debug_cycle_test = (cycle_stop > cycle_start) or (cycle_stop == -1); + debug_cycle_start = cycle_start; + debug_cycle_stop = cycle_stop; +#else + debug_cycle_test = false; +#endif + debug_initialized = true; } Index: trunk/IPs/systemC/processor/Morpheo/Common/src/Message.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/src/Message.cpp (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Common/src/Message.cpp (revision 100) @@ -8,8 +8,7 @@ #include "Common/include/Debug.h" #include "Common/include/Environment.h" -#include "Common/include/ToString.h" #include "Common/include/ErrorMorpheo.h" +#include "Common/include/Filename.h" #include -#include namespace morpheo { @@ -39,5 +38,11 @@ { // if the file is not define, take pid. - std::string filename = directory+"/Morpheo_"+((file!="")?file:toString(getpid()))+".log"; + std::string filename = morpheo::filename(directory, + "Morpheo", + "", + "log", + (file==""), + (file==""), + true); log_stream = fopen (filename.c_str(), "w"); Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-01_tree.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-01_tree.tex (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-01_tree.tex (revision 100) @@ -0,0 +1,36 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Arborescence}\label{tree} + +Dans le répertoire contenant le projet, il y a les répertoires suivants : +\begin{description} +\item[IPs/systemC/processor/Morpheo/Documentation/ :] Contiens différents documents décrivant le projet, dont ce document. +\item[IPs/systemC/processor/Morpheo/Behavioural/ :] Contiens toutes les classes décrivant le comportement interne de Morpheo. +\item[IPs/systemC/processor/Morpheo/Behavioural/include/ :] Contiens les définitions des structures internes nécessaires à la réalisation du générateur. (Il contient aussi la génération de statistiques, la génération des fichiers au format XML \dots)\\ + \begin{description} + \item [Parameters.h :] Contiens la classe {\it Parameters}, cette classe définit les paramètres constants et globaux. + \item [Vhdl.h :] Contiens la classe {\it Vhdl}. + \item [Constants.h :] Contiens toutes les constantes nécessaires au processeur (par exemple les Codes Opération des instructions). + \item [Types.h :] Contiens les types des signaux transitant entre deux composants. + \end{description} +\item[IPs/systemC/processor/Morpheo/Behavioural/\dots/Component :] Chaque composant est inclus dans un répertoire spécifique. De plus, pour éviter toute collision de nom, chaque répertoire équivaut à un espace de nom (namespace). +\item[IPs/systemC/processor/Morpheo/Behavioural/\dots/Component/include :]~\\ + \begin{description} + \item [Parameters.h :] Contient la classe {\it Parameters}, elle dérive de la classe contenue dans le fichier le répertoire {\it \dots/Behavioural/include/}. Elle définit les paramètres locaux au composant. Par exemple la taille de la file interne \dots. + \item [Component.h :] Contiens la classe {\it Component}. Elle définit l'interface, les registres ainsi que les méthodes du modèle systemC. + \item [Types.h :] Contiens les types spéciaux de ce composant. + \end{description} +\item[IPs/systemC/processor/Morpheo/Behavioural/\dots/Component/src :]~\\ + \begin{description} + \item [Component.cpp :] Définis les méthodes de construction et destruction. La construction spécifie les méthodes internes ainsi que les listes de sensibilités. + \item [Component\_transition.cpp :] Définis la fonction de transition du composant. Il s'agit de l'écriture dans les registres. + \item [Component\_genMoore.cpp :] Définis la fonction de génération de Moore. C'est-à-dire les signaux de sortie qui ne dépendent que de l'état courant du composant. + \item [Component\_genMealy\_XXX.cpp :] Définis une fonction de génération de Mealy. C'est à dire les signaux de sortie qui dépendant aussi bien de l'état courant du composant que de l'entrée de composant. Il peut avoir plusieurs fonctions de mealy par composant. + \item [Component\_vhdl.cpp :] Génère le modèle comportemental VHDL d'une instance du composant. + \item [Component\_vhdl\_declaration.cpp :] Définis les types et signaux nécessaires à la description comportementale en VHDL du composant. + \item [Component\_vhdl\_body.cpp :] Décris le comportement VHDL du composant. + \end{description} +\item[IPs/systemC/processor/Morpheo/Behavioural/\dots/Component/Selftest :] Test le composant. +\end{description} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-02_vhdl_declaration.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-02_vhdl_declaration.tex (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-02_vhdl_declaration.tex (revision 100) @@ -0,0 +1,169 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{VHDL : déclaration}\label{vhdl_declaration} + +Les déclarations se font dans le fichier {\it Component\_vhdl\_declaration.cpp}. + +\subSection{Interfaces} +L'interface est définie dans le modèle SystemC. Il n'est pas nécessaire de la redéfinir pour le modèle VHDL. + +La nomenclature est la suivante : +\begin{itemize} +\item La direction en minuscule ({\it in}, {\it out}). +\item Le nom de l'interface en majuscule ({\it READ}, {\it PUSH}, \dots). +\item Le numéro de l'interface (la première interface aura le numéro 0. S'il n'y a qu'une interface, celle-ci aura tout de même le numéro 0). +\item Le nom du signal en majuscule ({\it VAL}, {\it ADDRESS}, \dots). +\end{itemize} + +Par exemple pour la 2 ème interface de lecture d'un banc de registre : +\lstparam{VHDL} +\begin{lstlisting} + in_READ_1_VAL : in std_logic; +out_READ_1_ACK : out std_logic; + in_READ_1_ADDRESS : in std_logic_vector(8 downto 0); +out_READ_1_DATA : out std_logic_vector(31 downto 0); +\end{lstlisting} + +Chaque composant (aussi bien combinatoire que séquentielle) possède un signal d'horloge et un signal de reset. (Ce dernier est actif à l'état bas). Ils ont tous les deux le même nom quelque soit le composant. +\lstparam{VHDL} +\begin{lstlisting} + in_CLOCK : in std_logic; + in_NRESET : in std_logic; +\end{lstlisting} + +\subSection{Types} + +Le type de base utilisé est le {\it std\_logic\_vector} (ou std\_logic si le vecteur est sur un seul bit). Pour cela on utilise la fonction suivante : + +\lstparam{C++} +\begin{lstlisting} +std::string std_logic (uint32_t size); +\end{lstlisting} + +Pour accéder à une partie du vecteur, on utilise la fonction {\it std\_logic\_range}. Elle a les prototypes suivant : +\lstparam{C++} +\begin{lstlisting} +std::string std_logic_range (uint32_t size, + uint32_t max , + uint32_t min); +std::string std_logic_range (uint32_t max , + uint32_t min); +std::string std_logic_range (uint32_t size); +std::string _std_logic_range (uint32_t size, + uint32_t max , + uint32_t min); +std::string _std_logic_range (uint32_t max , + uint32_t min); +std::string _std_logic_range (uint32_t size); +\end{lstlisting} + +La première fonction fait un test sur la taille que la seconde ne fait pas. +L'argument de la troisième définit la taille (ce qui implique que la borne minimum est 0 et la borne maximum est size-1). +Toutes les fonctions préfixées par un underscore n'effectuent pas de test sur les bornes. + +Par exemple : +\begin{verbatim} + std_logic_range(4) renvoie "(3 downto 0)". + std_logic_range(1) renvoie "(0)". +_std_logic_range(1) renvoie "(0 downto 0)". +\end{verbatim} + +Pour les types plus complexes, la classe {\it Vhdl} possède une méthode générique. Le premier argument est le nom du type le second est le type. + +\lstparam{C++} +\begin{lstlisting} +void set_type (std::string name, + std::string type); +\end{lstlisting} + +L'exemple suivant définit un type représentant un tableau de {\it nb\_word} mots de {\it size\_word} bit chacun : +\lstparam{C++} +\begin{lstlisting} +vhdl->set_type ("Tregfile", + "array "+std_logic_range(nb_word)+" of "+std_logic(size_word)); +\end{lstlisting} + +\subSection{Constantes} + +La déclaration de constante, ce fait avec la méthode {\it set\_constant} de la classe {\it Vhdl}. Les différentes surcharges de cette méthode est le type des arguments {\it type} et {\it init}. + +\lstparam{C++} +\begin{lstlisting} +void set_constant (std::string name, + std::string type, + std::string init); +void set_constant (std::string name, + uint32_t size, + std::string init); +void set_constant (std::string name, + uint32_t size, + uint32_t init); +\end{lstlisting} + +Par exemple pour coder les états d'un automate à 5 états en One Hot : +\lstparam{C++} +\begin{lstlisting} +vhdl->set_constant ("State_idle",5,1); +\end{lstlisting} + +Dans le cas de signaux de type {\it std\_logic}, au lieu de déclarer des constantes, il existe deux fonctions permettant d'utiliser des constantes directement dans le corps du composant. +La première est {\it std\_logic\_others}. Elle permet de définir des constantes dont soit les bits sont à plein un soit à plein zéro. + +\lstparam{C++} +\begin{lstlisting} +std::string std_logic_others (uint32_t size, + bool cst ); +\end{lstlisting} + +Pour toutes les autres constantes, la méthode {\it std\_logic\_conv} transforme un entier en {\it std\_logic\_vector}. + +\lstparam{C++} +\begin{lstlisting} +std::string std_logic_conv (uint32_t size, + std::string value); +std::string std_logic_conv (uint32_t size, + uint32_t value); +\end{lstlisting} + + +\subSection{Signaux internes} + +Les signaux internes sont définis grâce à la méthode {\it set\_signal}. Le premier argument est le nom du signal. Le second est soit un type soit une taille (dans le cas où le type est un {\it std\_logic\_vector}). +\lstparam{C++} +\begin{lstlisting} +void set_signal (std::string name, + std::string type); +void set_signal (std::string name, + uint32_t size); +\end{lstlisting} + +La méthode est également surchargée si le signal a besoin d'une initialisation. + +\lstparam{C++} +\begin{lstlisting} +void set_signal (std::string name, + std::string type, + std::string init); +void set_signal (std::string name, + uint32_t size, + std::string init); +void set_signal (std::string name, + uint32_t size, + uint32_t init); +\end{lstlisting} + +En vhdl il est possible de renommer un champ d'un signal. Ceci se fait à l'aide de la fonction {\it set\_alias}. Elle prend 4 arguments. Le premier étant le nom du signal après le renommage. Le second est soit le type, soit la taille du {\it std\_logic\_vector} du signal renommé. Les deux derniers concernés le signal à renommé : le nom de ce dernier ainsi que l'intervalle. Pour le dernier paramètre, il est recommandé d'utiliser la fonction {\it std\_logic\_range}. + +\lstparam{C++} +\begin{lstlisting} +void set_alias (std::string name1 , + std::string type1 , + std::string name2 , + std::string range2); +void set_alias (std::string name1 , + uint32_t size1 , + std::string name2 , + std::string range2); +\end{lstlisting} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-03_vhdl_body.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-03_vhdl_body.tex (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-03_vhdl_body.tex (revision 100) @@ -0,0 +1,24 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{VHDL : comportement}\label{vhdl_body} + +Le comportement du composant est défini dans le fichier {\it Component\_vhdl\_body.cpp}. + +Il n'y a pas de fonction aidant à l'écriture du Vhdl. +La méthode {\it set\_body} permet de définir une ligne de code VHDL. Un retour à la ligne est automatiquement inséré. Le premier argument est pour l'indentation. +\lstparam{C++} +\begin{lstlisting} +void set_body (uint32_t depth, + std::string text ); +void set_body (std::string text ); +\end{lstlisting} + +Pour les commentaires, il y a la fonction {\it set\_comment}. +\lstparam{C++} +\begin{lstlisting} +void set_comment (uint32_t depth, + std::string text ); +void set_comment (std::string text ); +\end{lstlisting} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-04_vhdl_structural.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-04_vhdl_structural.tex (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-04_vhdl_structural.tex (revision 100) @@ -0,0 +1,139 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{VHDL : structurelle}\label{vhdl_structural} + +\subSection{Description du fichier {\it Component\_vhdl.cpp}} +Les modèles systemC structurels sont des modèles qui instancient d'autres modèles. Il n'y a pas de description comportementale. Ces modèles sont générés automatiquement. +Par contre, les modèles systemC comportementaux peuvent être décrit par un modèle VHDL mixte (incluant une description comportementale et des instances d'autre composant). + +Les modèles génériques sont dans le répertoire {\it IPs/systemC/processor/Morpheo/Behavioural/Generic}. + +\lstparam{C++} +\begin{lstlisting}[caption={Component\_vhdl.cpp}, label=component_vhdl.cpp] + void component::vhdl (void) + { + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + }; +\end{lstlisting} + + +La première étape est d'éditer le fichier {\it Component\_vhdl.cpp}. Le listing \ref{component_vhdl.cpp} représente le contenu de ce fichier. +\begin{itemize} +\item Ligne 3 : Déclaration et construction de la variable {\it vhdl} qui est du type {\it Vhdl}. +\item Ligne 5 : Ajout dans le modèle VHDL des interfaces présentes dans le modèle SystemC. (cf fichiers Component.h). +\item Ligne 6 : Ajout dans le modèle VHDL des composants internes dans le modèle SystemC. (cf fichiers Component.h et Component\_allocation.cpp). +\item Ligne 8 : Ajout dans le modèle VHDL des déclarations définit dans le fichiers Component\_vhdl\_declaration.cpp (cf section \ref{vhdl_declaration}). +\item Ligne 9 : Ajout dans le modèle VHDL de la description comportemental définit dans le fichiers Component\_vhdl\_body.cpp (cf section \ref{vhdl_body}). +\item Ligne 11 : Génération des fichiers VHDL. Le nom du fichier est construit à partir du nom fourni lors de la construction de la variable {\it vhdl}. +\item Ligne 13 : Destruction de l'objet. +\end{itemize} + +Pour la suite, nous allons supposer l'instanciation d'une FIFO. + +\subSection{Ajout d'une instance} + +Dans le fichier Component\_vhdl.cpp : +\begin{enumerate} +\item Inclure la définition de la classe désirée. +\lstparam{C++} +\begin{lstlisting} +#include "Behavioural/Generic/Queue/include/Queue.h" +\end{lstlisting} +\item Creer les paramètres du modèle. +\lstparam{C++} +\begin{lstlisting} + morpheo::behavioural::generic::queue::Parameters * param_queue; + param_queue = new morpheo::behavioural::generic::queue::Parameters + (16, //size_queue + 32);//size_data +\end{lstlisting} +\item Creer le modèle +\lstparam{C++} +\begin{lstlisting} + morpheo::behavioural::generic::queue::Queue * queue; + std::string queue_name = _name + "_queue"; + + queue = new morpheo::behavioural::generic::queue::Queue + (queue_name.c_str() // nom du modèle +#ifdef STATISTICS + ,NULL // Pas paramètres pour les statistiques +#endif + ,param_queue // Paramètres de la file + ,USE_VHDL); // Utilisation du modèle VHDL +\end{lstlisting} +\item Inclure le modèle dans la liste des composants internes +\lstparam{C++} +\begin{lstlisting} + _component->set_component(queue->_component +#ifdef POSITION + , 20, 20, 20, 20 + // Coordonée pour l'outil de visualisation +#endif + , INSTANCE_LIBRARY + // Instancier uniquement les librairies + ); +\end{lstlisting} +\item indiquer dans le fichier Makefile.deps que le composant dépend de ce modèle. +\lstparam{make} +\begin{lstlisting} +# Inclure les dépendances +ifndef Queue +include $(DIR_MORPHEO)/Behavioural/Generic/Queue/Makefile.deps +endif + +# Inclure les librairies +Component_LIBRARY = -lComponent \ + $(Queue_LIBRARY) + +# Les chemins vers les librairies +Component_DIR_LIBRARY = -L$(Component_DIR)/lib \ + $(Queue_DIR_LIBRARY) + +# Construction de la librairie ``Component'' +Component_library : + @\ + $(MAKE) Queue_library; \ + $(MAKE) --directory=$(Component_DIR) --makefile=Makefile; + +# Effacement des fichiers générés +Component_library_clean : + @\ + $(MAKE) Queue_library_clean; \ + $(MAKE) --directory=$(Component_DIR) --makefile=Makefile clean; +\end{lstlisting} +\end{enumerate} + +\subSection{Instanciation} +L'instanciation ce fait comme avec des composants VHDL classiques : +\lstparam{C++} +\begin{lstlisting} + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Instance queue "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + + vhdl->set_body (0,"instance_"+_name+"_queue : "+_name+"_queue"); + vhdl->set_body (0,"port map ("); + vhdl->set_body (1," in_CLOCK \t=>\t in_CLOCK "); + vhdl->set_body (1,", in_NRESET \t=>\t in_NRESET"); + vhdl->set_body (1,", in_INSERT_VAL \t=>\tinternal_QUEUE_INSERT_VAL"); + vhdl->set_body (1,",out_INSERT_ACK \t=>\tinternal_QUEUE_INSERT_ACK"); + vhdl->set_body (1,", in_INSERT_DATA \t=>\tinternal_QUEUE_INSERT_DATA"); + vhdl->set_body (1,",out_RETIRE_VAL \t=>\tinternal_QUEUE_RETIRE_VAL"); + vhdl->set_body (1,", in_RETIRE_ACK \t=>\tinternal_QUEUE_RETIRE_ACK"); + vhdl->set_body (1,",out_RETIRE_DATA \t=>\tinternal_QUEUE_RETIRE_DATA"); + vhdl->set_body (0,");"); +\end{lstlisting} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-05_01_registerfile.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-05_01_registerfile.tex (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-05_01_registerfile.tex (revision 100) @@ -0,0 +1,173 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\subSection{Banc de Registres Monolithique} + +\subsubSection{Fichier RegisterFile\_Monolithic\_vhdl.cpp} + +\lstparam{C++} +\begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl.cpp}] +void RegisterFile_Monolithic::vhdl (void) +{ + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port (vhdl); + _component ->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; +}; +\end{lstlisting} + + +\subsubSection{Fichier RegisterFile\_Monolithic\_vhdl\_declaration.cpp} + +\lstparam{C++} +\begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl\_declaration.cpp}] +void RegisterFile_Monolithic::vhdl_declaration (Vhdl * & vhdl) +{ + vhdl->set_type ("Tregfile", "array " + std_logic_range(_param->_nb_word,true)+ + " of "+ + std_logic(_param->_size_word)); + + vhdl->set_signal ("reg_DATA", "Tregfile"); +}; +\end{lstlisting} + +\subsubSection{Fichier RegisterFile\_Monolithic\_vhdl\_body.cpp} + +\lstparam{C++} +\begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl\_body.cpp}] +void RegisterFile_Monolithic::vhdl_body (Vhdl * & vhdl) +{ + vhdl->set_body (0,""); + vhdl->set_comment(0,"---------------------------------------------------"); + vhdl->set_comment(0," Ack"); + vhdl->set_comment(0,"---------------------------------------------------"); + vhdl->set_body (0,""); + + for (uint32_t i = 0; i < _param->_nb_port_read; i++) + vhdl->set_body (0,"out_READ_"+toString(i)+"_ACK <= '1';"); + for (uint32_t i = 0; i < _param->_nb_port_write; i++) + vhdl->set_body (0,"out_WRITE_"+toString(i)+"_ACK <= '1';"); + + vhdl->set_body (0,""); + vhdl->set_comment(0,"---------------------------------------------------"); + vhdl->set_comment(0," Read RegisterFile"); + vhdl->set_comment(0,"---------------------------------------------------"); + vhdl->set_body (0,""); + + for (uint32_t i = 0; i < _param->_nb_port_read; i++) + { + std::string str_address; + if (_param->_have_port_address) + str_address = "conv_integer(in_READ_"+toString(i)+"_ADDRESS)"; + else + str_address = "0"; + + vhdl->set_body (0,"out_READ_"+toString(i)+"_DATA <= reg_DATA ("+str_address+ + ") when in_READ_"+toString(i)+"_VAL = '1' else "+ + std_logic_others(_param->_size_word,0)+";"); + } + + vhdl->set_body (0,""); + vhdl->set_comment(0,"---------------------------------------------------"); + vhdl->set_comment(0," Write RegisterFile"); + vhdl->set_comment(0,"---------------------------------------------------"); + vhdl->set_body (0,""); + + vhdl->set_body (0,"RegisterFile_write: process (in_CLOCK)"); + vhdl->set_body (0,"begin -- process RegisterFile_write"); + vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); + + for (uint32_t i = 0; i < _param->_nb_port_write; i++) + { + std::string str_address; + if (_param->_have_port_address) + str_address = "conv_integer(in_WRITE_"+toString(i)+"_ADDRESS)"; + else + str_address = "0"; + + vhdl->set_body (2,"if (in_WRITE_"+toString(i)+"_VAL = '1') then"); + vhdl->set_body (3,"reg_DATA("+str_address+") <= in_WRITE_"+toString(i)+"_DATA;"); + vhdl->set_body (2,"end if;"); + } + + vhdl->set_body (1,"end if;"); + vhdl->set_body (0,"end process RegisterFile_write;"); +}; +\end{lstlisting} + +\subsubSection{Fichier RegisterFile\_Monolithic.vhdl} + +\lstparam{VHDL} +\begin{lstlisting}[caption={RegisterFile\_Monolithic.cpp}] + library ieee; + use ieee.numeric_bit.all; + use ieee.numeric_std.all; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_misc.all; +--use ieee.std_logic_signed.all; + use ieee.std_logic_unsigned.all; +--use ieee.std_logic_textio.all; + + +library work; +use work.RegisterFile_Monolithic_Pack.all; + + +entity RegisterFile_Monolithic is + port ( in_CLOCK : in std_logic; + in_NRESET : in std_logic; + in_READ_0_VAL : in std_logic; + out_READ_0_ACK : out std_logic; + in_READ_0_ADDRESS : in std_logic_vector(8 downto 0); + out_READ_0_DATA : out std_logic_vector(31 downto 0); + in_WRITE_0_VAL : in std_logic; + out_WRITE_0_ACK : out std_logic; + in_WRITE_0_ADDRESS: in std_logic_vector(8 downto 0); + in_WRITE_0_DATA : in std_logic_vector(31 downto 0) + ); +end RegisterFile_Monolithic; + +architecture behavioural of RegisterFile_Monolithic is + type Tregfile is array (511 downto 0) of std_logic_vector(31 downto 0); + + signal reg_DATA : Tregfile; + +begin + ----------------------------------------------------- + -- Ackitement + ----------------------------------------------------- + + out_READ_0_ACK <= '1'; + out_WRITE_0_ACK <= '1'; + + ----------------------------------------------------- + -- Read RegisterFile + ----------------------------------------------------- + + out_READ_0_DATA <= reg_DATA (conv_integer(in_READ_0_ADDRESS)) + when in_READ_0_VAL = '1' + else (others => '0'); + + ----------------------------------------------------- + -- Write RegisterFile + ----------------------------------------------------- + + RegisterFile_write: process (in_CLOCK) + begin -- process RegisterFile_write + if in_CLOCK'event and in_CLOCK = '1' then + if (in_WRITE_0_VAL = '1') then + reg_DATA(conv_integer(in_WRITE_0_ADDRESS)) <= in_WRITE_0_DATA; + end if; + end if; + end process RegisterFile_write; +end behavioural; +\end{lstlisting} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-05_02_execute_queue.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-05_02_execute_queue.tex (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-05_02_execute_queue.tex (revision 100) @@ -0,0 +1,422 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\subSection{Tampon entre la boucle d'exécutione et le buffer de réordonnancement} + +\subsubSection{Fichier Execute\_queue\_vhdl.cpp} + +\lstparam{C++} +\begin{lstlisting}[caption={Execute\_queue\_vhdl.cpp}] +void Execute_queue::vhdl (void) +{ + morpheo::behavioural::generic::queue::Parameters * param_queue; + + param_queue = new morpheo::behavioural::generic::queue::Parameters + (_param->_size_queue, + _param->_size_internal_queue + ); + + morpheo::behavioural::generic::queue::Queue * queue; + + std::string queue_name = _name + "_queue"; + queue = new morpheo::behavioural::generic::queue::Queue + (queue_name.c_str() +#ifdef STATISTICS + ,NULL +#endif + ,param_queue + ,USE_VHDL); + + _component->set_component(queue->_component +#ifdef POSITION + , 50, 50, 50, 50 +#endif + , INSTANCE_LIBRARY + ); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; +}; +\end{lstlisting} + +\subsubSection{Fichier Execute\_queue\_vhdl\_declaration.cpp} + +\lstparam{C++} +\begin{lstlisting}[caption={Execute\_queue\_vhdl\_declaration.cpp}] +void Execute_queue::vhdl_declaration (Vhdl * & vhdl) +{ + vhdl->set_alias ("internal_QUEUE_INSERT_VAL ", + 1, + " in_EXECUTE_QUEUE_IN_VAL", + std_logic_range(1)); + vhdl->set_alias ("internal_QUEUE_INSERT_ACK ", + 1, + "out_EXECUTE_QUEUE_IN_ACK", + std_logic_range(1)); + vhdl->set_signal ("internal_QUEUE_INSERT_DATA", + _param->_size_internal_queue); + vhdl->set_signal ("internal_QUEUE_RETIRE_DATA", + _param->_size_internal_queue); + vhdl->set_alias ("internal_QUEUE_RETIRE_VAL ", + 1, + "out_EXECUTE_QUEUE_OUT_VAL", + std_logic_range(1)); + vhdl->set_alias ("internal_QUEUE_RETIRE_ACK ", + 1, + " in_EXECUTE_QUEUE_OUT_ACK", + std_logic_range(1)); + + uint32_t min = 0; + uint32_t max, size; + + if(_param->_have_port_context_id ) + { + size = _param->_size_context_id; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_CONTEXT_ID ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + } + if(_param->_have_port_front_end_id ) + { + size = _param->_size_front_end_id; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_FRONT_END_ID ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + } + if(_param->_have_port_ooo_engine_id ) + { + size = _param->_size_ooo_engine_id; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + } + if(_param->_have_port_rob_ptr) + { + size = _param->_size_rob_ptr; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_PACKET_ID ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + } + + size = _param->_size_special_data; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_FLAGS ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + + size = _param->_size_exception; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_EXCEPTION ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + + size = 1; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + + size = _param->_size_instruction_address; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_ADDRESS ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + + size = _param->_size_general_data; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_DATA ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; +}; +\end{lstlisting} + +\subsubSection{Fichier Execute\_queue\_vhdl\_body.cpp} + +\lstparam{C++} +\begin{lstlisting}[caption={Execute\_queue\_vhdl\_body.cpp}] +void Execute_queue::vhdl_body (Vhdl * & vhdl) +{ + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Instance queue "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + + vhdl->set_body (0,"instance_"+_name+"_queue : "+_name+"_queue"); + vhdl->set_body (0,"port map ("); + vhdl->set_body (1," in_CLOCK \t=>\t in_CLOCK "); + vhdl->set_body (1,", in_NRESET \t=>\t in_NRESET"); + vhdl->set_body (1,", in_INSERT_VAL \t=>\tinternal_QUEUE_INSERT_VAL"); + vhdl->set_body (1,",out_INSERT_ACK \t=>\tinternal_QUEUE_INSERT_ACK"); + vhdl->set_body (1,", in_INSERT_DATA \t=>\tinternal_QUEUE_INSERT_DATA"); + vhdl->set_body (1,",out_RETIRE_VAL \t=>\tinternal_QUEUE_RETIRE_VAL"); + vhdl->set_body (1,", in_RETIRE_ACK \t=>\tinternal_QUEUE_RETIRE_ACK"); + vhdl->set_body (1,",out_RETIRE_DATA \t=>\tinternal_QUEUE_RETIRE_DATA"); + vhdl->set_body (0,");"); + + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Input Buffer "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + + { + uint32_t min = 0; + uint32_t max, size; + uint32_t size_queue = _param->_size_internal_queue; + + if(_param->_have_port_context_id ) + { + size = _param->_size_context_id; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_CONTEXT_ID;"); + min = max+1; + } + if(_param->_have_port_front_end_id ) + { + size = _param->_size_front_end_id; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_FRONT_END_ID;"); + min = max+1; + } + if(_param->_have_port_ooo_engine_id ) + { + size = _param->_size_ooo_engine_id; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID;"); + min = max+1; + } + if(_param->_have_port_rob_ptr) + { + size = _param->_size_rob_ptr; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_PACKET_ID;"); + min = max+1; + } + + size = _param->_size_special_data; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_FLAGS;"); + min = max+1; + + size = _param->_size_exception; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_EXCEPTION;"); + min = max+1; + + size = 1; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_NO_SEQUENCE;"); + min = max+1; + + size = _param->_size_instruction_address; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_ADDRESS;"); + min = max+1; + + size = _param->_size_general_data; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_DATA;"); + min = max+1; + } + + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Output Buffer "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + + if(_param->_have_port_context_id) + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID "+ + " <= internal_EXECUTE_QUEUE_OUT_CONTEXT_ID ;"); + if(_param->_have_port_front_end_id) + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID "+ + " <= internal_EXECUTE_QUEUE_OUT_FRONT_END_ID ;"); + if(_param->_have_port_ooo_engine_id) + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID"+ + " <= internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID;"); + if(_param->_have_port_rob_ptr) + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_PACKET_ID "+ + " <= internal_EXECUTE_QUEUE_OUT_PACKET_ID ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_FLAGS "+ + " <= internal_EXECUTE_QUEUE_OUT_FLAGS ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_EXCEPTION "+ + " <= internal_EXECUTE_QUEUE_OUT_EXCEPTION ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE "+ + " <= internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_ADDRESS "+ + " <= internal_EXECUTE_QUEUE_OUT_ADDRESS ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_DATA "+ + " <= internal_EXECUTE_QUEUE_OUT_DATA ;"); +}; +\end{lstlisting} + +\subsubSection{Fichier Execute\_queue.vhdl} + +\lstparam{VHDL} +\begin{lstlisting}[caption={Execute\_queue.cpp}] +library ieee; + use ieee.numeric_bit.all; + use ieee.numeric_std.all; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_misc.all; +--use ieee.std_logic_signed.all; + use ieee.std_logic_unsigned.all; +--use ieee.std_logic_textio.all; + +library work; +use work.Execute_queue_0_Pack.all; +use work.Execute_queue_0_queue_Pack.all; + +entity Execute_queue_0 is + port ( + in_CLOCK : in std_logic; + in_NRESET : in std_logic; + in_EXECUTE_QUEUE_IN_VAL : in std_logic; + out_EXECUTE_QUEUE_IN_ACK : out std_logic; + in_EXECUTE_QUEUE_IN_CONTEXT_ID : in std_logic; + in_EXECUTE_QUEUE_IN_FRONT_END_ID : in std_logic; + in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID : in std_logic; + in_EXECUTE_QUEUE_IN_PACKET_ID : in std_logic_vector(5 downto 0); + in_EXECUTE_QUEUE_IN_FLAGS : in std_logic_vector(1 downto 0); + in_EXECUTE_QUEUE_IN_EXCEPTION : in std_logic_vector(4 downto 0); + in_EXECUTE_QUEUE_IN_NO_SEQUENCE : in std_logic; + in_EXECUTE_QUEUE_IN_ADDRESS : in std_logic_vector(31 downto 0); + in_EXECUTE_QUEUE_IN_DATA : in std_logic_vector(31 downto 0); + out_EXECUTE_QUEUE_OUT_VAL : out std_logic; + in_EXECUTE_QUEUE_OUT_ACK : in std_logic; + out_EXECUTE_QUEUE_OUT_CONTEXT_ID : out std_logic; + out_EXECUTE_QUEUE_OUT_FRONT_END_ID : out std_logic; + out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID : out std_logic; + out_EXECUTE_QUEUE_OUT_PACKET_ID : out std_logic_vector(5 downto 0); + out_EXECUTE_QUEUE_OUT_FLAGS : out std_logic_vector(1 downto 0); + out_EXECUTE_QUEUE_OUT_EXCEPTION : out std_logic_vector(4 downto 0); + out_EXECUTE_QUEUE_OUT_NO_SEQUENCE : out std_logic; + out_EXECUTE_QUEUE_OUT_ADDRESS : out std_logic_vector(31 downto 0); + out_EXECUTE_QUEUE_OUT_DATA : out std_logic_vector(31 downto 0) + ); +end Execute_queue_0; + +architecture behavioural of Execute_queue_0 is + + signal internal_QUEUE_INSERT_DATA : std_logic_vector(80 downto 0); + signal internal_QUEUE_RETIRE_DATA : std_logic_vector(80 downto 0); + + alias internal_QUEUE_INSERT_VAL : std_logic is + in_EXECUTE_QUEUE_IN_VAL; + alias internal_QUEUE_INSERT_ACK : std_logic is + out_EXECUTE_QUEUE_IN_ACK; + alias internal_QUEUE_RETIRE_VAL : std_logic is + out_EXECUTE_QUEUE_OUT_VAL; + alias internal_QUEUE_RETIRE_ACK : std_logic is + in_EXECUTE_QUEUE_OUT_ACK; + alias internal_EXECUTE_QUEUE_OUT_CONTEXT_ID : std_logic is + internal_QUEUE_RETIRE_DATA (0); + alias internal_EXECUTE_QUEUE_OUT_FRONT_END_ID : std_logic is + internal_QUEUE_RETIRE_DATA (1); + alias internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID : std_logic is + internal_QUEUE_RETIRE_DATA (2); + alias internal_EXECUTE_QUEUE_OUT_PACKET_ID : std_logic_vector(5 downto 0) is + internal_QUEUE_RETIRE_DATA (8 downto 3); + alias internal_EXECUTE_QUEUE_OUT_FLAGS : std_logic_vector(1 downto 0) is + internal_QUEUE_RETIRE_DATA (10 downto 9); + alias internal_EXECUTE_QUEUE_OUT_EXCEPTION : std_logic_vector(4 downto 0) is + internal_QUEUE_RETIRE_DATA (15 downto 11); + alias internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE : std_logic is + internal_QUEUE_RETIRE_DATA (16); + alias internal_EXECUTE_QUEUE_OUT_ADDRESS : std_logic_vector(31 downto 0) is + internal_QUEUE_RETIRE_DATA (48 downto 17); + alias internal_EXECUTE_QUEUE_OUT_DATA : std_logic_vector(31 downto 0) is + internal_QUEUE_RETIRE_DATA (80 downto 49); + +begin + -- + -- ----------------------------------- + -- -- Instance queue + -- ----------------------------------- + -- + instance_Execute_queue_0_queue : Execute_queue_0_queue + port map ( + in_CLOCK => in_CLOCK + , in_NRESET => in_NRESET + , in_INSERT_VAL => internal_QUEUE_INSERT_VAL + ,out_INSERT_ACK => internal_QUEUE_INSERT_ACK + , in_INSERT_DATA => internal_QUEUE_INSERT_DATA + ,out_RETIRE_VAL => internal_QUEUE_RETIRE_VAL + , in_RETIRE_ACK => internal_QUEUE_RETIRE_ACK + ,out_RETIRE_DATA => internal_QUEUE_RETIRE_DATA + ); + -- + -- ----------------------------------- + -- -- Input Buffer + -- ----------------------------------- + -- + internal_QUEUE_INSERT_DATA (0) <= in_EXECUTE_QUEUE_IN_CONTEXT_ID; + internal_QUEUE_INSERT_DATA (1) <= in_EXECUTE_QUEUE_IN_FRONT_END_ID; + internal_QUEUE_INSERT_DATA (2) <= in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID; + internal_QUEUE_INSERT_DATA (8 downto 3) <= in_EXECUTE_QUEUE_IN_PACKET_ID; + internal_QUEUE_INSERT_DATA (10 downto 9) <= in_EXECUTE_QUEUE_IN_FLAGS; + internal_QUEUE_INSERT_DATA (15 downto 11) <= in_EXECUTE_QUEUE_IN_EXCEPTION; + internal_QUEUE_INSERT_DATA (16) <= in_EXECUTE_QUEUE_IN_NO_SEQUENCE; + internal_QUEUE_INSERT_DATA (48 downto 17) <= in_EXECUTE_QUEUE_IN_ADDRESS; + internal_QUEUE_INSERT_DATA (80 downto 49) <= in_EXECUTE_QUEUE_IN_DATA; + -- + -- ----------------------------------- + -- -- Output Buffer + -- ----------------------------------- + -- + out_EXECUTE_QUEUE_OUT_CONTEXT_ID <= internal_EXECUTE_QUEUE_OUT_CONTEXT_ID; + out_EXECUTE_QUEUE_OUT_FRONT_END_ID <= internal_EXECUTE_QUEUE_OUT_FRONT_END_ID; + out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID <= internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID; + out_EXECUTE_QUEUE_OUT_PACKET_ID <= internal_EXECUTE_QUEUE_OUT_PACKET_ID; + out_EXECUTE_QUEUE_OUT_FLAGS <= internal_EXECUTE_QUEUE_OUT_FLAGS; + out_EXECUTE_QUEUE_OUT_EXCEPTION <= internal_EXECUTE_QUEUE_OUT_EXCEPTION; + out_EXECUTE_QUEUE_OUT_NO_SEQUENCE <= internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE; + out_EXECUTE_QUEUE_OUT_ADDRESS <= internal_EXECUTE_QUEUE_OUT_ADDRESS; + out_EXECUTE_QUEUE_OUT_DATA <= internal_EXECUTE_QUEUE_OUT_DATA; + +end behavioural; +\end{lstlisting} + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-05_example.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-05_example.tex (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-05_example.tex (revision 100) @@ -0,0 +1,8 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Exemples}\label{example} + +\input{\dirroot/document-morpheo-vhdl_generation-fr-05_01_registerfile} +\input{\dirroot/document-morpheo-vhdl_generation-fr-05_02_execute_queue} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-06_testbench.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-06_testbench.tex (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr-06_testbench.tex (revision 100) @@ -0,0 +1,772 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section {Test du VHDL}\label{testbench} + +Lors d'une simulation systemC, \cpu va générer des fichiers de tests pour le modèle VHDL de chaque composant interne. +Ces tests sont tous écrits de la même façon. Soit l'interface X et le signal Y : +\begin{itemize} +\item Une variable {\it counter} indique le numéro de cycle courant. Elle est initialisée à 0. Elle est incrémentée à chaque cycle. +\item Le composant est instancé avec des signaux internes de même nom. +\item Pour chaque cycle, on affecte à chaque entrée la valeur obtenue lors de la simulation systemC. +\item Pour chaque sortie, on définit un signal dont le nom est {\it out\_X\_Y\_test}. Ces signaux sont affectés à la valeur obtenue des sorties lors de la simulation systemC. +\item Le signal {\it interface\_X\_test\_ok} est égal à 1 si chaque sortie calculée par la simulation VHDL est égal à la sortie attendue (calculé par la simulation systemC). +\item Le signal {\it interface\_X\_test\_transaction} est à 1 si tous les signaux de validité et d'acquittement sont à 1. +\item Le signal {\it interface\_X\_test\_tmp} est à 1 si la simulation systemC indique qu'il y a une transaction et que la simulation vhdl indique également une transaction et que toutes les sorties sont bien les sorties obtenues. Si la simulation systemC n'indique pas de transaction, on vérifie que c'est également le cas pour la simulation VHDL. +\item Le signal {\it interface\_X\_test} est égal au signal {\it interface\_X\_test\_tmp} quand il n'y a pas de reset. sinon il est positionné à 1. +\item Le signal {\it test} est un et logique entre tous tous les signaux {\it interface\_X\_test}. +\item La simulation VHDL ce termine si le signal {\it test} vaut 0 (dans ce cas, le test est un échec), ou que le registre {\it counter} vaut le nombre de cycles requis par la simulation systemC (dans ce cas, le test est un succès). +\end{itemize} + +Nous pouvons remarquer que : +\begin{itemize} +\item Nous vérifions la compatibilité au cycle des transactions entre le modèle systemC et le modèle VHDL. +\item Nous vérifions la compatibilité au bit près des données échangées lors qu'il y a une transaction sur une interface. +\item Nous ne vérifions pas la compatibilité au bit près des données présentes sur une interface qui ne fait pas de transaction lors d'un cycle. +\end{itemize} + +\lstparam{VHDL} +\begin{lstlisting}[caption={Execute\_queue\_Testbench.vhdl}] +library ieee; + use ieee.numeric_bit.all; + use ieee.numeric_std.all; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_misc.all; +--use ieee.std_logic_signed.all; + use ieee.std_logic_unsigned.all; +--use ieee.std_logic_textio.all; + +library work; +use work.Execute_queue_0_Pack.all; + +entity Execute_queue_0_Testbench is +end Execute_queue_0_Testbench; + +architecture behavioural of Execute_queue_0_Testbench is + + signal in_CLOCK : std_logic := '0'; + signal in_NRESET : std_logic := '0'; + signal in_EXECUTE_QUEUE_IN_VAL : std_logic; + signal out_EXECUTE_QUEUE_IN_ACK : std_logic; + signal out_EXECUTE_QUEUE_IN_ACK_test : std_logic; + signal in_EXECUTE_QUEUE_IN_PACKET_ID : std_logic_vector(3 downto 0); + signal in_EXECUTE_QUEUE_IN_FLAGS : std_logic_vector(1 downto 0); + signal in_EXECUTE_QUEUE_IN_EXCEPTION : std_logic_vector(4 downto 0); + signal in_EXECUTE_QUEUE_IN_NO_SEQUENCE : std_logic; + signal in_EXECUTE_QUEUE_IN_ADDRESS : std_logic_vector(31 downto 0); + signal in_EXECUTE_QUEUE_IN_DATA : std_logic_vector(31 downto 0); + signal out_EXECUTE_QUEUE_OUT_VAL : std_logic; + signal out_EXECUTE_QUEUE_OUT_VAL_test : std_logic; + signal in_EXECUTE_QUEUE_OUT_ACK : std_logic; + signal out_EXECUTE_QUEUE_OUT_PACKET_ID : std_logic_vector(3 downto 0); + signal out_EXECUTE_QUEUE_OUT_PACKET_ID_test : std_logic_vector(3 downto 0); + signal out_EXECUTE_QUEUE_OUT_FLAGS : std_logic_vector(1 downto 0); + signal out_EXECUTE_QUEUE_OUT_FLAGS_test : std_logic_vector(1 downto 0); + signal out_EXECUTE_QUEUE_OUT_EXCEPTION : std_logic_vector(4 downto 0); + signal out_EXECUTE_QUEUE_OUT_EXCEPTION_test : std_logic_vector(4 downto 0); + signal out_EXECUTE_QUEUE_OUT_NO_SEQUENCE : std_logic; + signal out_EXECUTE_QUEUE_OUT_NO_SEQUENCE_test : std_logic; + signal out_EXECUTE_QUEUE_OUT_ADDRESS : std_logic_vector(31 downto 0); + signal out_EXECUTE_QUEUE_OUT_ADDRESS_test : std_logic_vector(31 downto 0); + signal out_EXECUTE_QUEUE_OUT_DATA : std_logic_vector(31 downto 0); + signal out_EXECUTE_QUEUE_OUT_DATA_test : std_logic_vector(31 downto 0); + + signal counter : natural; + signal test : std_logic; + signal interface_test : std_logic; + signal interface_test_ok : std_logic; + signal interface_execute_queue_in_test : std_logic; + signal interface_execute_queue_in_test_ok : std_logic; + signal interface_execute_queue_in_test_transaction : std_logic; + signal interface_execute_queue_in_test_tmp : std_logic; + signal interface_execute_queue_out_test : std_logic; + signal interface_execute_queue_out_test_ok : std_logic; + signal interface_execute_queue_out_test_transaction : std_logic; + signal interface_execute_queue_out_test_tmp : std_logic; + +begin + + ------------------------------------------------------ + -- Component - Intanciation + ------------------------------------------------------ + + instance_Execute_queue_0 : Execute_queue_0 + port map ( + in_CLOCK => in_CLOCK + , in_NRESET => in_NRESET + , in_EXECUTE_QUEUE_IN_VAL => in_EXECUTE_QUEUE_IN_VAL + ,out_EXECUTE_QUEUE_IN_ACK => out_EXECUTE_QUEUE_IN_ACK + , in_EXECUTE_QUEUE_IN_PACKET_ID => in_EXECUTE_QUEUE_IN_PACKET_ID + , in_EXECUTE_QUEUE_IN_FLAGS => in_EXECUTE_QUEUE_IN_FLAGS + , in_EXECUTE_QUEUE_IN_EXCEPTION => in_EXECUTE_QUEUE_IN_EXCEPTION + , in_EXECUTE_QUEUE_IN_NO_SEQUENCE => in_EXECUTE_QUEUE_IN_NO_SEQUENCE + , in_EXECUTE_QUEUE_IN_ADDRESS => in_EXECUTE_QUEUE_IN_ADDRESS + , in_EXECUTE_QUEUE_IN_DATA => in_EXECUTE_QUEUE_IN_DATA + ,out_EXECUTE_QUEUE_OUT_VAL => out_EXECUTE_QUEUE_OUT_VAL + , in_EXECUTE_QUEUE_OUT_ACK => in_EXECUTE_QUEUE_OUT_ACK + ,out_EXECUTE_QUEUE_OUT_PACKET_ID => out_EXECUTE_QUEUE_OUT_PACKET_ID + ,out_EXECUTE_QUEUE_OUT_FLAGS => out_EXECUTE_QUEUE_OUT_FLAGS + ,out_EXECUTE_QUEUE_OUT_EXCEPTION => out_EXECUTE_QUEUE_OUT_EXCEPTION + ,out_EXECUTE_QUEUE_OUT_NO_SEQUENCE => out_EXECUTE_QUEUE_OUT_NO_SEQUENCE + ,out_EXECUTE_QUEUE_OUT_ADDRESS => out_EXECUTE_QUEUE_OUT_ADDRESS + ,out_EXECUTE_QUEUE_OUT_DATA => out_EXECUTE_QUEUE_OUT_DATA + ); + ------------------------------------------------------ + -- interface "" + ------------------------------------------------------ + + -- Test exhaustive + + interface_test_ok <= '1' when true + else '0'; + + interface_test <= '1' when (in_NRESET = '0') else interface_test_ok; + ------------------------------------------------------ + -- interface "execute_queue_in" + ------------------------------------------------------ + + with counter select + in_EXECUTE_QUEUE_IN_VAL <= + '0' when 0, + '0' when 1, + '0' when 2, + '0' when 3, + '0' when 4, + '1' when 5, + '1' when 6, + '0' when 7, + '0' when 8, + '1' when 9, + '1' when 10, + '1' when 11, + '1' when 12, + '1' when 13, + '1' when 14, + '1' when 15, + '1' when 16, + '0' when 17, + '1' when 18, + '1' when 19, + '1' when 20, + '0' when 21, + '1' when 22, + '1' when 23, + '0' when 24, + '1' when 25, + '0' when 26, + '0' when others; + + with counter select + out_EXECUTE_QUEUE_IN_ACK_test <= + '0' when 0, + '1' when 1, + '1' when 2, + '1' when 3, + '1' when 4, + '1' when 5, + '1' when 6, + '1' when 7, + '1' when 8, + '1' when 9, + '1' when 10, + '1' when 11, + '1' when 12, + '1' when 13, + '1' when 14, + '1' when 15, + '1' when 16, + '1' when 17, + '1' when 18, + '1' when 19, + '1' when 20, + '1' when 21, + '1' when 22, + '1' when 23, + '1' when 24, + '1' when 25, + '1' when 26, + '0' when others; + + with counter select + in_EXECUTE_QUEUE_IN_PACKET_ID <= + "0000" when 0, + "0000" when 1, + "0000" when 2, + "0000" when 3, + "0000" when 4, + "0000" when 5, + "0001" when 6, + "0001" when 7, + "0001" when 8, + "0010" when 9, + "0011" when 10, + "0100" when 11, + "0101" when 12, + "0110" when 13, + "0111" when 14, + "1000" when 15, + "1001" when 16, + "1001" when 17, + "1010" when 18, + "1011" when 19, + "1100" when 20, + "1100" when 21, + "1101" when 22, + "1110" when 23, + "1110" when 24, + "1111" when 25, + "1111" when 26, + (others => '0') when others; + + with counter select + in_EXECUTE_QUEUE_IN_FLAGS <= + "00" when 0, + "00" when 1, + "00" when 2, + "00" when 3, + "00" when 4, + "11" when 5, + "11" when 6, + "11" when 7, + "11" when 8, + "00" when 9, + "11" when 10, + "11" when 11, + "11" when 12, + "10" when 13, + "01" when 14, + "01" when 15, + "11" when 16, + "11" when 17, + "10" when 18, + "00" when 19, + "11" when 20, + "11" when 21, + "10" when 22, + "01" when 23, + "01" when 24, + "01" when 25, + "01" when 26, + (others => '0') when others; + + with counter select + in_EXECUTE_QUEUE_IN_EXCEPTION <= + "00000" when 0, + "00000" when 1, + "00000" when 2, + "00000" when 3, + "00000" when 4, + "10001" when 5, + "10010" when 6, + "10010" when 7, + "10010" when 8, + "11011" when 9, + "10011" when 10, + "10001" when 11, + "11000" when 12, + "11011" when 13, + "00001" when 14, + "00001" when 15, + "01010" when 16, + "01010" when 17, + "01100" when 18, + "01100" when 19, + "11011" when 20, + "11011" when 21, + "00101" when 22, + "01001" when 23, + "01001" when 24, + "10001" when 25, + "10001" when 26, + (others => '0') when others; + + with counter select + in_EXECUTE_QUEUE_IN_NO_SEQUENCE <= + '0' when 0, + '0' when 1, + '0' when 2, + '0' when 3, + '0' when 4, + '1' when 5, + '1' when 6, + '1' when 7, + '1' when 8, + '1' when 9, + '1' when 10, + '1' when 11, + '1' when 12, + '1' when 13, + '1' when 14, + '1' when 15, + '1' when 16, + '1' when 17, + '1' when 18, + '1' when 19, + '1' when 20, + '1' when 21, + '1' when 22, + '1' when 23, + '1' when 24, + '1' when 25, + '1' when 26, + '0' when others; + + with counter select + in_EXECUTE_QUEUE_IN_ADDRESS <= + "00000000000000000000000000000000" when 0, + "00000000000000000000000000000000" when 1, + "00000000000000000000000000000000" when 2, + "00000000000000000000000000000000" when 3, + "00000000000000000000000000000000" when 4, + "00101010111010001001010001001010" when 5, + "01111001111000101010100111100011" when 6, + "01111001111000101010100111100011" when 7, + "01111001111000101010100111100011" when 8, + "00010001100100001100110111100111" when 9, + "01000001101001111100010011001001" when 10, + "00100101011100010011000010100011" when 11, + "01100111011000111000010001011110" when 12, + "01110001111100110010010001010100" when 13, + "01110011011110111000110111011100" when 14, + "01000100000010111010110111111100" when 15, + "01010001111010101101001101101011" when 16, + "01010001111010101101001101101011" when 17, + "00011101010011101101010000111011" when 18, + "00111000010000110111111111011011" when 19, + "01111001101000011101111010101010" when 20, + "01111001101000011101111010101010" when 21, + "01100100100110111011011101111100" when 22, + "00010101101101011010111101011100" when 23, + "00010101101101011010111101011100" when 24, + "01010111100110111110010011110001" when 25, + "01010111100110111110010011110001" when 26, + (others => '0') when others; + + with counter select + in_EXECUTE_QUEUE_IN_DATA <= + "00000000000000000000000000000000" when 0, + "00000000000000000000000000000000" when 1, + "00000000000000000000000000000000" when 2, + "00000000000000000000000000000000" when 3, + "00000000000000000000000000000000" when 4, + "01100010010101010101100011101100" when 5, + "01110101010001011110000101000110" when 6, + "01110101010001011110000101000110" when 7, + "01110101010001011110000101000110" when 8, + "01100110111011110100001110001101" when 9, + "01101011011010000000011110011010" when 10, + "01100010101110111101100101011010" when 11, + "01110101101000101010100011010100" when 12, + "00101100101010001000011000010001" when 13, + "01101100111010101111000010000111" when 14, + "00000101000001110010001101100111" when 15, + "00101101010100010111011110010110" when 16, + "00101101010100010111011110010110" when 17, + "01110010010110100000011011111011" when 18, + "01110110010001001010010001011100" when 19, + "01110101110001101100001100111010" when 20, + "01110101110001101100001100111010" when 21, + "00100111010110101100011110010100" when 22, + "01110100000100100010011010111011" when 23, + "01110100000100100010011010111011" when 24, + "00110001000011000101000010110011" when 25, + "00110001000011000101000010110011" when 26, + (others => '0') when others; + + -- Test partial + + interface_execute_queue_in_test_ok <= '1' when true + and out_EXECUTE_QUEUE_IN_ACK = out_EXECUTE_QUEUE_IN_ACK_test + else '0'; + + interface_execute_queue_in_test_transaction <= '1' + and in_EXECUTE_QUEUE_IN_VAL + and out_EXECUTE_QUEUE_IN_ACK + ; + + with counter select + interface_execute_queue_in_test_tmp <= + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 5, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 6, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 9, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 10, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 11, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 12, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 13, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 14, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 15, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 16, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 18, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 19, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 20, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 22, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 23, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 25, + not interface_execute_queue_in_test_transaction when others; + + interface_execute_queue_in_test <= '1' when (in_NRESET = '0') else + interface_execute_queue_in_test_tmp; + ------------------------------------------------------ + -- interface "execute_queue_out" + ------------------------------------------------------ + + with counter select + out_EXECUTE_QUEUE_OUT_VAL_test <= + '0' when 0, + '0' when 1, + '0' when 2, + '0' when 3, + '0' when 4, + '0' when 5, + '1' when 6, + '1' when 7, + '0' when 8, + '0' when 9, + '1' when 10, + '1' when 11, + '1' when 12, + '1' when 13, + '1' when 14, + '1' when 15, + '1' when 16, + '1' when 17, + '0' when 18, + '1' when 19, + '1' when 20, + '1' when 21, + '1' when 22, + '1' when 23, + '1' when 24, + '0' when 25, + '1' when 26, + '0' when others; + + with counter select + in_EXECUTE_QUEUE_OUT_ACK <= + '0' when 0, + '0' when 1, + '0' when 2, + '0' when 3, + '0' when 4, + '1' when 5, + '1' when 6, + '1' when 7, + '1' when 8, + '0' when 9, + '1' when 10, + '1' when 11, + '1' when 12, + '1' when 13, + '1' when 14, + '1' when 15, + '1' when 16, + '1' when 17, + '1' when 18, + '1' when 19, + '1' when 20, + '0' when 21, + '1' when 22, + '1' when 23, + '1' when 24, + '1' when 25, + '1' when 26, + '0' when others; + + with counter select + out_EXECUTE_QUEUE_OUT_PACKET_ID_test <= + "0000" when 0, + "0000" when 1, + "0000" when 2, + "0000" when 3, + "0000" when 4, + "0000" when 5, + "0000" when 6, + "0001" when 7, + "0001" when 8, + "0001" when 9, + "0010" when 10, + "0011" when 11, + "0100" when 12, + "0101" when 13, + "0110" when 14, + "0111" when 15, + "1000" when 16, + "1001" when 17, + "1001" when 18, + "1010" when 19, + "1011" when 20, + "1100" when 21, + "1100" when 22, + "1101" when 23, + "1110" when 24, + "1110" when 25, + "1111" when 26, + (others => '0') when others; + + with counter select + out_EXECUTE_QUEUE_OUT_FLAGS_test <= + "00" when 0, + "00" when 1, + "00" when 2, + "00" when 3, + "00" when 4, + "00" when 5, + "11" when 6, + "11" when 7, + "11" when 8, + "11" when 9, + "00" when 10, + "11" when 11, + "11" when 12, + "11" when 13, + "10" when 14, + "01" when 15, + "01" when 16, + "11" when 17, + "11" when 18, + "10" when 19, + "00" when 20, + "11" when 21, + "11" when 22, + "10" when 23, + "01" when 24, + "01" when 25, + "01" when 26, + (others => '0') when others; + + with counter select + out_EXECUTE_QUEUE_OUT_EXCEPTION_test <= + "00000" when 0, + "00000" when 1, + "00000" when 2, + "00000" when 3, + "00000" when 4, + "00000" when 5, + "10001" when 6, + "10010" when 7, + "10010" when 8, + "10010" when 9, + "11011" when 10, + "10011" when 11, + "10001" when 12, + "11000" when 13, + "11011" when 14, + "00001" when 15, + "00001" when 16, + "01010" when 17, + "01010" when 18, + "01100" when 19, + "01100" when 20, + "11011" when 21, + "11011" when 22, + "00101" when 23, + "01001" when 24, + "01001" when 25, + "10001" when 26, + (others => '0') when others; + + with counter select + out_EXECUTE_QUEUE_OUT_NO_SEQUENCE_test <= + '0' when 0, + '0' when 1, + '0' when 2, + '0' when 3, + '0' when 4, + '0' when 5, + '1' when 6, + '1' when 7, + '1' when 8, + '1' when 9, + '1' when 10, + '1' when 11, + '1' when 12, + '1' when 13, + '1' when 14, + '1' when 15, + '1' when 16, + '1' when 17, + '1' when 18, + '1' when 19, + '1' when 20, + '1' when 21, + '1' when 22, + '1' when 23, + '1' when 24, + '1' when 25, + '1' when 26, + '0' when others; + + with counter select + out_EXECUTE_QUEUE_OUT_ADDRESS_test <= + "00000000000000000000000000000000" when 0, + "00000000000000000000000000000000" when 1, + "00000000000000000000000000000000" when 2, + "00000000000000000000000000000000" when 3, + "00000000000000000000000000000000" when 4, + "00000000000000000000000000000000" when 5, + "00101010111010001001010001001010" when 6, + "01111001111000101010100111100011" when 7, + "01111001111000101010100111100011" when 8, + "01111001111000101010100111100011" when 9, + "00010001100100001100110111100111" when 10, + "01000001101001111100010011001001" when 11, + "00100101011100010011000010100011" when 12, + "01100111011000111000010001011110" when 13, + "01110001111100110010010001010100" when 14, + "01110011011110111000110111011100" when 15, + "01000100000010111010110111111100" when 16, + "01010001111010101101001101101011" when 17, + "01010001111010101101001101101011" when 18, + "00011101010011101101010000111011" when 19, + "00111000010000110111111111011011" when 20, + "01111001101000011101111010101010" when 21, + "01111001101000011101111010101010" when 22, + "01100100100110111011011101111100" when 23, + "00010101101101011010111101011100" when 24, + "00010101101101011010111101011100" when 25, + "01010111100110111110010011110001" when 26, + (others => '0') when others; + + with counter select + out_EXECUTE_QUEUE_OUT_DATA_test <= + "00000000000000000000000000000000" when 0, + "00000000000000000000000000000000" when 1, + "00000000000000000000000000000000" when 2, + "00000000000000000000000000000000" when 3, + "00000000000000000000000000000000" when 4, + "00000000000000000000000000000000" when 5, + "01100010010101010101100011101100" when 6, + "01110101010001011110000101000110" when 7, + "01110101010001011110000101000110" when 8, + "01110101010001011110000101000110" when 9, + "01100110111011110100001110001101" when 10, + "01101011011010000000011110011010" when 11, + "01100010101110111101100101011010" when 12, + "01110101101000101010100011010100" when 13, + "00101100101010001000011000010001" when 14, + "01101100111010101111000010000111" when 15, + "00000101000001110010001101100111" when 16, + "00101101010100010111011110010110" when 17, + "00101101010100010111011110010110" when 18, + "01110010010110100000011011111011" when 19, + "01110110010001001010010001011100" when 20, + "01110101110001101100001100111010" when 21, + "01110101110001101100001100111010" when 22, + "00100111010110101100011110010100" when 23, + "01110100000100100010011010111011" when 24, + "01110100000100100010011010111011" when 25, + "00110001000011000101000010110011" when 26, + (others => '0') when others; + + -- Test partial + + interface_execute_queue_out_test_ok <= '1' when true + and out_EXECUTE_QUEUE_OUT_VAL = out_EXECUTE_QUEUE_OUT_VAL_test + and out_EXECUTE_QUEUE_OUT_PACKET_ID = out_EXECUTE_QUEUE_OUT_PACKET_ID_test + and out_EXECUTE_QUEUE_OUT_FLAGS = out_EXECUTE_QUEUE_OUT_FLAGS_test + and out_EXECUTE_QUEUE_OUT_EXCEPTION = out_EXECUTE_QUEUE_OUT_EXCEPTION_test + and out_EXECUTE_QUEUE_OUT_NO_SEQUENCE = out_EXECUTE_QUEUE_OUT_NO_SEQUENCE_test + and out_EXECUTE_QUEUE_OUT_ADDRESS = out_EXECUTE_QUEUE_OUT_ADDRESS_test + and out_EXECUTE_QUEUE_OUT_DATA = out_EXECUTE_QUEUE_OUT_DATA_test + else '0'; + + interface_execute_queue_out_test_transaction <= '1' + and out_EXECUTE_QUEUE_OUT_VAL + and in_EXECUTE_QUEUE_OUT_ACK + ; + + with counter select + interface_execute_queue_out_test_tmp <= + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 6, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 7, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 10, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 11, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 12, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 13, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 14, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 15, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 16, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 17, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 19, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 20, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 22, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 23, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 24, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 26, + not interface_execute_queue_out_test_transaction when others; + + interface_execute_queue_out_test <= '1' when (in_NRESET = '0') else + interface_execute_queue_out_test_tmp; + + ------------------------------------------------------ + -- Test + ------------------------------------------------------ + + test <= '1' + and interface_test + and interface_execute_queue_in_test + and interface_execute_queue_out_test; + + ------------------------------------------------------ + -- reset + ------------------------------------------------------ + + -- if the systemC simulate have multiple reset, we make the last + in_NRESET <= '1' after 150 ns; + + ------------------------------------------------------ + -- process clock_name + ------------------------------------------------------ + + in_CLOCK <= not in_CLOCK after 50 ns; + + process (in_CLOCK) + begin + if (in_CLOCK'event and in_CLOCK = '1') then + + if (in_NRESET = '0') then + counter <= 4; + else + counter <= counter+1; + + assert not (counter >= 27) report "Test OK" severity FAILURE; + assert not (test = '0') report "Test KO" severity FAILURE; + end if; + end if; + end process; +end behavioural; +\end{lstlisting} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr.tex (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr.tex (revision 100) @@ -5,5 +5,5 @@ \SEction{Introduction} -Ce document est une aide pour les développeur des générateurs de modèles VHDL de \cpu. +Ce document est une aide pour les développeurs des générateurs de modèles VHDL de \cpu. Il est décomposé en 6 sections : \begin{itemize} @@ -16,1714 +16,8 @@ \end{itemize} -\Section{Arborescence}\label{tree} - -Dans le répertoire contenant le projet, nous avons les répertoires suivant : -\begin{description} -\item[IPs/systemC/processor/Morpheo/Documentation/ :] Contient différent document décrivant certain point du projet, dont cette documentation. -\item[IPs/systemC/processor/Morpheo/Behavioural/ :] -\item[IPs/systemC/processor/Morpheo/Behavioural/include/ :] - \begin{description} - \item [Parameters.h :] Contient la classe {\it Parameters}, cette classe définit les paramètres constants. - \item [Vhdl.h :] Contient la classe {\it Vhdl}. - \end{description} -\item[IPs/systemC/processor/Morpheo/Behavioural/\dots/Component :] Chaque composant est inclue dans un répertoire spécifique. -\item[IPs/systemC/processor/Morpheo/Behavioural/\dots/Component/include :] - \begin{description} - \item [Parameters.h :] Contient la classe {\it Parameters}, elle dérive de la classe contenu dans le fichier le répertoire {\it \dots/Behavioural/include/}. - \item [Component.h :] Contient la classe {\it Component}. Il définit l'interface, les registres ainsi que les méthodes du modèle systemC. - \item [Types.h :] Contient les types spéciaux. - \end{description} -\item[IPs/systemC/processor/Morpheo/Behavioural/\dots/Component/src :] - \begin{description} - \item [Component\_transition.cpp :] - \item [Component\_genMoore.cpp :] - \item [Component\_genMealy\_XXX.cpp :] - - \item [Component\_vhdl\_declaration.cpp :] - \item [Component\_vhdl\_body.cpp :] - \end{description} -\item[IPs/systemC/processor/Morpheo/Behavioural/\dots/Component/Selftest :] -\end{description} - -\Section{VHDL : déclaration}\label{vhdl_declaration} - -Les déclarations ce font dans le fichier {\it Component\_vhdl\_declaration.cpp}. - -\subSection{Interfaces} -L'interface est définit dans le modèle SystemC. Il n'ont pas nécessaire de la redéfinir pour le modèle VHDL. - -La nomenclature est la suivante : -\begin{itemize} -\item La direction en minuscule ({\it in}, {\it out}). -\item Le nom de l'interface en majuscule ({\it READ}, {\it PUSH}, \dots). -\item Le numéro de l'interface (la première interface aura le numéro 0. S'il n'y a qu'une interface, celle ci aura tout de même le numéro 0). -\item Le nom du signal en majuscule ({\it VAL}, {\it ADDRESS}, \dots). -\end{itemize} - -Par exemple pour la 2 ème interface de lecture d'un banc de registre : -\lstparam{VHDL} -\begin{lstlisting} - in_READ_1_VAL : in std_logic; -out_READ_1_ACK : out std_logic; - in_READ_1_ADDRESS : in std_logic_vector(8 downto 0); -out_READ_1_DATA : out std_logic_vector(31 downto 0); -\end{lstlisting} - -Chaque composent (aussi bien combinatoire que séquentielle) possède un signal d'horloge et un signal de reset. (Ce dernier est actif à l'état bas). Ils ont tout les deux le même nom quelque soit le composant. -\lstparam{VHDL} -\begin{lstlisting} - in_CLOCK : in std_logic; - in_NRESET : in std_logic; -\end{lstlisting} - -\subSection{Types} - -Le type de base utilisé est le {\it std\_logic\_vector} (ou std\_logic si le vecteur est sur un seul bit). Pour cela on utilise la fonction suivante : - -\lstparam{C++} -\begin{lstlisting} -std::string std_logic (uint32_t size); -\end{lstlisting} - -Pour accéder à une partie du vecteur on utilise la fonction {\it std\_logic\_range}. Elle a les prototypes suivant : -\lstparam{C++} -\begin{lstlisting} -std::string std_logic_range (uint32_t size, - uint32_t max , - uint32_t min); -std::string std_logic_range (uint32_t max , - uint32_t min); -std::string std_logic_range (uint32_t size); -std::string _std_logic_range (uint32_t size, - uint32_t max , - uint32_t min); -std::string _std_logic_range (uint32_t max , - uint32_t min); -std::string _std_logic_range (uint32_t size); -\end{lstlisting} - -La première fonction fais un test sur la taille que la seconde ne fait pas. -L'argument de la troisième définit la taille (ce qui implique que la borne minimum est 0 et la borne maximum est size-1). -Toute les fonctions avec préfixé par un underscore n'effectue pas de test sur les bornes. - -Par exemple : -\begin{verbatim} - std_logic_range(4) renvoie "(3 downto 0)". - std_logic_range(1) renvoie "(0)". -_std_logic_range(1) renvoie "(0 downto 0)". -\end{verbatim} - -Pour les types plus complexe, la classe {\it Vhdl} possède une méthode générique. Le premier argument est le nom du type le second est le type. - -\lstparam{C++} -\begin{lstlisting} -void set_type (std::string name, - std::string type); -\end{lstlisting} - -L'exemple suivant définit un type représentat un tableau de {\it nb\_word} mots de {\it size\_word} bit chacun : -\lstparam{C++} -\begin{lstlisting} -vhdl->set_type ("Tregfile", - "array "+std_logic_range(nb_word)+" of "+std_logic(size_word)); -\end{lstlisting} - -\subSection{Constantes} - -La déclaration de constante, ce fait avec la méthode {\it set\_constant} de la classe {\it Vhdl}. Les différentes surcharges de cette méthode est le type des arguments {\it type} et {\it init}. - -\lstparam{C++} -\begin{lstlisting} -void set_constant (std::string name, - std::string type, - std::string init); -void set_constant (std::string name, - uint32_t size, - std::string init); -void set_constant (std::string name, - uint32_t size, - uint32_t init); -\end{lstlisting} - -Par exemple pour coder les états d'un automate à 5 états en One Hot : -\lstparam{C++} -\begin{lstlisting} -vhdl->set_constant ("State_idle",5,1); -\end{lstlisting} - -Dans le cas de signaux de type {\it std\_logic}, au lieu de déclarer des constantes, il existe deux fonctions permettant d'utiliser des constantes directement dans le corps du composant. -La première est {\it std\_logic\_others}. Elle permet de définir des constantes dont soit les bits sont à pleins un soit à plein zéro. - -\lstparam{C++} -\begin{lstlisting} -std::string std_logic_others (uint32_t size, - bool cst ); -\end{lstlisting} - -Pour toute les autres constantes, la méthode {\it std\_logic\_conv} transforme un entier en {\it std\_logic\_vector}. - -\lstparam{C++} -\begin{lstlisting} -std::string std_logic_conv (uint32_t size, - std::string value); -std::string std_logic_conv (uint32_t size, - uint32_t value); -\end{lstlisting} - - -\subSection{Signaux internes} - -Les signaux internes sont définit grâce au méthode {\it set\_signal}. Le premier argument est le nom du signal. Le second est soit un type soit une taille (dans le cas où le type est un {\it std\_logic\_vector}). -\lstparam{C++} -\begin{lstlisting} -void set_signal (std::string name, - std::string type); -void set_signal (std::string name, - uint32_t size); -\end{lstlisting} - -La méthode est également surchargé si le signal à besoin d'une initialisation. - -\lstparam{C++} -\begin{lstlisting} -void set_signal (std::string name, - std::string type, - std::string init); -void set_signal (std::string name, - uint32_t size, - std::string init); -void set_signal (std::string name, - uint32_t size, - uint32_t init); -\end{lstlisting} - -En vhdl il est possible de renommer une champ d'un signal. Ceci ce fait à l'aide de la fonction {\it set\_alias}. Elle prend 4 arguments. Le premier étant le nom du signal après le renommage. le second est soit le type, soit la taille du {\it std\_logic\_vector} du signal rénommé. Les deux derniers conserné le signal à renommé : le nom de ce dernier ainsi que l'intervalle. Pour le dernier paramètre il est recommandé d'utilisé la fonction {\it std\_logic\_range}. - -\lstparam{C++} -\begin{lstlisting} -void set_alias (std::string name1 , - std::string type1 , - std::string name2 , - std::string range2); -void set_alias (std::string name1 , - uint32_t size1 , - std::string name2 , - std::string range2); -\end{lstlisting} - -\Section{VHDL : comportement}\label{vhdl_body} - -Le comportement du composant est définit dans le fichier {\it Component\_vhdl\_body.cpp}. - -Il n'y a pas de fonction aidant à l'écriture du Vhdl. -La méthode {\it set\_body} permet de définir une ligne de code VHDL. Un retour à la ligne est automatiquement inséré. Le premier argument est pour l'indentation. -\lstparam{C++} -\begin{lstlisting} -void set_body (uint32_t depth, - std::string text ); -void set_body (std::string text ); -\end{lstlisting} - -Pour les commentaires, il y a la fonction {\it set\_comment}. -\lstparam{C++} -\begin{lstlisting} -void set_comment (uint32_t depth, - std::string text ); -void set_comment (std::string text ); -\end{lstlisting} - -\Section{VHDL : structurelle}\label{vhdl_structural} - -\subSection{Description du fichier {\it Component\_vhdl.cpp}} -Les modèles systemC structurelle sont des modèles qui instancie d'autre modèle. Il n'y a pas de description comportementale. Ces modèles sont générés automatiquement. -Par contre les modèles systemC comportementales peuvent être décrit par un modèle VHDL mixte (incluant une description comportementale et des instances d'autre composant). - -Les modèles génériques sont dans le répertoire {\it IPs/systemC/processor/Morpheo/Behavioural/Generic}. - -\lstparam{C++} -\begin{lstlisting}[caption={Component\_vhdl.cpp}, label=component_vhdl.cpp] - void component::vhdl (void) - { - Vhdl * vhdl = new Vhdl (_name); - - _interfaces->set_port(vhdl); - _component->vhdl_instance(vhdl); - - vhdl_declaration (vhdl); - vhdl_body (vhdl); - - vhdl->generate_file(); - - delete vhdl; - }; -\end{lstlisting} - - -La première étape est d'éditer le fichier {\it Component\_vhdl.cpp}. Le listing \ref{component_vhdl.cpp} représente le contenu de ce fichier. -\begin{itemize} -\item Ligne 3 : Déclaration et construction de la variable {\it vhdl} qui est du type {\it Vhdl}. -\item Ligne 5 : Ajout dans le modèle VHDL des interfaces présentes dans le modèle SystemC. (cf fichiers Component.h). -\item Ligne 6 : Ajout dans le modèle VHDL des composants internes dans le modèle SystemC. (cf fichiers Component.h et Component\_allocation.cpp). -\item Ligne 8 : Ajout dans le modèle VHDL des déclarations définit dans le fichiers Component\_vhdl\_declaration.cpp (cf section \ref{vhdl_declaration}). -\item Ligne 9 : Ajout dans le modèle VHDL de la description comportemental définit dans le fichiers Component\_vhdl\_body.cpp (cf section \ref{vhdl_body}). -\item Ligne 11 : Génération des fichiers VHDL. Le nom du fichier est construit à partir du nom fournit lors de la construction de la variable {\it vhdl}. -\item Ligne 13 : Destruction de l'objet. -\end{itemize} - -Pour la suite, nous allons supposer l'instanciation d'une FIFO. - -\subSection{Ajout d'une instance} - -Dans le fichier Component\_vhdl.cpp : -\begin{enumerate} -\item Inclure la définition de la classe désirée. -\lstparam{C++} -\begin{lstlisting} -#include "Behavioural/Generic/Queue/include/Queue.h" -\end{lstlisting} -\item Creer les paramètres du modèles. -\lstparam{C++} -\begin{lstlisting} - morpheo::behavioural::generic::queue::Parameters * param_queue; - param_queue = new morpheo::behavioural::generic::queue::Parameters - (16, //size_queue - 32);//size_data -\end{lstlisting} -\item Creer le modèle -\lstparam{C++} -\begin{lstlisting} - morpheo::behavioural::generic::queue::Queue * queue; - std::string queue_name = _name + "_queue"; - - queue = new morpheo::behavioural::generic::queue::Queue - (queue_name.c_str() // nom du modèle -#ifdef STATISTICS - ,NULL // Pas paramètres pour les statistiques -#endif - ,param_queue // Paramètres de la file - ,USE_VHDL); // Utilisation du modèle VHDL -\end{lstlisting} -\item Inclure le modèle dans la liste des composants internes -\lstparam{C++} -\begin{lstlisting} - _component->set_component(queue->_component -#ifdef POSITION - , 20, 20, 20, 20 - // Coordonée pour l'outil de visualisation -#endif - , INSTANCE_LIBRARY - // Instancier uniquement les libraries - ); -\end{lstlisting} -\item Indiquer dans le fichier Makefile.deps que le composant dépends de ce modèle. -\lstparam{make} -\begin{lstlisting} -# Inclure les dépendances -ifndef Queue -include $(DIR_MORPHEO)/Behavioural/Generic/Queue/Makefile.deps -endif - -# Inclure les librairies -Component_LIBRARY = -lComponent \ - $(Queue_LIBRARY) - -# Les chemins vers les libraries -Component_DIR_LIBRARY = -L$(Component_DIR)/lib \ - $(Queue_DIR_LIBRARY) - -# Construction de la librarie ``Component'' -Component_library : - @\ - $(MAKE) Queue_library; \ - $(MAKE) --directory=$(Component_DIR) --makefile=Makefile; - -# Effacement des fichiers générés -Component_library_clean : - @\ - $(MAKE) Queue_library_clean; \ - $(MAKE) --directory=$(Component_DIR) --makefile=Makefile clean; -\end{lstlisting} -\end{enumerate} - -\subSection{Instanciation} -L'instanciation ce fait comme avec des composants VHDL classique : -\lstparam{C++} -\begin{lstlisting} - vhdl->set_comment(0,""); - vhdl->set_comment(0,"-----------------------------------"); - vhdl->set_comment(0,"-- Instance queue "); - vhdl->set_comment(0,"-----------------------------------"); - vhdl->set_comment(0,""); - - vhdl->set_body (0,"instance_"+_name+"_queue : "+_name+"_queue"); - vhdl->set_body (0,"port map ("); - vhdl->set_body (1," in_CLOCK \t=>\t in_CLOCK "); - vhdl->set_body (1,", in_NRESET \t=>\t in_NRESET"); - vhdl->set_body (1,", in_INSERT_VAL \t=>\tinternal_QUEUE_INSERT_VAL"); - vhdl->set_body (1,",out_INSERT_ACK \t=>\tinternal_QUEUE_INSERT_ACK"); - vhdl->set_body (1,", in_INSERT_DATA \t=>\tinternal_QUEUE_INSERT_DATA"); - vhdl->set_body (1,",out_RETIRE_VAL \t=>\tinternal_QUEUE_RETIRE_VAL"); - vhdl->set_body (1,", in_RETIRE_ACK \t=>\tinternal_QUEUE_RETIRE_ACK"); - vhdl->set_body (1,",out_RETIRE_DATA \t=>\tinternal_QUEUE_RETIRE_DATA"); - vhdl->set_body (0,");"); -\end{lstlisting} - -\Section{Exemples}\label{example} - -\subSection{Banc de Registres Monolithique} - -\subsubSection{Fichier RegisterFile\_Monolithic\_vhdl.cpp} - -\lstparam{C++} -\begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl.cpp}] -void RegisterFile_Monolithic::vhdl (void) -{ - Vhdl * vhdl = new Vhdl (_name); - - _interfaces->set_port (vhdl); - _component ->vhdl_instance(vhdl); - - vhdl_declaration (vhdl); - vhdl_body (vhdl); - - vhdl->generate_file(); - - delete vhdl; -}; -\end{lstlisting} - - -\subsubSection{Fichier RegisterFile\_Monolithic\_vhdl\_declaration.cpp} - -\lstparam{C++} -\begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl\_declaration.cpp}] -void RegisterFile_Monolithic::vhdl_declaration (Vhdl * & vhdl) -{ - vhdl->set_type ("Tregfile", "array " + std_logic_range(_param->_nb_word,true)+ - " of "+ - std_logic(_param->_size_word)); - - vhdl->set_signal ("reg_DATA", "Tregfile"); -}; -\end{lstlisting} - -\subsubSection{Fichier RegisterFile\_Monolithic\_vhdl\_body.cpp} - -\lstparam{C++} -\begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl\_body.cpp}] -void RegisterFile_Monolithic::vhdl_body (Vhdl * & vhdl) -{ - vhdl->set_body (0,""); - vhdl->set_comment(0,"---------------------------------------------------"); - vhdl->set_comment(0," Ack"); - vhdl->set_comment(0,"---------------------------------------------------"); - vhdl->set_body (0,""); - - for (uint32_t i = 0; i < _param->_nb_port_read; i++) - vhdl->set_body (0,"out_READ_"+toString(i)+"_ACK <= '1';"); - for (uint32_t i = 0; i < _param->_nb_port_write; i++) - vhdl->set_body (0,"out_WRITE_"+toString(i)+"_ACK <= '1';"); - - vhdl->set_body (0,""); - vhdl->set_comment(0,"---------------------------------------------------"); - vhdl->set_comment(0," Read RegisterFile"); - vhdl->set_comment(0,"---------------------------------------------------"); - vhdl->set_body (0,""); - - for (uint32_t i = 0; i < _param->_nb_port_read; i++) - { - std::string str_address; - if (_param->_have_port_address) - str_address = "conv_integer(in_READ_"+toString(i)+"_ADDRESS)"; - else - str_address = "0"; - - vhdl->set_body (0,"out_READ_"+toString(i)+"_DATA <= reg_DATA ("+str_address+ - ") when in_READ_"+toString(i)+"_VAL = '1' else "+ - std_logic_others(_param->_size_word,0)+";"); - } - - vhdl->set_body (0,""); - vhdl->set_comment(0,"---------------------------------------------------"); - vhdl->set_comment(0," Write RegisterFile"); - vhdl->set_comment(0,"---------------------------------------------------"); - vhdl->set_body (0,""); - - vhdl->set_body (0,"RegisterFile_write: process (in_CLOCK)"); - vhdl->set_body (0,"begin -- process RegisterFile_write"); - vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); - - for (uint32_t i = 0; i < _param->_nb_port_write; i++) - { - std::string str_address; - if (_param->_have_port_address) - str_address = "conv_integer(in_WRITE_"+toString(i)+"_ADDRESS)"; - else - str_address = "0"; - - vhdl->set_body (2,"if (in_WRITE_"+toString(i)+"_VAL = '1') then"); - vhdl->set_body (3,"reg_DATA("+str_address+") <= in_WRITE_"+toString(i)+"_DATA;"); - vhdl->set_body (2,"end if;"); - } - - vhdl->set_body (1,"end if;"); - vhdl->set_body (0,"end process RegisterFile_write;"); -}; -\end{lstlisting} - -\subsubSection{Fichier RegisterFile\_Monolithic.vhdl} - -\lstparam{VHDL} -\begin{lstlisting}[caption={RegisterFile\_Monolithic.cpp}] - library ieee; - use ieee.numeric_bit.all; - use ieee.numeric_std.all; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_misc.all; ---use ieee.std_logic_signed.all; - use ieee.std_logic_unsigned.all; ---use ieee.std_logic_textio.all; - - -library work; -use work.RegisterFile_Monolithic_Pack.all; - - -entity RegisterFile_Monolithic is - port ( in_CLOCK : in std_logic; - in_NRESET : in std_logic; - in_READ_0_VAL : in std_logic; - out_READ_0_ACK : out std_logic; - in_READ_0_ADDRESS : in std_logic_vector(8 downto 0); - out_READ_0_DATA : out std_logic_vector(31 downto 0); - in_WRITE_0_VAL : in std_logic; - out_WRITE_0_ACK : out std_logic; - in_WRITE_0_ADDRESS: in std_logic_vector(8 downto 0); - in_WRITE_0_DATA : in std_logic_vector(31 downto 0) - ); -end RegisterFile_Monolithic; - -architecture behavioural of RegisterFile_Monolithic is - type Tregfile is array (511 downto 0) of std_logic_vector(31 downto 0); - - signal reg_DATA : Tregfile; - -begin - ----------------------------------------------------- - -- Ackitement - ----------------------------------------------------- - - out_READ_0_ACK <= '1'; - out_WRITE_0_ACK <= '1'; - - ----------------------------------------------------- - -- Read RegisterFile - ----------------------------------------------------- - - out_READ_0_DATA <= reg_DATA (conv_integer(in_READ_0_ADDRESS)) - when in_READ_0_VAL = '1' - else (others => '0'); - - ----------------------------------------------------- - -- Write RegisterFile - ----------------------------------------------------- - - RegisterFile_write: process (in_CLOCK) - begin -- process RegisterFile_write - if in_CLOCK'event and in_CLOCK = '1' then - if (in_WRITE_0_VAL = '1') then - reg_DATA(conv_integer(in_WRITE_0_ADDRESS)) <= in_WRITE_0_DATA; - end if; - end if; - end process RegisterFile_write; -end behavioural; -\end{lstlisting} - -\subSection{Tampon entre la boucle d'exécutione et le buffer de réordonnancement} - -\subsubSection{Fichier Execute\_queue\_vhdl.cpp} - -\lstparam{C++} -\begin{lstlisting}[caption={Execute\_queue\_vhdl.cpp}] -void Execute_queue::vhdl (void) -{ - morpheo::behavioural::generic::queue::Parameters * param_queue; - - param_queue = new morpheo::behavioural::generic::queue::Parameters - (_param->_size_queue, - _param->_size_internal_queue - ); - - morpheo::behavioural::generic::queue::Queue * queue; - - std::string queue_name = _name + "_queue"; - queue = new morpheo::behavioural::generic::queue::Queue - (queue_name.c_str() -#ifdef STATISTICS - ,NULL -#endif - ,param_queue - ,USE_VHDL); - - _component->set_component(queue->_component -#ifdef POSITION - , 50, 50, 50, 50 -#endif - , INSTANCE_LIBRARY - ); - - Vhdl * vhdl = new Vhdl (_name); - - _interfaces->set_port(vhdl); - _component->vhdl_instance(vhdl); - - vhdl_declaration (vhdl); - vhdl_body (vhdl); - - vhdl->generate_file(); - - delete vhdl; -}; -\end{lstlisting} - -\subsubSection{Fichier Execute\_queue\_vhdl\_declaration.cpp} - -\lstparam{C++} -\begin{lstlisting}[caption={Execute\_queue\_vhdl\_declaration.cpp}] -void Execute_queue::vhdl_declaration (Vhdl * & vhdl) -{ - vhdl->set_alias ("internal_QUEUE_INSERT_VAL ", - 1, - " in_EXECUTE_QUEUE_IN_VAL", - std_logic_range(1)); - vhdl->set_alias ("internal_QUEUE_INSERT_ACK ", - 1, - "out_EXECUTE_QUEUE_IN_ACK", - std_logic_range(1)); - vhdl->set_signal ("internal_QUEUE_INSERT_DATA", - _param->_size_internal_queue); - vhdl->set_signal ("internal_QUEUE_RETIRE_DATA", - _param->_size_internal_queue); - vhdl->set_alias ("internal_QUEUE_RETIRE_VAL ", - 1, - "out_EXECUTE_QUEUE_OUT_VAL", - std_logic_range(1)); - vhdl->set_alias ("internal_QUEUE_RETIRE_ACK ", - 1, - " in_EXECUTE_QUEUE_OUT_ACK", - std_logic_range(1)); - - uint32_t min = 0; - uint32_t max, size; - - if(_param->_have_port_context_id ) - { - size = _param->_size_context_id; - max = min-1+size; - vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_CONTEXT_ID ", - std_logic(size), - "internal_QUEUE_RETIRE_DATA", - std_logic_range(_param->_size_internal_queue,max,min)); - min = max+1; - } - if(_param->_have_port_front_end_id ) - { - size = _param->_size_front_end_id; - max = min-1+size; - vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_FRONT_END_ID ", - std_logic(size), - "internal_QUEUE_RETIRE_DATA", - std_logic_range(_param->_size_internal_queue,max,min)); - min = max+1; - } - if(_param->_have_port_ooo_engine_id ) - { - size = _param->_size_ooo_engine_id; - max = min-1+size; - vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID ", - std_logic(size), - "internal_QUEUE_RETIRE_DATA", - std_logic_range(_param->_size_internal_queue,max,min)); - min = max+1; - } - if(_param->_have_port_rob_ptr) - { - size = _param->_size_rob_ptr; - max = min-1+size; - vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_PACKET_ID ", - std_logic(size), - "internal_QUEUE_RETIRE_DATA", - std_logic_range(_param->_size_internal_queue,max,min)); - min = max+1; - } - - size = _param->_size_special_data; - max = min-1+size; - vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_FLAGS ", - std_logic(size), - "internal_QUEUE_RETIRE_DATA", - std_logic_range(_param->_size_internal_queue,max,min)); - min = max+1; - - size = _param->_size_exception; - max = min-1+size; - vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_EXCEPTION ", - std_logic(size), - "internal_QUEUE_RETIRE_DATA", - std_logic_range(_param->_size_internal_queue,max,min)); - min = max+1; - - size = 1; - max = min-1+size; - vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE ", - std_logic(size), - "internal_QUEUE_RETIRE_DATA", - std_logic_range(_param->_size_internal_queue,max,min)); - min = max+1; - - size = _param->_size_instruction_address; - max = min-1+size; - vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_ADDRESS ", - std_logic(size), - "internal_QUEUE_RETIRE_DATA", - std_logic_range(_param->_size_internal_queue,max,min)); - min = max+1; - - size = _param->_size_general_data; - max = min-1+size; - vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_DATA ", - std_logic(size), - "internal_QUEUE_RETIRE_DATA", - std_logic_range(_param->_size_internal_queue,max,min)); - min = max+1; -}; -\end{lstlisting} - -\subsubSection{Fichier Execute\_queue\_vhdl\_body.cpp} - -\lstparam{C++} -\begin{lstlisting}[caption={Execute\_queue\_vhdl\_body.cpp}] -void Execute_queue::vhdl_body (Vhdl * & vhdl) -{ - vhdl->set_comment(0,""); - vhdl->set_comment(0,"-----------------------------------"); - vhdl->set_comment(0,"-- Instance queue "); - vhdl->set_comment(0,"-----------------------------------"); - vhdl->set_comment(0,""); - - vhdl->set_body (0,"instance_"+_name+"_queue : "+_name+"_queue"); - vhdl->set_body (0,"port map ("); - vhdl->set_body (1," in_CLOCK \t=>\t in_CLOCK "); - vhdl->set_body (1,", in_NRESET \t=>\t in_NRESET"); - vhdl->set_body (1,", in_INSERT_VAL \t=>\tinternal_QUEUE_INSERT_VAL"); - vhdl->set_body (1,",out_INSERT_ACK \t=>\tinternal_QUEUE_INSERT_ACK"); - vhdl->set_body (1,", in_INSERT_DATA \t=>\tinternal_QUEUE_INSERT_DATA"); - vhdl->set_body (1,",out_RETIRE_VAL \t=>\tinternal_QUEUE_RETIRE_VAL"); - vhdl->set_body (1,", in_RETIRE_ACK \t=>\tinternal_QUEUE_RETIRE_ACK"); - vhdl->set_body (1,",out_RETIRE_DATA \t=>\tinternal_QUEUE_RETIRE_DATA"); - vhdl->set_body (0,");"); - - vhdl->set_comment(0,""); - vhdl->set_comment(0,"-----------------------------------"); - vhdl->set_comment(0,"-- Input Buffer "); - vhdl->set_comment(0,"-----------------------------------"); - vhdl->set_comment(0,""); - - { - uint32_t min = 0; - uint32_t max, size; - uint32_t size_queue = _param->_size_internal_queue; - - if(_param->_have_port_context_id ) - { - size = _param->_size_context_id; - max = min-1+size; - vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ - " <= in_EXECUTE_QUEUE_IN_CONTEXT_ID;"); - min = max+1; - } - if(_param->_have_port_front_end_id ) - { - size = _param->_size_front_end_id; - max = min-1+size; - vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ - " <= in_EXECUTE_QUEUE_IN_FRONT_END_ID;"); - min = max+1; - } - if(_param->_have_port_ooo_engine_id ) - { - size = _param->_size_ooo_engine_id; - max = min-1+size; - vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ - " <= in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID;"); - min = max+1; - } - if(_param->_have_port_rob_ptr) - { - size = _param->_size_rob_ptr; - max = min-1+size; - vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ - " <= in_EXECUTE_QUEUE_IN_PACKET_ID;"); - min = max+1; - } - - size = _param->_size_special_data; - max = min-1+size; - vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ - " <= in_EXECUTE_QUEUE_IN_FLAGS;"); - min = max+1; - - size = _param->_size_exception; - max = min-1+size; - vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ - " <= in_EXECUTE_QUEUE_IN_EXCEPTION;"); - min = max+1; - - size = 1; - max = min-1+size; - vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ - " <= in_EXECUTE_QUEUE_IN_NO_SEQUENCE;"); - min = max+1; - - size = _param->_size_instruction_address; - max = min-1+size; - vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ - " <= in_EXECUTE_QUEUE_IN_ADDRESS;"); - min = max+1; - - size = _param->_size_general_data; - max = min-1+size; - vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ - " <= in_EXECUTE_QUEUE_IN_DATA;"); - min = max+1; - } - - vhdl->set_comment(0,""); - vhdl->set_comment(0,"-----------------------------------"); - vhdl->set_comment(0,"-- Output Buffer "); - vhdl->set_comment(0,"-----------------------------------"); - vhdl->set_comment(0,""); - - if(_param->_have_port_context_id) - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID "+ - " <= internal_EXECUTE_QUEUE_OUT_CONTEXT_ID ;"); - if(_param->_have_port_front_end_id) - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID "+ - " <= internal_EXECUTE_QUEUE_OUT_FRONT_END_ID ;"); - if(_param->_have_port_ooo_engine_id) - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID"+ - " <= internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID;"); - if(_param->_have_port_rob_ptr) - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_PACKET_ID "+ - " <= internal_EXECUTE_QUEUE_OUT_PACKET_ID ;"); - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_FLAGS "+ - " <= internal_EXECUTE_QUEUE_OUT_FLAGS ;"); - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_EXCEPTION "+ - " <= internal_EXECUTE_QUEUE_OUT_EXCEPTION ;"); - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE "+ - " <= internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE ;"); - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_ADDRESS "+ - " <= internal_EXECUTE_QUEUE_OUT_ADDRESS ;"); - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_DATA "+ - " <= internal_EXECUTE_QUEUE_OUT_DATA ;"); -}; -\end{lstlisting} - -\subsubSection{Fichier Execute\_queue.vhdl} - -\lstparam{VHDL} -\begin{lstlisting}[caption={Execute\_queue.cpp}] -library ieee; - use ieee.numeric_bit.all; - use ieee.numeric_std.all; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_misc.all; ---use ieee.std_logic_signed.all; - use ieee.std_logic_unsigned.all; ---use ieee.std_logic_textio.all; - -library work; -use work.Execute_queue_0_Pack.all; -use work.Execute_queue_0_queue_Pack.all; - -entity Execute_queue_0 is - port ( - in_CLOCK : in std_logic; - in_NRESET : in std_logic; - in_EXECUTE_QUEUE_IN_VAL : in std_logic; - out_EXECUTE_QUEUE_IN_ACK : out std_logic; - in_EXECUTE_QUEUE_IN_CONTEXT_ID : in std_logic; - in_EXECUTE_QUEUE_IN_FRONT_END_ID : in std_logic; - in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID : in std_logic; - in_EXECUTE_QUEUE_IN_PACKET_ID : in std_logic_vector(5 downto 0); - in_EXECUTE_QUEUE_IN_FLAGS : in std_logic_vector(1 downto 0); - in_EXECUTE_QUEUE_IN_EXCEPTION : in std_logic_vector(4 downto 0); - in_EXECUTE_QUEUE_IN_NO_SEQUENCE : in std_logic; - in_EXECUTE_QUEUE_IN_ADDRESS : in std_logic_vector(31 downto 0); - in_EXECUTE_QUEUE_IN_DATA : in std_logic_vector(31 downto 0); - out_EXECUTE_QUEUE_OUT_VAL : out std_logic; - in_EXECUTE_QUEUE_OUT_ACK : in std_logic; - out_EXECUTE_QUEUE_OUT_CONTEXT_ID : out std_logic; - out_EXECUTE_QUEUE_OUT_FRONT_END_ID : out std_logic; - out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID : out std_logic; - out_EXECUTE_QUEUE_OUT_PACKET_ID : out std_logic_vector(5 downto 0); - out_EXECUTE_QUEUE_OUT_FLAGS : out std_logic_vector(1 downto 0); - out_EXECUTE_QUEUE_OUT_EXCEPTION : out std_logic_vector(4 downto 0); - out_EXECUTE_QUEUE_OUT_NO_SEQUENCE : out std_logic; - out_EXECUTE_QUEUE_OUT_ADDRESS : out std_logic_vector(31 downto 0); - out_EXECUTE_QUEUE_OUT_DATA : out std_logic_vector(31 downto 0) - ); -end Execute_queue_0; - -architecture behavioural of Execute_queue_0 is - - signal internal_QUEUE_INSERT_DATA : std_logic_vector(80 downto 0); - signal internal_QUEUE_RETIRE_DATA : std_logic_vector(80 downto 0); - - alias internal_QUEUE_INSERT_VAL : std_logic is - in_EXECUTE_QUEUE_IN_VAL; - alias internal_QUEUE_INSERT_ACK : std_logic is - out_EXECUTE_QUEUE_IN_ACK; - alias internal_QUEUE_RETIRE_VAL : std_logic is - out_EXECUTE_QUEUE_OUT_VAL; - alias internal_QUEUE_RETIRE_ACK : std_logic is - in_EXECUTE_QUEUE_OUT_ACK; - alias internal_EXECUTE_QUEUE_OUT_CONTEXT_ID : std_logic is - internal_QUEUE_RETIRE_DATA (0); - alias internal_EXECUTE_QUEUE_OUT_FRONT_END_ID : std_logic is - internal_QUEUE_RETIRE_DATA (1); - alias internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID : std_logic is - internal_QUEUE_RETIRE_DATA (2); - alias internal_EXECUTE_QUEUE_OUT_PACKET_ID : std_logic_vector(5 downto 0) is - internal_QUEUE_RETIRE_DATA (8 downto 3); - alias internal_EXECUTE_QUEUE_OUT_FLAGS : std_logic_vector(1 downto 0) is - internal_QUEUE_RETIRE_DATA (10 downto 9); - alias internal_EXECUTE_QUEUE_OUT_EXCEPTION : std_logic_vector(4 downto 0) is - internal_QUEUE_RETIRE_DATA (15 downto 11); - alias internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE : std_logic is - internal_QUEUE_RETIRE_DATA (16); - alias internal_EXECUTE_QUEUE_OUT_ADDRESS : std_logic_vector(31 downto 0) is - internal_QUEUE_RETIRE_DATA (48 downto 17); - alias internal_EXECUTE_QUEUE_OUT_DATA : std_logic_vector(31 downto 0) is - internal_QUEUE_RETIRE_DATA (80 downto 49); - -begin - -- - -- ----------------------------------- - -- -- Instance queue - -- ----------------------------------- - -- - instance_Execute_queue_0_queue : Execute_queue_0_queue - port map ( - in_CLOCK => in_CLOCK - , in_NRESET => in_NRESET - , in_INSERT_VAL => internal_QUEUE_INSERT_VAL - ,out_INSERT_ACK => internal_QUEUE_INSERT_ACK - , in_INSERT_DATA => internal_QUEUE_INSERT_DATA - ,out_RETIRE_VAL => internal_QUEUE_RETIRE_VAL - , in_RETIRE_ACK => internal_QUEUE_RETIRE_ACK - ,out_RETIRE_DATA => internal_QUEUE_RETIRE_DATA - ); - -- - -- ----------------------------------- - -- -- Input Buffer - -- ----------------------------------- - -- - internal_QUEUE_INSERT_DATA (0) <= in_EXECUTE_QUEUE_IN_CONTEXT_ID; - internal_QUEUE_INSERT_DATA (1) <= in_EXECUTE_QUEUE_IN_FRONT_END_ID; - internal_QUEUE_INSERT_DATA (2) <= in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID; - internal_QUEUE_INSERT_DATA (8 downto 3) <= in_EXECUTE_QUEUE_IN_PACKET_ID; - internal_QUEUE_INSERT_DATA (10 downto 9) <= in_EXECUTE_QUEUE_IN_FLAGS; - internal_QUEUE_INSERT_DATA (15 downto 11) <= in_EXECUTE_QUEUE_IN_EXCEPTION; - internal_QUEUE_INSERT_DATA (16) <= in_EXECUTE_QUEUE_IN_NO_SEQUENCE; - internal_QUEUE_INSERT_DATA (48 downto 17) <= in_EXECUTE_QUEUE_IN_ADDRESS; - internal_QUEUE_INSERT_DATA (80 downto 49) <= in_EXECUTE_QUEUE_IN_DATA; - -- - -- ----------------------------------- - -- -- Output Buffer - -- ----------------------------------- - -- - out_EXECUTE_QUEUE_OUT_CONTEXT_ID <= internal_EXECUTE_QUEUE_OUT_CONTEXT_ID; - out_EXECUTE_QUEUE_OUT_FRONT_END_ID <= internal_EXECUTE_QUEUE_OUT_FRONT_END_ID; - out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID <= internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID; - out_EXECUTE_QUEUE_OUT_PACKET_ID <= internal_EXECUTE_QUEUE_OUT_PACKET_ID; - out_EXECUTE_QUEUE_OUT_FLAGS <= internal_EXECUTE_QUEUE_OUT_FLAGS; - out_EXECUTE_QUEUE_OUT_EXCEPTION <= internal_EXECUTE_QUEUE_OUT_EXCEPTION; - out_EXECUTE_QUEUE_OUT_NO_SEQUENCE <= internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE; - out_EXECUTE_QUEUE_OUT_ADDRESS <= internal_EXECUTE_QUEUE_OUT_ADDRESS; - out_EXECUTE_QUEUE_OUT_DATA <= internal_EXECUTE_QUEUE_OUT_DATA; - -end behavioural; -\end{lstlisting} - - -\Section {Test du VHDL}\label{testbench} - -Lors d'une simulation systemC, \cpu va générer des fichiers de tests pour le modèle VHDL de chaque composant interne. -Ces tests sont tous écrit de la même façon. Soit l'interface X et le signal Y : -\begin{itemize} -\item Une variable {\it counter} indique le numéro de cycle courant. Elle est initialisé à 0. Elle est incrémenté à chaque cycle. -\item Le composant est instancé avec des signaux internes de même nom. -\item Pour chaque cycle, on affecte à chaque entrée la valeur obtenu lors de la simulation systemC. -\item Pour chaque sortie, on définit un signal dont le nom est {\it out\_X\_Y\_test}. Ces signaux sont affecté au valeur obtenu des sorties lors la simulation systemC. -\item Le signal {\it interface\_X\_test\_ok} est égal à 1 si chaque sortie calculé par la simulation VHDL est égal au sortie attendu (calculé par la simulation systemC). -\item Le signal {\it interface\_X\_test\_transaction} est à 1 si tous les signaux de validité et d'aquittement sont à 1. -\item Le signal {\it interface\_X\_test\_tmp} est à 1 si la simulation systemC indique qu'il y a une transaction et que la simulation vhdl indique également une transaction et que toute les sortie sont bien les sorties obtenu. Si la simulation systemC n'indique pas de transaction, on vérifie que c'est également le cas pour la simulation VHDL. -\item Le signal {\it interface\_X\_test} est égal au signal {\it interface\_X\_test\_tmp} quand il n'y a pas de reset. sinon il est positionné à 1. -\item Le signal {\it test} est un et logique entre tout tous les signaux {\it interface\_X\_test}. -\item La simulation VHDL ce termine si le signal {\it test} vaut 0 (dans ce cas, le test est un échec), ou que le registre {\it counter} vaut le nombre de cycle requis par la simulation systemC (dans ce cas, le test est un succès). -\end{itemize} - -Nous pouvons remarquer que : -\begin{itemize} -\item Nous vérifions la compatibilité au cycle des transactions entre le modèle systemC et le modèle VHDL. -\item Nous vérifions la compatibilité au bit près des données échangé lors qu'il y a une transaction sur une interface. -\item Nous ne vérifions pas la compatibilité au bit près des données présente sur une interface qui ne fait pas de transaction lors d'un cycle. -\end{itemize} - -\lstparam{VHDL} -\begin{lstlisting}[caption={Execute\_queue\_Testbench.vhdl}] -library ieee; - use ieee.numeric_bit.all; - use ieee.numeric_std.all; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_misc.all; ---use ieee.std_logic_signed.all; - use ieee.std_logic_unsigned.all; ---use ieee.std_logic_textio.all; - -library work; -use work.Execute_queue_0_Pack.all; - -entity Execute_queue_0_Testbench is -end Execute_queue_0_Testbench; - -architecture behavioural of Execute_queue_0_Testbench is - - signal in_CLOCK : std_logic := '0'; - signal in_NRESET : std_logic := '0'; - signal in_EXECUTE_QUEUE_IN_VAL : std_logic; - signal out_EXECUTE_QUEUE_IN_ACK : std_logic; - signal out_EXECUTE_QUEUE_IN_ACK_test : std_logic; - signal in_EXECUTE_QUEUE_IN_PACKET_ID : std_logic_vector(3 downto 0); - signal in_EXECUTE_QUEUE_IN_FLAGS : std_logic_vector(1 downto 0); - signal in_EXECUTE_QUEUE_IN_EXCEPTION : std_logic_vector(4 downto 0); - signal in_EXECUTE_QUEUE_IN_NO_SEQUENCE : std_logic; - signal in_EXECUTE_QUEUE_IN_ADDRESS : std_logic_vector(31 downto 0); - signal in_EXECUTE_QUEUE_IN_DATA : std_logic_vector(31 downto 0); - signal out_EXECUTE_QUEUE_OUT_VAL : std_logic; - signal out_EXECUTE_QUEUE_OUT_VAL_test : std_logic; - signal in_EXECUTE_QUEUE_OUT_ACK : std_logic; - signal out_EXECUTE_QUEUE_OUT_PACKET_ID : std_logic_vector(3 downto 0); - signal out_EXECUTE_QUEUE_OUT_PACKET_ID_test : std_logic_vector(3 downto 0); - signal out_EXECUTE_QUEUE_OUT_FLAGS : std_logic_vector(1 downto 0); - signal out_EXECUTE_QUEUE_OUT_FLAGS_test : std_logic_vector(1 downto 0); - signal out_EXECUTE_QUEUE_OUT_EXCEPTION : std_logic_vector(4 downto 0); - signal out_EXECUTE_QUEUE_OUT_EXCEPTION_test : std_logic_vector(4 downto 0); - signal out_EXECUTE_QUEUE_OUT_NO_SEQUENCE : std_logic; - signal out_EXECUTE_QUEUE_OUT_NO_SEQUENCE_test : std_logic; - signal out_EXECUTE_QUEUE_OUT_ADDRESS : std_logic_vector(31 downto 0); - signal out_EXECUTE_QUEUE_OUT_ADDRESS_test : std_logic_vector(31 downto 0); - signal out_EXECUTE_QUEUE_OUT_DATA : std_logic_vector(31 downto 0); - signal out_EXECUTE_QUEUE_OUT_DATA_test : std_logic_vector(31 downto 0); - - signal counter : natural; - signal test : std_logic; - signal interface_test : std_logic; - signal interface_test_ok : std_logic; - signal interface_execute_queue_in_test : std_logic; - signal interface_execute_queue_in_test_ok : std_logic; - signal interface_execute_queue_in_test_transaction : std_logic; - signal interface_execute_queue_in_test_tmp : std_logic; - signal interface_execute_queue_out_test : std_logic; - signal interface_execute_queue_out_test_ok : std_logic; - signal interface_execute_queue_out_test_transaction : std_logic; - signal interface_execute_queue_out_test_tmp : std_logic; - -begin - - ------------------------------------------------------ - -- Component - Intanciation - ------------------------------------------------------ - - instance_Execute_queue_0 : Execute_queue_0 - port map ( - in_CLOCK => in_CLOCK - , in_NRESET => in_NRESET - , in_EXECUTE_QUEUE_IN_VAL => in_EXECUTE_QUEUE_IN_VAL - ,out_EXECUTE_QUEUE_IN_ACK => out_EXECUTE_QUEUE_IN_ACK - , in_EXECUTE_QUEUE_IN_PACKET_ID => in_EXECUTE_QUEUE_IN_PACKET_ID - , in_EXECUTE_QUEUE_IN_FLAGS => in_EXECUTE_QUEUE_IN_FLAGS - , in_EXECUTE_QUEUE_IN_EXCEPTION => in_EXECUTE_QUEUE_IN_EXCEPTION - , in_EXECUTE_QUEUE_IN_NO_SEQUENCE => in_EXECUTE_QUEUE_IN_NO_SEQUENCE - , in_EXECUTE_QUEUE_IN_ADDRESS => in_EXECUTE_QUEUE_IN_ADDRESS - , in_EXECUTE_QUEUE_IN_DATA => in_EXECUTE_QUEUE_IN_DATA - ,out_EXECUTE_QUEUE_OUT_VAL => out_EXECUTE_QUEUE_OUT_VAL - , in_EXECUTE_QUEUE_OUT_ACK => in_EXECUTE_QUEUE_OUT_ACK - ,out_EXECUTE_QUEUE_OUT_PACKET_ID => out_EXECUTE_QUEUE_OUT_PACKET_ID - ,out_EXECUTE_QUEUE_OUT_FLAGS => out_EXECUTE_QUEUE_OUT_FLAGS - ,out_EXECUTE_QUEUE_OUT_EXCEPTION => out_EXECUTE_QUEUE_OUT_EXCEPTION - ,out_EXECUTE_QUEUE_OUT_NO_SEQUENCE => out_EXECUTE_QUEUE_OUT_NO_SEQUENCE - ,out_EXECUTE_QUEUE_OUT_ADDRESS => out_EXECUTE_QUEUE_OUT_ADDRESS - ,out_EXECUTE_QUEUE_OUT_DATA => out_EXECUTE_QUEUE_OUT_DATA - ); - ------------------------------------------------------ - -- interface "" - ------------------------------------------------------ - - -- Test exhaustive - - interface_test_ok <= '1' when true - else '0'; - - interface_test <= '1' when (in_NRESET = '0') else interface_test_ok; - ------------------------------------------------------ - -- interface "execute_queue_in" - ------------------------------------------------------ - - with counter select - in_EXECUTE_QUEUE_IN_VAL <= - '0' when 0, - '0' when 1, - '0' when 2, - '0' when 3, - '0' when 4, - '1' when 5, - '1' when 6, - '0' when 7, - '0' when 8, - '1' when 9, - '1' when 10, - '1' when 11, - '1' when 12, - '1' when 13, - '1' when 14, - '1' when 15, - '1' when 16, - '0' when 17, - '1' when 18, - '1' when 19, - '1' when 20, - '0' when 21, - '1' when 22, - '1' when 23, - '0' when 24, - '1' when 25, - '0' when 26, - '0' when others; - - with counter select - out_EXECUTE_QUEUE_IN_ACK_test <= - '0' when 0, - '1' when 1, - '1' when 2, - '1' when 3, - '1' when 4, - '1' when 5, - '1' when 6, - '1' when 7, - '1' when 8, - '1' when 9, - '1' when 10, - '1' when 11, - '1' when 12, - '1' when 13, - '1' when 14, - '1' when 15, - '1' when 16, - '1' when 17, - '1' when 18, - '1' when 19, - '1' when 20, - '1' when 21, - '1' when 22, - '1' when 23, - '1' when 24, - '1' when 25, - '1' when 26, - '0' when others; - - with counter select - in_EXECUTE_QUEUE_IN_PACKET_ID <= - "0000" when 0, - "0000" when 1, - "0000" when 2, - "0000" when 3, - "0000" when 4, - "0000" when 5, - "0001" when 6, - "0001" when 7, - "0001" when 8, - "0010" when 9, - "0011" when 10, - "0100" when 11, - "0101" when 12, - "0110" when 13, - "0111" when 14, - "1000" when 15, - "1001" when 16, - "1001" when 17, - "1010" when 18, - "1011" when 19, - "1100" when 20, - "1100" when 21, - "1101" when 22, - "1110" when 23, - "1110" when 24, - "1111" when 25, - "1111" when 26, - (others => '0') when others; - - with counter select - in_EXECUTE_QUEUE_IN_FLAGS <= - "00" when 0, - "00" when 1, - "00" when 2, - "00" when 3, - "00" when 4, - "11" when 5, - "11" when 6, - "11" when 7, - "11" when 8, - "00" when 9, - "11" when 10, - "11" when 11, - "11" when 12, - "10" when 13, - "01" when 14, - "01" when 15, - "11" when 16, - "11" when 17, - "10" when 18, - "00" when 19, - "11" when 20, - "11" when 21, - "10" when 22, - "01" when 23, - "01" when 24, - "01" when 25, - "01" when 26, - (others => '0') when others; - - with counter select - in_EXECUTE_QUEUE_IN_EXCEPTION <= - "00000" when 0, - "00000" when 1, - "00000" when 2, - "00000" when 3, - "00000" when 4, - "10001" when 5, - "10010" when 6, - "10010" when 7, - "10010" when 8, - "11011" when 9, - "10011" when 10, - "10001" when 11, - "11000" when 12, - "11011" when 13, - "00001" when 14, - "00001" when 15, - "01010" when 16, - "01010" when 17, - "01100" when 18, - "01100" when 19, - "11011" when 20, - "11011" when 21, - "00101" when 22, - "01001" when 23, - "01001" when 24, - "10001" when 25, - "10001" when 26, - (others => '0') when others; - - with counter select - in_EXECUTE_QUEUE_IN_NO_SEQUENCE <= - '0' when 0, - '0' when 1, - '0' when 2, - '0' when 3, - '0' when 4, - '1' when 5, - '1' when 6, - '1' when 7, - '1' when 8, - '1' when 9, - '1' when 10, - '1' when 11, - '1' when 12, - '1' when 13, - '1' when 14, - '1' when 15, - '1' when 16, - '1' when 17, - '1' when 18, - '1' when 19, - '1' when 20, - '1' when 21, - '1' when 22, - '1' when 23, - '1' when 24, - '1' when 25, - '1' when 26, - '0' when others; - - with counter select - in_EXECUTE_QUEUE_IN_ADDRESS <= - "00000000000000000000000000000000" when 0, - "00000000000000000000000000000000" when 1, - "00000000000000000000000000000000" when 2, - "00000000000000000000000000000000" when 3, - "00000000000000000000000000000000" when 4, - "00101010111010001001010001001010" when 5, - "01111001111000101010100111100011" when 6, - "01111001111000101010100111100011" when 7, - "01111001111000101010100111100011" when 8, - "00010001100100001100110111100111" when 9, - "01000001101001111100010011001001" when 10, - "00100101011100010011000010100011" when 11, - "01100111011000111000010001011110" when 12, - "01110001111100110010010001010100" when 13, - "01110011011110111000110111011100" when 14, - "01000100000010111010110111111100" when 15, - "01010001111010101101001101101011" when 16, - "01010001111010101101001101101011" when 17, - "00011101010011101101010000111011" when 18, - "00111000010000110111111111011011" when 19, - "01111001101000011101111010101010" when 20, - "01111001101000011101111010101010" when 21, - "01100100100110111011011101111100" when 22, - "00010101101101011010111101011100" when 23, - "00010101101101011010111101011100" when 24, - "01010111100110111110010011110001" when 25, - "01010111100110111110010011110001" when 26, - (others => '0') when others; - - with counter select - in_EXECUTE_QUEUE_IN_DATA <= - "00000000000000000000000000000000" when 0, - "00000000000000000000000000000000" when 1, - "00000000000000000000000000000000" when 2, - "00000000000000000000000000000000" when 3, - "00000000000000000000000000000000" when 4, - "01100010010101010101100011101100" when 5, - "01110101010001011110000101000110" when 6, - "01110101010001011110000101000110" when 7, - "01110101010001011110000101000110" when 8, - "01100110111011110100001110001101" when 9, - "01101011011010000000011110011010" when 10, - "01100010101110111101100101011010" when 11, - "01110101101000101010100011010100" when 12, - "00101100101010001000011000010001" when 13, - "01101100111010101111000010000111" when 14, - "00000101000001110010001101100111" when 15, - "00101101010100010111011110010110" when 16, - "00101101010100010111011110010110" when 17, - "01110010010110100000011011111011" when 18, - "01110110010001001010010001011100" when 19, - "01110101110001101100001100111010" when 20, - "01110101110001101100001100111010" when 21, - "00100111010110101100011110010100" when 22, - "01110100000100100010011010111011" when 23, - "01110100000100100010011010111011" when 24, - "00110001000011000101000010110011" when 25, - "00110001000011000101000010110011" when 26, - (others => '0') when others; - - -- Test partial - - interface_execute_queue_in_test_ok <= '1' when true - and out_EXECUTE_QUEUE_IN_ACK = out_EXECUTE_QUEUE_IN_ACK_test - else '0'; - - interface_execute_queue_in_test_transaction <= '1' - and in_EXECUTE_QUEUE_IN_VAL - and out_EXECUTE_QUEUE_IN_ACK - ; - - with counter select - interface_execute_queue_in_test_tmp <= - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 5, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 6, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 9, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 10, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 11, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 12, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 13, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 14, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 15, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 16, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 18, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 19, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 20, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 22, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 23, - interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok - when 25, - not interface_execute_queue_in_test_transaction when others; - - interface_execute_queue_in_test <= '1' when (in_NRESET = '0') else - interface_execute_queue_in_test_tmp; - ------------------------------------------------------ - -- interface "execute_queue_out" - ------------------------------------------------------ - - with counter select - out_EXECUTE_QUEUE_OUT_VAL_test <= - '0' when 0, - '0' when 1, - '0' when 2, - '0' when 3, - '0' when 4, - '0' when 5, - '1' when 6, - '1' when 7, - '0' when 8, - '0' when 9, - '1' when 10, - '1' when 11, - '1' when 12, - '1' when 13, - '1' when 14, - '1' when 15, - '1' when 16, - '1' when 17, - '0' when 18, - '1' when 19, - '1' when 20, - '1' when 21, - '1' when 22, - '1' when 23, - '1' when 24, - '0' when 25, - '1' when 26, - '0' when others; - - with counter select - in_EXECUTE_QUEUE_OUT_ACK <= - '0' when 0, - '0' when 1, - '0' when 2, - '0' when 3, - '0' when 4, - '1' when 5, - '1' when 6, - '1' when 7, - '1' when 8, - '0' when 9, - '1' when 10, - '1' when 11, - '1' when 12, - '1' when 13, - '1' when 14, - '1' when 15, - '1' when 16, - '1' when 17, - '1' when 18, - '1' when 19, - '1' when 20, - '0' when 21, - '1' when 22, - '1' when 23, - '1' when 24, - '1' when 25, - '1' when 26, - '0' when others; - - with counter select - out_EXECUTE_QUEUE_OUT_PACKET_ID_test <= - "0000" when 0, - "0000" when 1, - "0000" when 2, - "0000" when 3, - "0000" when 4, - "0000" when 5, - "0000" when 6, - "0001" when 7, - "0001" when 8, - "0001" when 9, - "0010" when 10, - "0011" when 11, - "0100" when 12, - "0101" when 13, - "0110" when 14, - "0111" when 15, - "1000" when 16, - "1001" when 17, - "1001" when 18, - "1010" when 19, - "1011" when 20, - "1100" when 21, - "1100" when 22, - "1101" when 23, - "1110" when 24, - "1110" when 25, - "1111" when 26, - (others => '0') when others; - - with counter select - out_EXECUTE_QUEUE_OUT_FLAGS_test <= - "00" when 0, - "00" when 1, - "00" when 2, - "00" when 3, - "00" when 4, - "00" when 5, - "11" when 6, - "11" when 7, - "11" when 8, - "11" when 9, - "00" when 10, - "11" when 11, - "11" when 12, - "11" when 13, - "10" when 14, - "01" when 15, - "01" when 16, - "11" when 17, - "11" when 18, - "10" when 19, - "00" when 20, - "11" when 21, - "11" when 22, - "10" when 23, - "01" when 24, - "01" when 25, - "01" when 26, - (others => '0') when others; - - with counter select - out_EXECUTE_QUEUE_OUT_EXCEPTION_test <= - "00000" when 0, - "00000" when 1, - "00000" when 2, - "00000" when 3, - "00000" when 4, - "00000" when 5, - "10001" when 6, - "10010" when 7, - "10010" when 8, - "10010" when 9, - "11011" when 10, - "10011" when 11, - "10001" when 12, - "11000" when 13, - "11011" when 14, - "00001" when 15, - "00001" when 16, - "01010" when 17, - "01010" when 18, - "01100" when 19, - "01100" when 20, - "11011" when 21, - "11011" when 22, - "00101" when 23, - "01001" when 24, - "01001" when 25, - "10001" when 26, - (others => '0') when others; - - with counter select - out_EXECUTE_QUEUE_OUT_NO_SEQUENCE_test <= - '0' when 0, - '0' when 1, - '0' when 2, - '0' when 3, - '0' when 4, - '0' when 5, - '1' when 6, - '1' when 7, - '1' when 8, - '1' when 9, - '1' when 10, - '1' when 11, - '1' when 12, - '1' when 13, - '1' when 14, - '1' when 15, - '1' when 16, - '1' when 17, - '1' when 18, - '1' when 19, - '1' when 20, - '1' when 21, - '1' when 22, - '1' when 23, - '1' when 24, - '1' when 25, - '1' when 26, - '0' when others; - - with counter select - out_EXECUTE_QUEUE_OUT_ADDRESS_test <= - "00000000000000000000000000000000" when 0, - "00000000000000000000000000000000" when 1, - "00000000000000000000000000000000" when 2, - "00000000000000000000000000000000" when 3, - "00000000000000000000000000000000" when 4, - "00000000000000000000000000000000" when 5, - "00101010111010001001010001001010" when 6, - "01111001111000101010100111100011" when 7, - "01111001111000101010100111100011" when 8, - "01111001111000101010100111100011" when 9, - "00010001100100001100110111100111" when 10, - "01000001101001111100010011001001" when 11, - "00100101011100010011000010100011" when 12, - "01100111011000111000010001011110" when 13, - "01110001111100110010010001010100" when 14, - "01110011011110111000110111011100" when 15, - "01000100000010111010110111111100" when 16, - "01010001111010101101001101101011" when 17, - "01010001111010101101001101101011" when 18, - "00011101010011101101010000111011" when 19, - "00111000010000110111111111011011" when 20, - "01111001101000011101111010101010" when 21, - "01111001101000011101111010101010" when 22, - "01100100100110111011011101111100" when 23, - "00010101101101011010111101011100" when 24, - "00010101101101011010111101011100" when 25, - "01010111100110111110010011110001" when 26, - (others => '0') when others; - - with counter select - out_EXECUTE_QUEUE_OUT_DATA_test <= - "00000000000000000000000000000000" when 0, - "00000000000000000000000000000000" when 1, - "00000000000000000000000000000000" when 2, - "00000000000000000000000000000000" when 3, - "00000000000000000000000000000000" when 4, - "00000000000000000000000000000000" when 5, - "01100010010101010101100011101100" when 6, - "01110101010001011110000101000110" when 7, - "01110101010001011110000101000110" when 8, - "01110101010001011110000101000110" when 9, - "01100110111011110100001110001101" when 10, - "01101011011010000000011110011010" when 11, - "01100010101110111101100101011010" when 12, - "01110101101000101010100011010100" when 13, - "00101100101010001000011000010001" when 14, - "01101100111010101111000010000111" when 15, - "00000101000001110010001101100111" when 16, - "00101101010100010111011110010110" when 17, - "00101101010100010111011110010110" when 18, - "01110010010110100000011011111011" when 19, - "01110110010001001010010001011100" when 20, - "01110101110001101100001100111010" when 21, - "01110101110001101100001100111010" when 22, - "00100111010110101100011110010100" when 23, - "01110100000100100010011010111011" when 24, - "01110100000100100010011010111011" when 25, - "00110001000011000101000010110011" when 26, - (others => '0') when others; - - -- Test partial - - interface_execute_queue_out_test_ok <= '1' when true - and out_EXECUTE_QUEUE_OUT_VAL = out_EXECUTE_QUEUE_OUT_VAL_test - and out_EXECUTE_QUEUE_OUT_PACKET_ID = out_EXECUTE_QUEUE_OUT_PACKET_ID_test - and out_EXECUTE_QUEUE_OUT_FLAGS = out_EXECUTE_QUEUE_OUT_FLAGS_test - and out_EXECUTE_QUEUE_OUT_EXCEPTION = out_EXECUTE_QUEUE_OUT_EXCEPTION_test - and out_EXECUTE_QUEUE_OUT_NO_SEQUENCE = out_EXECUTE_QUEUE_OUT_NO_SEQUENCE_test - and out_EXECUTE_QUEUE_OUT_ADDRESS = out_EXECUTE_QUEUE_OUT_ADDRESS_test - and out_EXECUTE_QUEUE_OUT_DATA = out_EXECUTE_QUEUE_OUT_DATA_test - else '0'; - - interface_execute_queue_out_test_transaction <= '1' - and out_EXECUTE_QUEUE_OUT_VAL - and in_EXECUTE_QUEUE_OUT_ACK - ; - - with counter select - interface_execute_queue_out_test_tmp <= - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 6, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 7, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 10, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 11, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 12, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 13, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 14, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 15, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 16, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 17, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 19, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 20, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 22, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 23, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 24, - interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok - when 26, - not interface_execute_queue_out_test_transaction when others; - - interface_execute_queue_out_test <= '1' when (in_NRESET = '0') else - interface_execute_queue_out_test_tmp; - - ------------------------------------------------------ - -- Test - ------------------------------------------------------ - - test <= '1' - and interface_test - and interface_execute_queue_in_test - and interface_execute_queue_out_test; - - ------------------------------------------------------ - -- reset - ------------------------------------------------------ - - -- if the systemC simulate have multiple reset, we make the last - in_NRESET <= '1' after 150 ns; - - ------------------------------------------------------ - -- process clock_name - ------------------------------------------------------ - - in_CLOCK <= not in_CLOCK after 50 ns; - - process (in_CLOCK) - begin - if (in_CLOCK'event and in_CLOCK = '1') then - - if (in_NRESET = '0') then - counter <= 4; - else - counter <= counter+1; - - assert not (counter >= 27) report "Test OK" severity FAILURE; - assert not (test = '0') report "Test KO" severity FAILURE; - end if; - end if; - end process; -end behavioural; -\end{lstlisting} +\input{\dirroot/document-morpheo-vhdl_generation-fr-01_tree} +\input{\dirroot/document-morpheo-vhdl_generation-fr-02_vhdl_declaration} +\input{\dirroot/document-morpheo-vhdl_generation-fr-03_vhdl_body} +\input{\dirroot/document-morpheo-vhdl_generation-fr-04_vhdl_structural} +\input{\dirroot/document-morpheo-vhdl_generation-fr-05_example} +\input{\dirroot/document-morpheo-vhdl_generation-fr-06_testbench} Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_1.cfg (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_1.cfg (revision 100) @@ -1,5 +1,5 @@ - + Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_2.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_2.cfg (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_2.cfg (revision 100) @@ -1,5 +1,5 @@ - + @@ -71,7 +71,7 @@ - + - + Index: trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen (revision 100) @@ -73,5 +73,5 @@ - + Index: trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 100) @@ -8,12 +8,12 @@ - + - - + + - + @@ -23,5 +23,7 @@ - + + + Index: trunk/IPs/systemC/processor/Morpheo/Script/xilinx_extract_info.sh =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Script/xilinx_extract_info.sh (revision 99) +++ trunk/IPs/systemC/processor/Morpheo/Script/xilinx_extract_info.sh (revision 100) @@ -5,9 +5,43 @@ #----------------------------------------------------------- -for i in *.fpga.log; do - echo "===== $i"; - grep "Number of Slice Registers" $i; - grep "Number used as Logic" $i; - grep "Number used as Memory" $i; - grep "Maximum Frequency" $i; -done +##-----[ usage ]--------------------------------------------- +#function usage () +#{ +# echo "Usage : ${0} [files]"; +# echo "Arguments : "; +# echo ' * files : lists of files. If empty, take *.fpga.log'; +## echo "Notes :"; +## echo " * Morpheo's environnement must be positionned."; +# +# exit; +#} + +#-----[ info ]---------------------------------------------- +function info () +{ + echo "===== ${1}"; + grep "Number of Slice Registers" ${1}; + grep "Number of Slice LUTs" ${1}; + grep "Number used as Logic" ${1}; + grep "Number used as Memory" ${1}; + grep "Number used as RAM" ${1}; + grep "Maximum Frequency" ${1}; +} + +#-----[ main ]---------------------------------------------- +function main () +{ + if test $# -eq 0; then + files="*.fpga.log"; + else + files="$*"; + fi; + + for i in $files; do + info $i; + done +} + +#-----[ Corps ]--------------------------------------------- +main ${*} +