Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h	(revision 101)
@@ -133,6 +133,6 @@
     // Address's Read must be aligned
 
-    if ((address & _mask_addr) != 0)
-      TEST_KO("<Memory_t::read> Address is not aligned");
+//     if ((address & _mask_addr) != 0)
+//       TEST_KO("<Memory_t::read> Address is not aligned");
 
     if (context>_nb_context)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp	(revision 101)
@@ -24,6 +24,6 @@
   void Load_store_unit::function_speculative_load_commit_genMealy_dcache (void)
   {
-    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
-    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+    log_begin(Load_store_unit,FUNCTION);
+    log_end  (Load_store_unit,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp	(revision 101)
@@ -24,5 +24,6 @@
   void Load_store_unit::function_speculative_load_commit_genMealy_insert (void)
   {
-    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    log_begin(Load_store_unit,FUNCTION);
+    log_function(Load_store_unit,FUNCTION,_name.c_str());
 
     // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -52,5 +53,5 @@
       PORT_WRITE(out_MEMORY_IN_ACK [i], ack [i]);
 
-    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+    log_end(Load_store_unit,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp	(revision 101)
@@ -24,6 +24,6 @@
   void Load_store_unit::function_speculative_load_commit_genMealy_retire (void)
   {
-    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
-    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+    log_begin(Load_store_unit,FUNCTION);
+    log_end  (Load_store_unit,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 101)
@@ -24,5 +24,6 @@
   void Load_store_unit::function_speculative_load_commit_genMoore (void)
   {
-    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    log_begin(Load_store_unit,FUNCTION);
+    log_function(Load_store_unit,FUNCTION,_name.c_str());
 
     // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -44,7 +45,7 @@
     // Test store and load queue
 
-    log_printf(TRACE,Load_store_unit,FUNCTION,"genMoore : Test MEMORY_OUT");
-
-    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Load  queue");
+    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test MEMORY_OUT");
+
+    log_printf(TRACE,Load_store_unit,FUNCTION,"    * Load  queue");
     for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++)
 //     for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++)
@@ -71,5 +72,6 @@
 							     _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed,
 							     _load_queue [internal_MEMORY_OUT_PTR]._access_size);
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * data : %.8x",data_new);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (old) : %.8x",data_old);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (new) : %.8x",data_new);
 	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * rdata        : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata);
 	    log_printf(TRACE,Load_store_unit,FUNCTION,"      * shift        : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift);
@@ -91,5 +93,5 @@
     if (not internal_MEMORY_OUT_VAL)
       {
-	log_printf(TRACE,Load_store_unit,FUNCTION,"  * Store queue");
+	log_printf(TRACE,Load_store_unit,FUNCTION,"    * Store queue");
 	if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT)
 	  {
@@ -143,5 +145,5 @@
     Tdcache_data_t    dcache_req_wdata     ;
 
-    log_printf(TRACE,Load_store_unit,FUNCTION,"genMoore : Test DCACHE_REQ");
+    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test DCACHE_REQ");
 
     internal_DCACHE_REQ_VAL = 0;
@@ -152,5 +154,5 @@
     if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE)
       {
-	log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue[%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);
+	log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);
 
 	internal_DCACHE_REQ_VAL          = 1;
@@ -169,6 +171,11 @@
 
 	dcache_req_packet_id  = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write);
-	dcache_req_address    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address & _param->_mask_address_msb;
+	dcache_req_address    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb;
 	dcache_req_type       = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation);
+
+// 	log_printf(TRACE,Load_store_unit,FUNCTION,"      * address            : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address);
+//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * mask               : %.8x",_param->_mask_address_msb);
+        log_printf(TRACE,Load_store_unit,FUNCTION,"      * dcache_req_address : %.8x",dcache_req_address);
+
 #ifdef SYSTEMC_VHDL_COMPATIBILITY
 	dcache_req_wdata      = 0;
@@ -210,5 +217,5 @@
     PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
     
-    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+    log_end(Load_store_unit,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 101)
@@ -260,4 +260,6 @@
             (    internal_MEMORY_IN_ACK  == 1))
           {
+            log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_IN [%d]",internal_MEMORY_IN_PORT);
+
 	    // Test operation :
 	    //~~~~~~~~~~~~~~~~~
@@ -440,5 +442,5 @@
             (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1))
           {
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_OUT transaction");
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_OUT[0] transaction");
 
 	    switch (internal_MEMORY_OUT_SELECT_QUEUE)
@@ -498,5 +500,5 @@
             (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1))
           {
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_REQ");
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_REQ[0]");
 
 	    switch (internal_DCACHE_REQ_SELECT_QUEUE)
@@ -602,5 +604,5 @@
             (    internal_DCACHE_RSP_ACK == 1))
           {
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_RSP");
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_RSP [0]");
 
 	    // don't use context_id : because there are one queue for all thread
@@ -610,5 +612,7 @@
 	    Tdcache_error_t error      = PORT_READ(in_DCACHE_RSP_ERROR     [0]);
 
-	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * original packet_id : %d", packet_id);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * original packet_id : %d"  , packet_id);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * rdata              : %.8x", rdata);
+	    log_printf(TRACE,Load_store_unit,FUNCTION,"    * error              : %d"  , error);
 	    
 	    if (DCACHE_RSP_IS_LOAD(packet_id) == 1)
@@ -623,5 +627,6 @@
 		  throw ErrorMorpheo(_("Receive of respons, but the corresponding operation don't wait a respons."));
 #endif
-		
+
+                _load_queue [packet_id]._rdata = rdata;
 		
 		if (error != DCACHE_ERROR_NONE)
@@ -639,6 +644,5 @@
 		    // FIXME : convention : if bus error, the cache return the fautive address !
 		    // But, the load's address is aligned !
-		    _load_queue [packet_id]._rdata = rdata;
-		
+
 		    switch (_load_queue [packet_id]._state)
 		      {
@@ -695,5 +699,5 @@
 	    uint32_t j = (*_speculative_access_queue_control)[i];
 
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.6d, %.2d, %s",
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.4d, %.2d, %s",
                        j,
                        _speculative_access_queue[j]._context_id          ,
@@ -719,5 +723,5 @@
 	    uint32_t j = i;
 
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.6d, %.2d, %s",
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s",
                        j,
                        _load_queue[j]._context_id          ,
