Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp	(revision 101)
@@ -213,4 +213,17 @@
   // Initialisation
 
+  const bool test1  = true;
+  const bool test2  = true;
+  const bool test3  = true;
+  const bool test4  = true;
+  const bool test5  = true;
+  const bool test6  = true;
+  const bool test7  = true;
+  const bool test8  = true;
+  const bool test9  = true;
+  const bool test10 = true;
+  const bool test11 = true;
+  const bool test12 = true;
+
   const uint32_t seed = 0;
 //const uint32_t seed = static_cast<uint32_t>(time(NULL));
@@ -264,5 +277,5 @@
       uint32_t context    = rand()%_param->_nb_context;
 
-      if (1)
+      if (test1)
 	{
 	  SC_START(3);
@@ -285,13 +298,25 @@
 	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
 	  
-	  do
-	    {
-	      in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
-	      
-	      SC_START(1);
-	    }
-	  while (not ( in_DECOD_EVENT_VAL [port]->read() and
-		       out_DECOD_EVENT_ACK [port]->read()));
-	  in_DECOD_EVENT_VAL [port]->write(0);
+          in_DECOD_EVENT_VAL           [port]->write(1);
+
+          SC_START(0);
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  TEST(Tcontrol_t, out_DECOD_EVENT_ACK     [port]   ->read(), 0);
+
+          SC_START(1);
+
+	  in_NB_INST_DECOD_ALL  [context]->write(0);
+	  in_NB_INST_COMMIT_ALL [context]->write(0);
+	  in_NB_INST_COMMIT_MEM [context]->write(0);
+          
+          LABEL("msync (send decod)");
+          SC_START(0);
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  TEST(Tcontrol_t, out_DECOD_EVENT_ACK     [port]   ->read(), 1);
+
+	  SC_START(1);
+
+          in_DECOD_EVENT_VAL     [port]->write(0);
+	  in_NB_INST_COMMIT_ALL  [context]->write(1);
 	  
 	  LABEL("msync (wait end)");
@@ -300,102 +325,16 @@
 	  SC_START(3);
 	  
-	  in_NB_INST_DECOD_ALL  [context]->write(0);
-	  in_NB_INST_COMMIT_ALL [context]->write(1);
-	  in_NB_INST_COMMIT_MEM [context]->write(0);
-	  
-	  SC_START(1);
-	  
-	  LABEL("msync (send decod)");
-	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
-	  
-	  SC_START(3);
-	  
-	  in_NB_INST_DECOD_ALL  [context]->write(1);
-	  SC_START(1);
-	  
-	  LABEL("msync (wait end)");
-	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
-	  in_NB_INST_DECOD_ALL  [context]->write(0);
-	  in_NB_INST_COMMIT_MEM [context]->write(1);
-	  
-	  SC_START(3);
-	  
-	  in_NB_INST_COMMIT_MEM [context]->write(0);
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
+	  in_NB_INST_COMMIT_ALL [context]->write(0);
+
 	  SC_START(1);
 	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
 	}
       
-      if (1)
+      if (test2)
 	{
 	  SC_START(3);
-
+	  
 	  LABEL("psync (begin)");
-	  in_NB_INST_DECOD_ALL  [context]->write(1);
-	  in_NB_INST_COMMIT_ALL [context]->write(1);
-	  in_NB_INST_COMMIT_MEM [context]->write(1);
-	  
-	  uint32_t port = rand()%_param->_nb_decod_unit;
-	  
-	  in_DECOD_EVENT_CONTEXT_ID    [port]->write(context);
-	  in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
-	  in_DECOD_EVENT_ADDRESS       [port]->write(0x200);
-	  in_DECOD_EVENT_ADDRESS_EPCR  [port]->write(0xdeadbebe);
-	  if (_param->_have_port_depth)
-          in_DECOD_EVENT_DEPTH         [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
-	  in_DECOD_EVENT_TYPE          [port]->write(EVENT_TYPE_PSYNC);
-	  
-	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
-	  
-	  do
-	    {
-	      in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
-	  
-	      SC_START(1);
-	    }
-	  while (not ( in_DECOD_EVENT_VAL [port]->read() and
-		       out_DECOD_EVENT_ACK [port]->read()));
-	  in_DECOD_EVENT_VAL [port]->write(0);
-	  
-	  LABEL("psync (wait end)");
-	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
-	  
-	  SC_START(3);
-	  
-	  in_NB_INST_DECOD_ALL  [context]->write(0);
-	  in_NB_INST_COMMIT_ALL [context]->write(0);
-	  in_NB_INST_COMMIT_MEM [context]->write(0);
-	  
-	  SC_START(1);
-
-	  bool find = false;
-	  do
-	    {
-	      in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
-	  
-	      SC_START(0);
-	  
-	      if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
-	        {
-		  TEST(Taddress_t,out_EVENT_ADDRESS          [context]->read(),0x201);
-		  TEST(Taddress_t,out_EVENT_ADDRESS_NEXT     [context]->read(),0xdeadbebe); 
-		  TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
-		  TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE       [context]->read(),0);
-		  
-		  find = true;
-	        }
-	      
-	      SC_START(1);
-	    }
-	  while (not find);
-
-	  in_EVENT_ACK [context]->write(0);
-	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
-	}
-
-      if (1)
-	{
-	  SC_START(3);
-
-	  LABEL("csync (begin)");
 	  in_NB_INST_DECOD_ALL  [context]->write(1);
 	  in_NB_INST_COMMIT_ALL [context]->write(1);
@@ -410,27 +349,38 @@
 	  if (_param->_have_port_depth)
 	  in_DECOD_EVENT_DEPTH         [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
-	  in_DECOD_EVENT_TYPE          [port]->write(EVENT_TYPE_CSYNC);
-	  
-	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
-	  
-	  do
-	    {
-	      in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
-	  
-	      SC_START(1);
-	    }
-	  while (not ( in_DECOD_EVENT_VAL [port]->read() and
-		       out_DECOD_EVENT_ACK [port]->read()));
-	  in_DECOD_EVENT_VAL [port]->write(0);
-	  
-	  LABEL("csync (wait end)");
-	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
-	  
-	  SC_START(3);
-	  
+	  in_DECOD_EVENT_TYPE          [port]->write(EVENT_TYPE_PSYNC);
+	  
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  
+          in_DECOD_EVENT_VAL           [port]->write(1);
+
+          SC_START(0);
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  TEST(Tcontrol_t, out_DECOD_EVENT_ACK     [port]   ->read(), 0);
+
+          SC_START(1);
+
 	  in_NB_INST_DECOD_ALL  [context]->write(0);
 	  in_NB_INST_COMMIT_ALL [context]->write(0);
 	  in_NB_INST_COMMIT_MEM [context]->write(0);
-	  
+          
+          LABEL("psync (send decod)");
+          SC_START(0);
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  TEST(Tcontrol_t, out_DECOD_EVENT_ACK     [port]   ->read(), 1);
+
+	  SC_START(1);
+
+          in_DECOD_EVENT_VAL     [port]->write(0);
+	  in_NB_INST_COMMIT_ALL  [context]->write(1);
+	  
+	  LABEL("psync (wait end)");
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
+	  
+	  SC_START(3);
+	  
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
+	  in_NB_INST_COMMIT_ALL [context]->write(0);
+
 	  SC_START(1);
 
@@ -448,19 +398,21 @@
 		  TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
 		  TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE       [context]->read(),0);
-	  
-		  find = true;
-	        }
-	      
-	      SC_START(1);
-	    }
-	  while (not find);
+		  
+		  find = true;
+	        }
+	      
+	      SC_START(1);
+	    }
+	  while (not find);
+
 	  in_EVENT_ACK [context]->write(0);
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
 	}
 
-      if (1)
+      if (test3)
 	{
 	  SC_START(3);
 	  
-	  LABEL("spr (begin)");
+	  LABEL("csync (begin)");
 	  in_NB_INST_DECOD_ALL  [context]->write(1);
 	  in_NB_INST_COMMIT_ALL [context]->write(1);
@@ -471,6 +423,85 @@
 	  in_DECOD_EVENT_CONTEXT_ID    [port]->write(context);
 	  in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
-	  in_DECOD_EVENT_ADDRESS       [port]->write(0x100);
-	  in_DECOD_EVENT_ADDRESS_EPCR  [port]->write(0xdeadbeef);
+	  in_DECOD_EVENT_ADDRESS       [port]->write(0x300);
+	  in_DECOD_EVENT_ADDRESS_EPCR  [port]->write(0xdead0300);
+	  if (_param->_have_port_depth)
+	  in_DECOD_EVENT_DEPTH         [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
+	  in_DECOD_EVENT_TYPE          [port]->write(EVENT_TYPE_CSYNC);
+	  
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  
+          in_DECOD_EVENT_VAL           [port]->write(1);
+
+          SC_START(0);
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  TEST(Tcontrol_t, out_DECOD_EVENT_ACK     [port]   ->read(), 0);
+
+          SC_START(1);
+
+	  in_NB_INST_DECOD_ALL  [context]->write(0);
+	  in_NB_INST_COMMIT_ALL [context]->write(0);
+	  in_NB_INST_COMMIT_MEM [context]->write(0);
+          
+          LABEL("csync (send decod)");
+          SC_START(0);
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  TEST(Tcontrol_t, out_DECOD_EVENT_ACK     [port]   ->read(), 1);
+
+	  SC_START(1);
+
+          in_DECOD_EVENT_VAL     [port]->write(0);
+	  in_NB_INST_COMMIT_ALL  [context]->write(1);
+	  
+	  LABEL("csync (wait end)");
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
+	  
+	  SC_START(3);
+	  
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
+	  in_NB_INST_COMMIT_ALL [context]->write(0);
+
+	  SC_START(1);
+
+	  bool find = false;
+	  do
+	    {
+	      in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
+	  
+	      SC_START(0);
+	  
+	      if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
+	        {
+		  TEST(Taddress_t,out_EVENT_ADDRESS          [context]->read(),0x301);
+		  TEST(Taddress_t,out_EVENT_ADDRESS_NEXT     [context]->read(),0xdead0300); 
+		  TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
+		  TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE       [context]->read(),0);
+		  
+		  find = true;
+	        }
+	      
+	      SC_START(1);
+	    }
+	  while (not find);
+
+	  in_EVENT_ACK [context]->write(0);
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+
+	}
+
+      if (test4)
+	{
+	  SC_START(3);
+	  
+	  LABEL("spr_access (begin)");
+	  in_NB_INST_DECOD_ALL  [context]->write(1);
+	  in_NB_INST_COMMIT_ALL [context]->write(1);
+	  in_NB_INST_COMMIT_MEM [context]->write(1);
+	  
+	  uint32_t port = rand()%_param->_nb_decod_unit;
+	  
+	  in_DECOD_EVENT_CONTEXT_ID    [port]->write(context);
+	  in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
+	  in_DECOD_EVENT_ADDRESS       [port]->write(0x400);
+	  in_DECOD_EVENT_ADDRESS_EPCR  [port]->write(0xdead0400);
 	  if (_param->_have_port_depth)
 	  in_DECOD_EVENT_DEPTH         [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
@@ -479,46 +510,39 @@
 	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
 	  
-	  do
-	    {
-	      in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
-	      
-	      SC_START(1);
-	    }
-	  while (not ( in_DECOD_EVENT_VAL [port]->read() and
-		       out_DECOD_EVENT_ACK [port]->read()));
-	  in_DECOD_EVENT_VAL [port]->write(0);
-	  
-	  LABEL("spr (wait end)");
-	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
-	  
-	  SC_START(3);
-	  
+          in_DECOD_EVENT_VAL           [port]->write(1);
+
+          SC_START(0);
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  TEST(Tcontrol_t, out_DECOD_EVENT_ACK     [port]   ->read(), 0);
+
+          SC_START(1);
+
 	  in_NB_INST_DECOD_ALL  [context]->write(0);
 	  in_NB_INST_COMMIT_ALL [context]->write(0);
 	  in_NB_INST_COMMIT_MEM [context]->write(0);
-	  
-	  SC_START(1);
-	  
-	  LABEL("spr (send decod)");
-	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
-	  
-	  SC_START(3);
-	  
-	  in_NB_INST_DECOD_ALL  [context]->write(1);
-	  SC_START(1);
-	  
-	  LABEL("spr (wait end)");
-	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
-	  in_NB_INST_DECOD_ALL  [context]->write(0);
-	  in_NB_INST_COMMIT_ALL [context]->write(1);
-	  
-	  SC_START(3);
-	  
-	  in_NB_INST_COMMIT_ALL [context]->write(0);
+          
+          LABEL("spr_access (send decod)");
+          SC_START(0);
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  TEST(Tcontrol_t, out_DECOD_EVENT_ACK     [port]   ->read(), 1);
+
+	  SC_START(1);
+
+          in_DECOD_EVENT_VAL     [port]->write(0);
+	  in_NB_INST_COMMIT_ALL  [context]->write(1);
+	  
+	  LABEL("spr_access (wait end)");
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
+	  
+	  SC_START(3);
+	  
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
+	  in_NB_INST_COMMIT_ALL [context]->write(0);
+
 	  SC_START(1);
 	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
 	}
 
-      if (1)
+      if (test5)
 	{
 	  SC_START(3);
@@ -610,5 +634,5 @@
 	}
 
-      if (1)
+      if (test6)
 	{
 	  SC_START(3);
@@ -697,5 +721,5 @@
 	}
 
-      if (1)
+      if (test7)
 	{
 	  SC_START(3);
@@ -791,5 +815,5 @@
 	}
 
-      if (1)
+      if (test8)
 	{
 	  SC_START(3);
@@ -885,5 +909,5 @@
 	}
 
-      if (1)
+      if (test9)
 	{
 	  SC_START(3);
@@ -979,5 +1003,5 @@
 	}
       
-      if (1)
+      if (test10)
 	{
 	  SC_START(3);
@@ -1073,5 +1097,5 @@
 	}
 
-      if (1)
+      if (test11)
 	{
 	  SC_START(3);
@@ -1167,5 +1191,5 @@
 	}
       
-      if (1)
+      if (test12)
 	{
 	  SC_START(3);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h	(revision 101)
@@ -197,4 +197,5 @@
   public  : void        transition                (void);
   public  : void        genMoore                  (void);
+  public  : void        genMealy_decod_event      (void);
 #endif					       
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h	(revision 101)
@@ -29,17 +29,17 @@
       CONTEXT_STATE_KO_EXCEP_ADDR   , // update address manager
       CONTEXT_STATE_KO_EXCEP_SPR    , // update spr (epc, esr, sr[DSX])
-      CONTEXT_STATE_KO_MISS         , // wait end of event (miss (branch, load))
       CONTEXT_STATE_KO_MISS_ADDR    , // update address manager
-      CONTEXT_STATE_KO_MSYNC        , // wait completion of all memory operation
-      CONTEXT_STATE_KO_MSYNC_ISSUE  , // issue msync operation
+      CONTEXT_STATE_KO_MISS_WAITEND , // wait end of event (miss (branch, load))
+//    CONTEXT_STATE_KO_MSYNC        , // wait completion of all memory operation
+//    CONTEXT_STATE_KO_MSYNC_ISSUE  , // issue msync operation
       CONTEXT_STATE_KO_MSYNC_EXEC   , // wait completion of     msync  operation
-      CONTEXT_STATE_KO_PSYNC        , // wait completion of all        operation and after flush pipeline
+//    CONTEXT_STATE_KO_PSYNC        , // wait completion of all        operation and after flush pipeline
       CONTEXT_STATE_KO_PSYNC_FLUSH  , // wait completion of all 
       CONTEXT_STATE_KO_PSYNC_ADDR   , // wait completion of all 
-      CONTEXT_STATE_KO_CSYNC        , // wait completion of all        operation and after flush pipeline and flush ALL units (MMU, cache ...)
+//    CONTEXT_STATE_KO_CSYNC        , // wait completion of all        operation and after flush pipeline and flush ALL units (MMU, cache ...)
       CONTEXT_STATE_KO_CSYNC_FLUSH  ,
       CONTEXT_STATE_KO_CSYNC_ADDR   ,
-      CONTEXT_STATE_KO_SPR          , // wait completion of all        operation
-      CONTEXT_STATE_KO_SPR_ISSUE    , // issue spr's access
+//    CONTEXT_STATE_KO_SPR          , // wait completion of all        operation
+//    CONTEXT_STATE_KO_SPR_ISSUE    , // issue spr's access
       CONTEXT_STATE_KO_SPR_EXEC       // wait completion of all        operation (spr access)
     } context_state_t;
@@ -60,17 +60,17 @@
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_ADDR   : return "context_state_ko_excep_addr"  ; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_SPR    : return "context_state_ko_excep_spr"   ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS         : return "context_state_ko_miss"        ; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_ADDR    : return "context_state_ko_miss_addr"   ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC        : return "context_state_ko_msync"       ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE  : return "context_state_ko_msync_issue" ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_WAITEND : return "context_state_ko_miss_waitend"; break;
+//       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC        : return "context_state_ko_msync"       ; break;
+//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE  : return "context_state_ko_msync_issue" ; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_EXEC   : return "context_state_ko_msync_exec"  ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC        : return "context_state_ko_psync"       ; break;
+//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC        : return "context_state_ko_psync"       ; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_FLUSH  : return "context_state_ko_psync_flush" ; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_ADDR   : return "context_state_ko_psync_addr"  ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC        : return "context_state_ko_csync"       ; break;
+//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC        : return "context_state_ko_csync"       ; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_FLUSH  : return "context_state_ko_csync_flush" ; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_ADDR   : return "context_state_ko_csync_addr"  ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR          : return "context_state_ko_spr"         ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_ISSUE    : return "context_state_ko_spr_issue"   ; break;
+//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR          : return "context_state_ko_spr"         ; break;
+//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_ISSUE    : return "context_state_ko_spr_issue"   ; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_EXEC     : return "context_state_ko_spr_exec"    ; break;
       default    : return ""      ; break;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State.cpp	(revision 101)
@@ -82,9 +82,9 @@
 	  }
 
-	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
-	  {
-	    internal_DECOD_EVENT_ACK [i] = 1;
-	    PORT_WRITE(out_DECOD_EVENT_ACK [i], internal_DECOD_EVENT_ACK [i]);
-	  }
+// 	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
+// 	  {
+// 	    internal_DECOD_EVENT_ACK [i] = 1;
+// 	    PORT_WRITE(out_DECOD_EVENT_ACK [i], internal_DECOD_EVENT_ACK [i]);
+// 	  }
 
         internal_COMMIT_EVENT_ACK = 1;
@@ -112,4 +112,27 @@
 	dont_initialize ();
 	sensitive << (*(in_CLOCK)).neg(); // use internal register
+	
+# ifdef SYSTEMCASS_SPECIFIC
+	// List dependency information
+# endif    
+
+	log_printf(INFO,Context_State,FUNCTION,_("Method - genMealy_decod_event"));
+
+	SC_METHOD (genMealy_decod_event);
+	dont_initialize ();
+	sensitive << (*(in_CLOCK)).neg(); // use internal register
+        for (uint32_t i=0; i<_param->_nb_decod_unit; ++i)
+          {
+            sensitive << (*(in_DECOD_EVENT_VAL        [i])) // not necessary
+                      << (*(in_DECOD_EVENT_TYPE       [i]));
+            if (_param->_have_port_context_id)				        
+            sensitive << (*(in_DECOD_EVENT_CONTEXT_ID [i]));
+          }
+        for (uint32_t i=0; i<_param->_nb_context; ++i)
+          {
+            sensitive << (*(in_NB_INST_DECOD_ALL      [i]))
+                      << (*(in_NB_INST_COMMIT_ALL     [i]))
+                      << (*(in_NB_INST_COMMIT_MEM     [i]));
+          }
 	
 # ifdef SYSTEMCASS_SPECIFIC
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp	(revision 101)
@@ -105,7 +105,8 @@
 	context_state_t state = reg_STATE [i];
 
-	PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], ((state==CONTEXT_STATE_OK            ) or
-						  (state==CONTEXT_STATE_KO_MSYNC_ISSUE) or
-						  (state==CONTEXT_STATE_KO_SPR_ISSUE  )));
+// 	PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], ((state==CONTEXT_STATE_OK            ) or
+// 						  (state==CONTEXT_STATE_KO_MSYNC_ISSUE) or
+// 						  (state==CONTEXT_STATE_KO_SPR_ISSUE  )));
+	PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], (state==CONTEXT_STATE_OK));
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 101)
@@ -35,4 +35,145 @@
       {
         // -------------------------------------------------------------------
+        // -----[ next state ]------------------------------------------------
+        // -------------------------------------------------------------------
+        for (uint32_t i=0; i<_param->_nb_context; i++)
+          {
+//             uint32_t x = _param->_link_context_to_decod_unit    [i];
+
+            Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
+//          Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
+
+            context_state_t state = reg_STATE [i];
+
+            switch (state)
+              {
+              case CONTEXT_STATE_OK              :
+                {
+                  // nothing, wait an event
+                  break;
+                }
+              case CONTEXT_STATE_KO_EXCEP        :
+                {
+                  // Wait end of all instruction
+                  if (inst_all == 0)
+                    state = CONTEXT_STATE_KO_EXCEP_ADDR;
+                  break;
+                }
+              case CONTEXT_STATE_KO_EXCEP_ADDR   :
+                {
+                  // nothing, wait the update of internal register (pc)
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_WAITEND :
+                {
+                  // Wait end of all instruction
+                  if (inst_all == 0)
+                    
+//                  state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
+                    state = CONTEXT_STATE_KO_MISS_ADDR;
+                  break;
+                }
+              case CONTEXT_STATE_KO_EXCEP_SPR    :
+                {
+                  // nothing, wait the update of internal register (epcr, eear, sr, esr)
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_ADDR    :
+                {
+                  // nothing, wait the update of internal register (pc)
+                  break;
+                }
+//               case CONTEXT_STATE_KO_PSYNC        :
+//                 {
+//                   // Wait end of all instruction
+//                   if (inst_all == 0)
+//                     state = CONTEXT_STATE_KO_PSYNC_FLUSH;
+//                   break;
+//                 }
+              case CONTEXT_STATE_KO_PSYNC_FLUSH  :
+                {
+                  // nothing, wait end of flush (ifetch)
+                  if (inst_all == 0)
+//                  state = CONTEXT_STATE_KO_PSYNC_ADDR;
+                    state = CONTEXT_STATE_OK;
+                    
+                  break;
+                }
+              case CONTEXT_STATE_KO_PSYNC_ADDR   :
+                {
+                  // nothing, wait the pc write
+                  break;
+                }
+//               case CONTEXT_STATE_KO_CSYNC        :
+//                 {
+//                   // Wait end of all instruction
+//                   if (inst_all == 0)
+//                     state = CONTEXT_STATE_KO_CSYNC_FLUSH;
+//                   break;
+//                 }
+              case CONTEXT_STATE_KO_CSYNC_FLUSH  :
+                {
+                  // nothing, wait end of flush (all internal structure)
+                  if (inst_all == 0)
+                    state = CONTEXT_STATE_KO_CSYNC_ADDR;
+                  break;
+                }
+              case CONTEXT_STATE_KO_CSYNC_ADDR   :
+                {
+                  // nothing, wait the pc write
+                  break;
+                }
+//               case CONTEXT_STATE_KO_MSYNC        :
+//                 {
+//                   // Wait end of memory instruction
+//                   if (inst_mem == 0)
+//                     state = CONTEXT_STATE_KO_MSYNC_ISSUE;
+//                   break;
+//                 }
+//               case CONTEXT_STATE_KO_MSYNC_ISSUE  :
+//                 {
+//                   // Wait the msync issue
+//                   if (inst_mem != 0)
+//                     state = CONTEXT_STATE_KO_MSYNC_EXEC;
+//                   break;
+//                 }
+              case CONTEXT_STATE_KO_MSYNC_EXEC   :
+                {
+                  // Wait the end of msync
+                  if (inst_all == 0)
+                    state = CONTEXT_STATE_OK;
+                  break;
+                }
+//               case CONTEXT_STATE_KO_SPR          :
+//                 {
+//                   // Wait end of all instruction
+//                   if (inst_all == 0)
+//                     state = CONTEXT_STATE_KO_SPR_ISSUE;
+//                   break;
+//                 }
+//               case CONTEXT_STATE_KO_SPR_ISSUE    :
+//                 {
+//                   // Wait the spr_access issue
+//                   if (inst_all != 0)
+//                     state = CONTEXT_STATE_KO_SPR_EXEC;
+//                   break;
+//                 }
+              case CONTEXT_STATE_KO_SPR_EXEC     :
+                {
+                  // Wait the spr_access execution
+                  if (inst_all == 0)
+                    state = CONTEXT_STATE_OK;
+                  break;
+                }
+
+              default :
+                {
+                  throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str()));
+                }
+              }
+            reg_STATE [i] = state;
+          }
+
+        // -------------------------------------------------------------------
         // -----[ BRANCH_EVENT ]----------------------------------------------
         // -------------------------------------------------------------------
@@ -57,5 +198,5 @@
 
               // priority : miss > excep > spr/sync
-              uint8_t    priority0  = (state == CONTEXT_STATE_KO_MISS)?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
+              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
               uint8_t    priority1  = 2; // miss
 
@@ -71,5 +212,6 @@
                 {
                   Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
-                  reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS;
+//                reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_ADDR;
+                  reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
                   reg_EVENT_ADDRESS          [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC  [i])+1; // address delay slot
                   reg_EVENT_ADDRESS_EPCR     [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]);   // address_next
@@ -107,5 +249,5 @@
               
               // miss > excep > spr/sync
-              uint8_t    priority0  = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
               uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?1:0;
 
@@ -120,4 +262,6 @@
               if (is_valid)
                 {
+                  log_printf(TRACE,Context_State,FUNCTION,"    * is_valid");
+
                   // decod : 
                   // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys)
@@ -130,4 +274,6 @@
                     case EVENT_TYPE_EXCEPTION          : 
                       {
+                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_EXCEPTION");
+
                         state_next = CONTEXT_STATE_KO_EXCEP; 
 
@@ -136,32 +282,44 @@
                     case EVENT_TYPE_SPR_ACCESS         : 
                       {
-                        state_next = CONTEXT_STATE_KO_SPR  ; 
+                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_SPR_ACCESS");
+
+//                      state_next = CONTEXT_STATE_KO_SPR  ; 
+                        state_next = CONTEXT_STATE_KO_SPR_EXEC; 
                         address++; // take next address
-                        if (is_delay_slot)
-                          throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
+//                         if (is_delay_slot)
+//                           throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
                         break;
                       }
                     case EVENT_TYPE_MSYNC              : 
                       {
-                        state_next = CONTEXT_STATE_KO_MSYNC;
+                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_MSYNC");
+
+//                      state_next = CONTEXT_STATE_KO_MSYNC;
+                        state_next = CONTEXT_STATE_KO_MSYNC_EXEC;
                         address++;  // take next address
-                        if (is_delay_slot)
-                          throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
+//                         if (is_delay_slot)
+//                           throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n");
                         break;
                       }
                     case EVENT_TYPE_PSYNC              :
                       {
-                        state_next = CONTEXT_STATE_KO_PSYNC;
+                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_PSYNC");
+
+//                      state_next = CONTEXT_STATE_KO_PSYNC;
+                        state_next = CONTEXT_STATE_KO_PSYNC_FLUSH;
                         address++;  // take next address
                         if (is_delay_slot)
-                          throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
+                          throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n");
                         break;
                       }
                     case EVENT_TYPE_CSYNC              :
                       {
-                        state_next = CONTEXT_STATE_KO_CSYNC;
+                        log_printf(TRACE,Context_State,FUNCTION,"    * EVENT_TYPE_CSYNC");
+
+//                      state_next = CONTEXT_STATE_KO_CSYNC;
+                        state_next = CONTEXT_STATE_KO_CSYNC_FLUSH;
                         address++;  // take next address
                         if (is_delay_slot)
-                          throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
+                          throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n");
                         break;
                       }               
@@ -210,5 +368,5 @@
             
             // miss > excep > spr/sync
-            uint8_t    priority0  = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+            uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
             uint8_t    priority1  = 1; // exception
 
@@ -277,5 +435,5 @@
                   
 //                   // miss > excep > spr/sync
-//                   uint8_t    priority0  = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+//                   uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
 //                   uint8_t    priority1  = 2; // miss
                   
@@ -323,4 +481,8 @@
                   }
                 case CONTEXT_STATE_KO_MISS_ADDR  :
+//                   {
+//                     reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
+//                     break;
+//                   }
                 case CONTEXT_STATE_KO_PSYNC_ADDR :
                 case CONTEXT_STATE_KO_CSYNC_ADDR :
@@ -357,139 +519,4 @@
               reg_STATE [i] = CONTEXT_STATE_OK;
             }
-
-        // -------------------------------------------------------------------
-        // -----[ next state ]------------------------------------------------
-        // -------------------------------------------------------------------
-        for (uint32_t i=0; i<_param->_nb_context; i++)
-          {
-//             uint32_t x = _param->_link_context_to_decod_unit    [i];
-
-            Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
-            Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
-
-            context_state_t state = reg_STATE [i];
-
-            switch (state)
-              {
-              case CONTEXT_STATE_OK              :
-                {
-                  // nothing, wait an event
-                  break;
-                }
-              case CONTEXT_STATE_KO_EXCEP        :
-                {
-                  // Wait end of all instruction
-                  if (inst_all == 0)
-                    state = CONTEXT_STATE_KO_EXCEP_ADDR;
-                  break;
-                }
-              case CONTEXT_STATE_KO_MISS         :
-                {
-                  // Wait end of all instruction
-                  if (inst_all == 0)
-                    state = CONTEXT_STATE_KO_MISS_ADDR;
-                  break;
-                }
-              case CONTEXT_STATE_KO_EXCEP_ADDR   :
-                {
-                  // nothing, wait the update of internal register (pc)
-                  break;
-                }
-              case CONTEXT_STATE_KO_EXCEP_SPR    :
-                {
-                  // nothing, wait the update of internal register (epcr, eear, sr, esr)
-                  break;
-                }
-              case CONTEXT_STATE_KO_MISS_ADDR    :
-                {
-                  // nothing, wait the update of internal register (pc)
-                  break;
-                }
-              case CONTEXT_STATE_KO_PSYNC        :
-                {
-                  // Wait end of all instruction
-                  if (inst_all == 0)
-//                  state = CONTEXT_STATE_KO_PSYNC_FLUSH;
-                    state = CONTEXT_STATE_KO_PSYNC_ADDR ;
-                  break;
-                }
-//            case CONTEXT_STATE_KO_PSYNC_FLUSH  :
-//              {
-//                // nothing, wait end of flush (ifetch)
-//                break;
-//              }
-              case CONTEXT_STATE_KO_PSYNC_ADDR   :
-                {
-                  // nothing, wait the pc write
-                  break;
-                }
-              case CONTEXT_STATE_KO_CSYNC        :
-                {
-                  // Wait end of all instruction
-                  if (inst_all == 0)
-                    state = CONTEXT_STATE_KO_CSYNC_ADDR ;
-//                  state = CONTEXT_STATE_KO_CSYNC_FLUSH;
-                  break;
-                }
-//            case CONTEXT_STATE_KO_CSYNC_FLUSH  :
-//              {
-//                // nothing, wait end of flush (all internal structure)
-//                break;
-//              }
-              case CONTEXT_STATE_KO_CSYNC_ADDR   :
-                {
-                  // nothing, wait the pc write
-                  break;
-                }
-              case CONTEXT_STATE_KO_MSYNC        :
-                {
-                  // Wait end of memory instruction
-                  if (inst_mem == 0)
-                    state = CONTEXT_STATE_KO_MSYNC_ISSUE;
-                  break;
-                }
-              case CONTEXT_STATE_KO_MSYNC_ISSUE  :
-                {
-                  // Wait the msync issue
-                  if (inst_mem != 0)
-                    state = CONTEXT_STATE_KO_MSYNC_EXEC;
-                  break;
-                }
-              case CONTEXT_STATE_KO_MSYNC_EXEC   :
-                {
-                  // Wait the end of msync
-                  if (inst_mem == 0)
-                    state = CONTEXT_STATE_OK;
-                  break;
-                }
-              case CONTEXT_STATE_KO_SPR          :
-                {
-                  // Wait end of all instruction
-                  if (inst_all == 0)
-                    state = CONTEXT_STATE_KO_SPR_ISSUE;
-                  break;
-                }
-              case CONTEXT_STATE_KO_SPR_ISSUE    :
-                {
-                  // Wait the spr_access issue
-                  if (inst_all != 0)
-                    state = CONTEXT_STATE_KO_SPR_EXEC;
-                  break;
-                }
-              case CONTEXT_STATE_KO_SPR_EXEC     :
-                {
-                  // Wait the spr_access execution
-                  if (inst_all == 0)
-                    state = CONTEXT_STATE_OK;
-                  break;
-                }
-
-              default :
-                {
-                  throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str()));
-                }
-              }
-            reg_STATE [i] = state;
-          }
 
         for (uint32_t i=0; i<_param->_nb_context; ++i)
