Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp	(revision 101)
@@ -67,4 +67,5 @@
   ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE         ," in_PREDICT_INSTRUCTION_ENABLE         ",Tcontrol_t        ,_param->_nb_instruction);
   ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR            ," in_PREDICT_INST_IFETCH_PTR            ",Tinst_ifetch_ptr_t);
+//ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_IS_CURRENT          ," in_PREDICT_BRANCH_IS_CURRENT          ",Tcontrol_t        );
   ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE               ," in_PREDICT_BRANCH_STATE               ",Tbranch_state_t   );
   ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
@@ -104,4 +105,5 @@
   if (_param->_have_port_inst_ifetch_ptr)
   INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR            );
+//INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_IS_CURRENT          );
   INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE               );
   if (_param->_have_port_depth)
@@ -129,7 +131,7 @@
   srand(seed);
 
-  const  int32_t percent_transaction_address = 75;
-  const  int32_t percent_transaction_predict = 75;
-  const  int32_t percent_transaction_event   =  5;
+  const  int32_t percent_transaction_address = 100;
+  const  int32_t percent_transaction_predict = 100;
+  const  int32_t percent_transaction_event   =  0;
 
   SC_START(0);
@@ -155,22 +157,26 @@
   uint32_t        nb_packet = 1;
 
+  Tcontrol_t      a_val   = false;
   Tcontrol_t      c_val   = false;
-  Tcontrol_t      n_val   = false;
+  Tcontrol_t      n_val   = true ;
   Tcontrol_t      nn_val  = false;
 
+  Tgeneral_data_t a_addr  = 0x100>>2;
   Tgeneral_data_t c_addr  = 0x100>>2;
   Tgeneral_data_t n_addr  = 0x100>>2;
   Tgeneral_data_t nn_addr = 0x100>>2;
 
+  Tcontrol_t      a_enable [_param->_nb_instruction];
   Tcontrol_t      c_enable [_param->_nb_instruction];
   Tcontrol_t      n_enable [_param->_nb_instruction];
 
+  Tcontrol_t      a_is_ds_take   = 0;
   Tcontrol_t      c_is_ds_take   = 0;
   Tcontrol_t      n_is_ds_take   = 0;		
   Tcontrol_t      nn_is_ds_take  = 0;
 
-  c_enable [0] = 1;
+  n_enable [0] = 1;
   for (uint32_t i=1; i<_param->_nb_instruction; i++)
-    c_enable [i] = 0;
+    n_enable [i] = 0;
 
   LABEL("Send Reset");
@@ -216,4 +222,5 @@
 	in_PREDICT_PC_NEXT_IS_DS_TAKE         ->write(take);
 	in_PREDICT_INST_IFETCH_PTR            ->write(0);
+// 	in_PREDICT_BRANCH_IS_CURRENT          ->write(0);
 	in_PREDICT_BRANCH_STATE               ->write(0);
 	in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0);
@@ -251,4 +258,6 @@
 	  for (uint32_t i=0; i<_param->_nb_instruction; i++)
 	  n_enable [i]  = in_PREDICT_INSTRUCTION_ENABLE [i]->read();
+
+	  LABEL("  * nn_addr          : %.8x",nn_addr);
 	}
  
@@ -256,9 +265,9 @@
 	{
 	  LABEL("ADDRESS    : Transaction accepted");
-	  LABEL("  * address wait     : %.8x",c_addr);
-
-	  TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS        ->read(),c_addr);
+	  LABEL("  * address wait     : %.8x",a_addr);
+
+	  TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS        ->read(),a_addr);
 	  for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	  TEST(Tcontrol_t        ,out_ADDRESS_INSTRUCTION_ENABLE     [i] ->read(),c_enable[i]);
+	  TEST(Tcontrol_t        ,out_ADDRESS_INSTRUCTION_ENABLE     [i] ->read(),a_enable[i]);
 	  if (_param->_have_port_inst_ifetch_ptr)
 	  TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR            ->read(),0);
@@ -267,27 +276,70 @@
 	  TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0);
 
-	  c_val = 0;
+	  a_val = 0;
 	  nb_packet ++;
 	}
 
+      {
+	string str_a_enable = "";
+	string str_c_enable = "";
+	string str_n_enable = "";
+
+	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	  {
+	    str_a_enable += " " + toString(a_enable [i]);
+	    str_c_enable += " " + toString(c_enable [i]);
+	    str_n_enable += " " + toString(n_enable [i]);
+	  }
+
+	LABEL("----[ Before ]---------------------");
+	LABEL("  * nb_packet : %d",nb_packet);
+	LABEL("  * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str());
+	LABEL("  * pc   : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str());
+	LABEL("  * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str());
+	LABEL("  * pc+8 : %d %d %.8x"   ,nn_val,nn_is_ds_take,nn_addr);
+	LABEL("-----------------------------------");
+      }
+
+      if (not a_val)
+	{
+          if (c_val and n_val and nn_val)
+            {
+	      a_val        = 1;
+              c_val        = 0;
+	      a_addr       = c_addr;
+	      a_is_ds_take = c_is_ds_take;
+
+	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
+		a_enable [i] = c_enable [i];
+            }
+        }
 
       if (not c_val)
-	{
-	  if (n_val and nn_val)
-	    {
-	      c_val        = 1;
-	      c_addr       = n_addr;
-	      c_is_ds_take = n_is_ds_take;
-
-	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
-		c_enable [i] = n_enable [i];
-	      
-	      n_val        = 1;
-	      n_addr       = nn_addr;
-	      n_is_ds_take = nn_is_ds_take;
-	      
-	      nn_val       = 0;
-	    }
-	}
+        {
+          c_val        = n_val;
+          if (n_val)
+            {
+              c_addr       = n_addr;
+              c_is_ds_take = n_is_ds_take;
+              
+              for (uint32_t i=0; i<_param->_nb_instruction; i++)
+                c_enable [i] = n_enable [i];
+            }
+          n_val        = 0;
+        }
+
+      if (not n_val)
+        {
+          n_val        = nn_val;
+          if (nn_val)
+            {
+              n_addr       = nn_addr;
+              n_is_ds_take = nn_is_ds_take;
+              
+// 	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
+// 		n_enable [i] = nn_enable [i];
+            }
+          nn_val       = 0;
+        }
 
       if (in_EVENT_VAL->read() and out_EVENT_ACK->read())
@@ -295,4 +347,5 @@
 	  LABEL("EVENT      : Transaction accepted");
 
+	  a_val        = false;
 	  c_val        = false;
 	  n_val        = true;
@@ -312,4 +365,5 @@
       
       {
+	string str_a_enable = "";
 	string str_c_enable = "";
 	string str_n_enable = "";
@@ -317,20 +371,15 @@
 	for (uint32_t i=0; i<_param->_nb_instruction; i++)
 	  {
+	    str_a_enable += " " + toString(a_enable [i]);
 	    str_c_enable += " " + toString(c_enable [i]);
 	    str_n_enable += " " + toString(n_enable [i]);
 	  }
 
-	LABEL("-----------------------------------");
+	LABEL("----[ After ]----------------------");
 	LABEL("  * nb_packet : %d",nb_packet);
-	LABEL("  * pc   : %d %d %.8x %s",c_val  ,c_is_ds_take , c_addr ,str_c_enable.c_str());
-	if (nn_val)
-	  {
-	LABEL("  * pc+4 : %d %d %.8x %s",n_val  ,n_is_ds_take , n_addr ,str_n_enable.c_str());
-	  }
-	else
-	  {
-	LABEL("  * pc+4 : %d %d %.8x"   ,n_val  ,n_is_ds_take , n_addr );
-	  }
-	LABEL("  * pc+8 : %d %d %.8x"   ,nn_val ,nn_is_ds_take, nn_addr);
+	LABEL("  * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str());
+	LABEL("  * pc   : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str());
+	LABEL("  * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str());
+	LABEL("  * pc+8 : %d %d %.8x"   ,nn_val,nn_is_ds_take,nn_addr);
 	LABEL("-----------------------------------");
       }
@@ -368,4 +417,5 @@
   delete []  in_PREDICT_INSTRUCTION_ENABLE         ;
   delete     in_PREDICT_INST_IFETCH_PTR            ;
+//delete     in_PREDICT_BRANCH_IS_CURRENT          ;
   delete     in_PREDICT_BRANCH_STATE               ;
   delete     in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
