Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp	(revision 101)
@@ -28,8 +28,18 @@
       {
 	// nothing is valid
+	reg_PC_ACCESS_VAL    = 0;
+
 	reg_PC_CURRENT_VAL   = 0;
 
         reg_PC_NEXT_VAL      = 1;
         reg_PC_NEXT          = 0x100>>2;
+        reg_PC_NEXT_IS_DS_TAKE                  = 0;
+        reg_PC_NEXT_INSTRUCTION_ENABLE [0]      = 1;
+        for (uint32_t i=1; i<_param->_nb_instruction; i++)
+        reg_PC_NEXT_INSTRUCTION_ENABLE [i]      = 0;
+        reg_PC_NEXT_INST_IFETCH_PTR             = 0;
+        reg_PC_NEXT_BRANCH_STATE                = 0;
+        reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0;
+
 
 	reg_PC_NEXT_NEXT_VAL = 0;
@@ -42,11 +52,24 @@
 	if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL)
 	  {
+            bool branch_is_current = reg_PC_NEXT_IS_DS_TAKE;
+            if (branch_is_current)
+              {
+                if (_param->_have_port_inst_ifetch_ptr)
+                reg_PC_CURRENT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
+                reg_PC_CURRENT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
+                if (_param->_have_port_depth)
+                reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
+              }
+            else
+              {
+                if (_param->_have_port_inst_ifetch_ptr)
+                reg_PC_NEXT_INST_IFETCH_PTR                = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
+                reg_PC_NEXT_BRANCH_STATE                   = PORT_READ(in_PREDICT_BRANCH_STATE               );
+                if (_param->_have_port_depth)
+                reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID    = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
+              }
+
 	    for (uint32_t i=0; i<_param->_nb_instruction; i++)
 	    reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);
-	    if (_param->_have_port_inst_ifetch_ptr)
-	    reg_PC_NEXT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
-	    reg_PC_NEXT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
-	    if (_param->_have_port_depth)
-	    reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
 	    
 	    reg_PC_NEXT_NEXT_VAL                    = 1; // address is valid
@@ -64,50 +87,73 @@
 	// =========================================
 	// transaction with icache
-	if ( (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) or not reg_PC_CURRENT_VAL)
-	  {
+	if (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK))
+          {
+            reg_PC_ACCESS_VAL = 0;
 #ifdef STATISTICS
             if (usage_is_set(_usage,USE_STATISTICS))
-              if (reg_PC_CURRENT_VAL)
-                {
+              {
                   (*_stat_nb_transaction_address) ++;
                   
                   for (uint32_t i=0; i<_param->_nb_instruction; i++)
-                    if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true)
+                    if (reg_PC_ACCESS_INSTRUCTION_ENABLE [i] == true)
                       (*_stat_sum_packet_size) ++;
                 }
 #endif
-
-
-	    Tcontrol_t pc_next_val = reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL;
-
-	    // next pc became current pc
-	    reg_PC_CURRENT_VAL                             = pc_next_val;
-
-	    // if pc_next is not valid : don't erase PC and PC_IS_DS_TAKE : this register is send a the predict (to compute pc_next)
-	    if (pc_next_val)
-	      {
-		reg_PC_CURRENT                             = reg_PC_NEXT                            ;
-		reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
-		reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
-		reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
-		reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
-
-		for (uint32_t i=0; i<_param->_nb_instruction; i++)
-		reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
-	    
-		reg_PC_NEXT_VAL                            = reg_PC_NEXT_NEXT_VAL       ;
-		// if pc_next_next is not valid : don't erase PC_NEXT and PC_NEXT_IS_DS_TAKE : this register is send a the predict (to compute pc_next)
-		if (reg_PC_NEXT_NEXT_VAL)
-		  {
-		    reg_PC_NEXT                            = reg_PC_NEXT_NEXT           ;
-		    reg_PC_NEXT_IS_DS_TAKE                 = reg_PC_NEXT_NEXT_IS_DS_TAKE;
-		  }
-		
-		// invalid next next pc
-		reg_PC_NEXT_NEXT_VAL                       = 0;
-	      }
-
-	  }
-	
+          }
+        
+        // Shift register
+
+        if (not reg_PC_ACCESS_VAL and reg_PC_CURRENT_VAL and reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL)
+          {
+            reg_PC_ACCESS_VAL  = 1; // new request
+            reg_PC_CURRENT_VAL = 0; // invalid current
+            
+            reg_PC_ACCESS                             = reg_PC_CURRENT                            ;
+            reg_PC_ACCESS_IS_DS_TAKE                  = reg_PC_CURRENT_IS_DS_TAKE                 ;
+            reg_PC_ACCESS_INST_IFETCH_PTR             = reg_PC_CURRENT_INST_IFETCH_PTR            ;
+            reg_PC_ACCESS_BRANCH_STATE                = reg_PC_CURRENT_BRANCH_STATE               ;
+            reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID = reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID;
+            
+            for (uint32_t i=0; i<_param->_nb_instruction; i++)
+              reg_PC_ACCESS_INSTRUCTION_ENABLE [i] = reg_PC_CURRENT_INSTRUCTION_ENABLE [i];
+          }
+        
+        if (not reg_PC_CURRENT_VAL)
+          {
+            bool val = reg_PC_NEXT_VAL;
+            reg_PC_CURRENT_VAL = val; // new PC_CURRENT if PC_NEXT is valid
+            reg_PC_NEXT_VAL    = 0;   // invalid next
+
+            if (val)
+              {
+                reg_PC_CURRENT                             = reg_PC_NEXT                            ;
+                reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
+                reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
+                reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
+                reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
+                
+                for (uint32_t i=0; i<_param->_nb_instruction; i++)
+                  reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
+              }
+          }
+
+        if (not reg_PC_NEXT_VAL)
+          {
+            bool val = reg_PC_NEXT_NEXT_VAL;
+            reg_PC_NEXT_VAL      = val; // new PC_NEXT if PC_NEXT_NEXT is valid
+            reg_PC_NEXT_NEXT_VAL = 0;   // invalid next_next
+            
+            if (val)
+              {
+                reg_PC_NEXT                             = reg_PC_NEXT_NEXT                            ;
+                reg_PC_NEXT_IS_DS_TAKE                  = reg_PC_NEXT_NEXT_IS_DS_TAKE                 ;
+//              reg_PC_NEXT_INST_IFETCH_PTR             = reg_PC_NEXT_NEXT_INST_IFETCH_PTR            ;
+//              reg_PC_NEXT_BRANCH_STATE                = reg_PC_NEXT_NEXT_BRANCH_STATE               ;
+//              reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID;
+             
+//              for (uint32_t i=0; i<_param->_nb_instruction; i++)
+//                reg_PC_NEXT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE [i];
+              }
+          }
 
 	// =========================================
@@ -121,4 +167,6 @@
 	    log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT     : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS_NEXT    ),PORT_READ(in_EVENT_ADDRESS_NEXT    )<<2);
 	    log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT_VAL : %d"  ,PORT_READ(in_EVENT_ADDRESS_NEXT_VAL));
+
+	    reg_PC_ACCESS_VAL                       = 0;
 	    reg_PC_CURRENT_VAL                      = 0;
 	    reg_PC_NEXT_VAL                         = 1;
@@ -157,9 +205,58 @@
       }
 
-#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE)
+#if defined(DEBUG) and DEBUG_Address_management and (DEBUG >= DEBUG_TRACE)
     log_printf(TRACE,Address_management,FUNCTION,"  * Dump PC");
-    log_printf(TRACE,Address_management,FUNCTION,"    * Current   : %d %d 0x%.8x (%.8x)",reg_PC_CURRENT_VAL  , reg_PC_CURRENT_IS_DS_TAKE  , reg_PC_CURRENT  , reg_PC_CURRENT  <<2);
-    log_printf(TRACE,Address_management,FUNCTION,"    * Next      : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_VAL     , reg_PC_NEXT_IS_DS_TAKE     , reg_PC_NEXT     , reg_PC_NEXT     <<2);    
-    log_printf(TRACE,Address_management,FUNCTION,"    * Next_Next : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT, reg_PC_NEXT_NEXT<<2);    
+    {
+      std::string instruction_enable;
+      for (uint32_t i=0; i<_param->_nb_instruction; ++i)
+        instruction_enable += toString(reg_PC_ACCESS_INSTRUCTION_ENABLE [i])+ " ";
+
+      log_printf(TRACE,Address_management,FUNCTION,"    * Access    : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s",
+                 reg_PC_ACCESS_VAL,
+                 reg_PC_ACCESS_IS_DS_TAKE,
+                 reg_PC_ACCESS,
+                 reg_PC_ACCESS<<2,
+                 reg_PC_ACCESS_BRANCH_STATE,
+                 reg_PC_ACCESS_INST_IFETCH_PTR,
+                 reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID,
+                 instruction_enable.c_str()
+                 );
+    }
+    {
+      std::string instruction_enable;
+      for (uint32_t i=0; i<_param->_nb_instruction; ++i)
+        instruction_enable += toString(reg_PC_CURRENT_INSTRUCTION_ENABLE [i])+ " ";
+
+      log_printf(TRACE,Address_management,FUNCTION,"    * Current   : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s",
+                 reg_PC_CURRENT_VAL,
+                 reg_PC_CURRENT_IS_DS_TAKE,
+                 reg_PC_CURRENT,
+                 reg_PC_CURRENT<<2,
+                 reg_PC_CURRENT_BRANCH_STATE,
+                 reg_PC_CURRENT_INST_IFETCH_PTR,
+                 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID,
+                 instruction_enable.c_str()
+                 );
+    }
+    {
+      std::string instruction_enable;
+      for (uint32_t i=0; i<_param->_nb_instruction; ++i)
+        instruction_enable += toString(reg_PC_NEXT_INSTRUCTION_ENABLE [i])+ " ";
+
+      log_printf(TRACE,Address_management,FUNCTION,"    * Next      : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s",
+                 reg_PC_NEXT_VAL,
+                 reg_PC_NEXT_IS_DS_TAKE,
+                 reg_PC_NEXT,
+                 reg_PC_NEXT<<2,
+                 reg_PC_NEXT_BRANCH_STATE,
+                 reg_PC_NEXT_INST_IFETCH_PTR,
+                 reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID,
+                 instruction_enable.c_str());
+    }
+    log_printf(TRACE,Address_management,FUNCTION,"    * Next_Next : %d %d 0x%.8x (%.8x)",
+               reg_PC_NEXT_NEXT_VAL,
+               reg_PC_NEXT_NEXT_IS_DS_TAKE,
+               reg_PC_NEXT_NEXT,
+               reg_PC_NEXT_NEXT<<2);    
 #endif 
 
