Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp	(revision 101)
@@ -67,4 +67,5 @@
   ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE         ," in_PREDICT_INSTRUCTION_ENABLE         ",Tcontrol_t        ,_param->_nb_instruction);
   ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR            ," in_PREDICT_INST_IFETCH_PTR            ",Tinst_ifetch_ptr_t);
+//ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_IS_CURRENT          ," in_PREDICT_BRANCH_IS_CURRENT          ",Tcontrol_t        );
   ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE               ," in_PREDICT_BRANCH_STATE               ",Tbranch_state_t   );
   ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
@@ -104,4 +105,5 @@
   if (_param->_have_port_inst_ifetch_ptr)
   INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR            );
+//INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_IS_CURRENT          );
   INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE               );
   if (_param->_have_port_depth)
@@ -129,7 +131,7 @@
   srand(seed);
 
-  const  int32_t percent_transaction_address = 75;
-  const  int32_t percent_transaction_predict = 75;
-  const  int32_t percent_transaction_event   =  5;
+  const  int32_t percent_transaction_address = 100;
+  const  int32_t percent_transaction_predict = 100;
+  const  int32_t percent_transaction_event   =  0;
 
   SC_START(0);
@@ -155,22 +157,26 @@
   uint32_t        nb_packet = 1;
 
+  Tcontrol_t      a_val   = false;
   Tcontrol_t      c_val   = false;
-  Tcontrol_t      n_val   = false;
+  Tcontrol_t      n_val   = true ;
   Tcontrol_t      nn_val  = false;
 
+  Tgeneral_data_t a_addr  = 0x100>>2;
   Tgeneral_data_t c_addr  = 0x100>>2;
   Tgeneral_data_t n_addr  = 0x100>>2;
   Tgeneral_data_t nn_addr = 0x100>>2;
 
+  Tcontrol_t      a_enable [_param->_nb_instruction];
   Tcontrol_t      c_enable [_param->_nb_instruction];
   Tcontrol_t      n_enable [_param->_nb_instruction];
 
+  Tcontrol_t      a_is_ds_take   = 0;
   Tcontrol_t      c_is_ds_take   = 0;
   Tcontrol_t      n_is_ds_take   = 0;		
   Tcontrol_t      nn_is_ds_take  = 0;
 
-  c_enable [0] = 1;
+  n_enable [0] = 1;
   for (uint32_t i=1; i<_param->_nb_instruction; i++)
-    c_enable [i] = 0;
+    n_enable [i] = 0;
 
   LABEL("Send Reset");
@@ -216,4 +222,5 @@
 	in_PREDICT_PC_NEXT_IS_DS_TAKE         ->write(take);
 	in_PREDICT_INST_IFETCH_PTR            ->write(0);
+// 	in_PREDICT_BRANCH_IS_CURRENT          ->write(0);
 	in_PREDICT_BRANCH_STATE               ->write(0);
 	in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0);
@@ -251,4 +258,6 @@
 	  for (uint32_t i=0; i<_param->_nb_instruction; i++)
 	  n_enable [i]  = in_PREDICT_INSTRUCTION_ENABLE [i]->read();
+
+	  LABEL("  * nn_addr          : %.8x",nn_addr);
 	}
  
@@ -256,9 +265,9 @@
 	{
 	  LABEL("ADDRESS    : Transaction accepted");
-	  LABEL("  * address wait     : %.8x",c_addr);
-
-	  TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS        ->read(),c_addr);
+	  LABEL("  * address wait     : %.8x",a_addr);
+
+	  TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS        ->read(),a_addr);
 	  for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	  TEST(Tcontrol_t        ,out_ADDRESS_INSTRUCTION_ENABLE     [i] ->read(),c_enable[i]);
+	  TEST(Tcontrol_t        ,out_ADDRESS_INSTRUCTION_ENABLE     [i] ->read(),a_enable[i]);
 	  if (_param->_have_port_inst_ifetch_ptr)
 	  TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR            ->read(),0);
@@ -267,27 +276,70 @@
 	  TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0);
 
-	  c_val = 0;
+	  a_val = 0;
 	  nb_packet ++;
 	}
 
+      {
+	string str_a_enable = "";
+	string str_c_enable = "";
+	string str_n_enable = "";
+
+	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	  {
+	    str_a_enable += " " + toString(a_enable [i]);
+	    str_c_enable += " " + toString(c_enable [i]);
+	    str_n_enable += " " + toString(n_enable [i]);
+	  }
+
+	LABEL("----[ Before ]---------------------");
+	LABEL("  * nb_packet : %d",nb_packet);
+	LABEL("  * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str());
+	LABEL("  * pc   : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str());
+	LABEL("  * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str());
+	LABEL("  * pc+8 : %d %d %.8x"   ,nn_val,nn_is_ds_take,nn_addr);
+	LABEL("-----------------------------------");
+      }
+
+      if (not a_val)
+	{
+          if (c_val and n_val and nn_val)
+            {
+	      a_val        = 1;
+              c_val        = 0;
+	      a_addr       = c_addr;
+	      a_is_ds_take = c_is_ds_take;
+
+	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
+		a_enable [i] = c_enable [i];
+            }
+        }
 
       if (not c_val)
-	{
-	  if (n_val and nn_val)
-	    {
-	      c_val        = 1;
-	      c_addr       = n_addr;
-	      c_is_ds_take = n_is_ds_take;
-
-	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
-		c_enable [i] = n_enable [i];
-	      
-	      n_val        = 1;
-	      n_addr       = nn_addr;
-	      n_is_ds_take = nn_is_ds_take;
-	      
-	      nn_val       = 0;
-	    }
-	}
+        {
+          c_val        = n_val;
+          if (n_val)
+            {
+              c_addr       = n_addr;
+              c_is_ds_take = n_is_ds_take;
+              
+              for (uint32_t i=0; i<_param->_nb_instruction; i++)
+                c_enable [i] = n_enable [i];
+            }
+          n_val        = 0;
+        }
+
+      if (not n_val)
+        {
+          n_val        = nn_val;
+          if (nn_val)
+            {
+              n_addr       = nn_addr;
+              n_is_ds_take = nn_is_ds_take;
+              
+// 	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
+// 		n_enable [i] = nn_enable [i];
+            }
+          nn_val       = 0;
+        }
 
       if (in_EVENT_VAL->read() and out_EVENT_ACK->read())
@@ -295,4 +347,5 @@
 	  LABEL("EVENT      : Transaction accepted");
 
+	  a_val        = false;
 	  c_val        = false;
 	  n_val        = true;
@@ -312,4 +365,5 @@
       
       {
+	string str_a_enable = "";
 	string str_c_enable = "";
 	string str_n_enable = "";
@@ -317,20 +371,15 @@
 	for (uint32_t i=0; i<_param->_nb_instruction; i++)
 	  {
+	    str_a_enable += " " + toString(a_enable [i]);
 	    str_c_enable += " " + toString(c_enable [i]);
 	    str_n_enable += " " + toString(n_enable [i]);
 	  }
 
-	LABEL("-----------------------------------");
+	LABEL("----[ After ]----------------------");
 	LABEL("  * nb_packet : %d",nb_packet);
-	LABEL("  * pc   : %d %d %.8x %s",c_val  ,c_is_ds_take , c_addr ,str_c_enable.c_str());
-	if (nn_val)
-	  {
-	LABEL("  * pc+4 : %d %d %.8x %s",n_val  ,n_is_ds_take , n_addr ,str_n_enable.c_str());
-	  }
-	else
-	  {
-	LABEL("  * pc+4 : %d %d %.8x"   ,n_val  ,n_is_ds_take , n_addr );
-	  }
-	LABEL("  * pc+8 : %d %d %.8x"   ,nn_val ,nn_is_ds_take, nn_addr);
+	LABEL("  * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str());
+	LABEL("  * pc   : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str());
+	LABEL("  * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str());
+	LABEL("  * pc+8 : %d %d %.8x"   ,nn_val,nn_is_ds_take,nn_addr);
 	LABEL("-----------------------------------");
       }
@@ -368,4 +417,5 @@
   delete []  in_PREDICT_INSTRUCTION_ENABLE         ;
   delete     in_PREDICT_INST_IFETCH_PTR            ;
+//delete     in_PREDICT_BRANCH_IS_CURRENT          ;
   delete     in_PREDICT_BRANCH_STATE               ;
   delete     in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h	(revision 101)
@@ -83,7 +83,8 @@
   public    : SC_IN (Tcontrol_t         )   *  in_PREDICT_PC_NEXT_IS_DS_TAKE          ;
   public    : SC_IN (Tcontrol_t         )  **  in_PREDICT_INSTRUCTION_ENABLE          ; //[nb_instruction]
-  public    : SC_IN (Tinst_ifetch_ptr_t )   *  in_PREDICT_INST_IFETCH_PTR             ;
+//public    : SC_IN (Tcontrol_t         )   *  in_PREDICT_BRANCH_IS_CURRENT           ;
   public    : SC_IN (Tbranch_state_t    )   *  in_PREDICT_BRANCH_STATE                ;
   public    : SC_IN (Tprediction_ptr_t  )   *  in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ;
+  public    : SC_IN (Tinst_ifetch_ptr_t )   *  in_PREDICT_INST_IFETCH_PTR             ;
 
     // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -98,4 +99,12 @@
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+  private   : Tcontrol_t                      reg_PC_ACCESS_VAL                           ;
+  private   : Tgeneral_address_t              reg_PC_ACCESS                               ;
+  private   : Tcontrol_t                      reg_PC_ACCESS_IS_DS_TAKE                    ;
+  private   : Tcontrol_t                    * reg_PC_ACCESS_INSTRUCTION_ENABLE            ; //[nb_instruction]
+  private   : Tinst_ifetch_ptr_t              reg_PC_ACCESS_INST_IFETCH_PTR               ;
+  private   : Tbranch_state_t                 reg_PC_ACCESS_BRANCH_STATE                  ;
+  private   : Tprediction_ptr_t               reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID   ;
+
   private   : Tcontrol_t                      reg_PC_CURRENT_VAL                          ;
   private   : Tgeneral_address_t              reg_PC_CURRENT                              ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp	(revision 101)
@@ -85,7 +85,8 @@
       ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT                    ,"pc_next"                    ,Tgeneral_address_t,_param->_size_instruction_address);
       ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT_IS_DS_TAKE         ,"pc_next_is_ds_take"         ,Tcontrol_t        ,1);
-      ALLOC_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
+//    ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_IS_CURRENT          ,"branch_is_current"          ,Tcontrol_t        ,1);
       ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
       ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
+      ALLOC_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
     }
     {
@@ -110,6 +111,7 @@
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
-        reg_PC_CURRENT_INSTRUCTION_ENABLE = new Tcontrol_t [_param->_nb_instruction];
-        reg_PC_NEXT_INSTRUCTION_ENABLE    = new Tcontrol_t [_param->_nb_instruction];
+        ALLOC1(reg_PC_ACCESS_INSTRUCTION_ENABLE ,Tcontrol_t,_param->_nb_instruction);
+        ALLOC1(reg_PC_CURRENT_INSTRUCTION_ENABLE,Tcontrol_t,_param->_nb_instruction);
+        ALLOC1(reg_PC_NEXT_INSTRUCTION_ENABLE   ,Tcontrol_t,_param->_nb_instruction);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp	(revision 101)
@@ -47,4 +47,5 @@
 	if (_param->_have_port_inst_ifetch_ptr)
 	delete     in_PREDICT_INST_IFETCH_PTR            ;
+// 	delete     in_PREDICT_BRANCH_IS_CURRENT          ;
 	delete     in_PREDICT_BRANCH_STATE               ;
 	if (_param->_have_port_depth)
@@ -60,4 +61,5 @@
         if (usage_is_set(_usage,USE_SYSTEMC))
           {
+            delete reg_PC_ACCESS_INSTRUCTION_ENABLE ;
             delete reg_PC_CURRENT_INSTRUCTION_ENABLE;
             delete reg_PC_NEXT_INSTRUCTION_ENABLE   ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp	(revision 101)
@@ -28,16 +28,16 @@
     // =========================================
 
-    internal_ADDRESS_VAL = reg_PC_CURRENT_VAL;
+    internal_ADDRESS_VAL = reg_PC_ACCESS_VAL;
 
     PORT_WRITE(out_ADDRESS_VAL                        ,internal_ADDRESS_VAL                      );
-    PORT_WRITE(out_ADDRESS_INSTRUCTION_ADDRESS        ,reg_PC_CURRENT                            );
+    PORT_WRITE(out_ADDRESS_INSTRUCTION_ADDRESS        ,reg_PC_ACCESS                            );
     if (_param->_have_port_inst_ifetch_ptr)
-    PORT_WRITE(out_ADDRESS_INST_IFETCH_PTR            ,reg_PC_CURRENT_INST_IFETCH_PTR            );
-    PORT_WRITE(out_ADDRESS_BRANCH_STATE               ,reg_PC_CURRENT_BRANCH_STATE               );
+    PORT_WRITE(out_ADDRESS_INST_IFETCH_PTR            ,reg_PC_ACCESS_INST_IFETCH_PTR            );
+    PORT_WRITE(out_ADDRESS_BRANCH_STATE               ,reg_PC_ACCESS_BRANCH_STATE               );
     if (_param->_have_port_depth)
-    PORT_WRITE(out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID);
+    PORT_WRITE(out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID);
 
     for (uint32_t i=0; i<_param->_nb_instruction; i++)
-      PORT_WRITE(out_ADDRESS_INSTRUCTION_ENABLE [i], reg_PC_CURRENT_INSTRUCTION_ENABLE[i]);
+      PORT_WRITE(out_ADDRESS_INSTRUCTION_ENABLE [i], reg_PC_ACCESS_INSTRUCTION_ENABLE[i]);
 
     // =========================================
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp	(revision 98)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp	(revision 101)
@@ -28,8 +28,18 @@
       {
 	// nothing is valid
+	reg_PC_ACCESS_VAL    = 0;
+
 	reg_PC_CURRENT_VAL   = 0;
 
         reg_PC_NEXT_VAL      = 1;
         reg_PC_NEXT          = 0x100>>2;
+        reg_PC_NEXT_IS_DS_TAKE                  = 0;
+        reg_PC_NEXT_INSTRUCTION_ENABLE [0]      = 1;
+        for (uint32_t i=1; i<_param->_nb_instruction; i++)
+        reg_PC_NEXT_INSTRUCTION_ENABLE [i]      = 0;
+        reg_PC_NEXT_INST_IFETCH_PTR             = 0;
+        reg_PC_NEXT_BRANCH_STATE                = 0;
+        reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0;
+
 
 	reg_PC_NEXT_NEXT_VAL = 0;
@@ -42,11 +52,24 @@
 	if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL)
 	  {
+            bool branch_is_current = reg_PC_NEXT_IS_DS_TAKE;
+            if (branch_is_current)
+              {
+                if (_param->_have_port_inst_ifetch_ptr)
+                reg_PC_CURRENT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
+                reg_PC_CURRENT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
+                if (_param->_have_port_depth)
+                reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
+              }
+            else
+              {
+                if (_param->_have_port_inst_ifetch_ptr)
+                reg_PC_NEXT_INST_IFETCH_PTR                = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
+                reg_PC_NEXT_BRANCH_STATE                   = PORT_READ(in_PREDICT_BRANCH_STATE               );
+                if (_param->_have_port_depth)
+                reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID    = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
+              }
+
 	    for (uint32_t i=0; i<_param->_nb_instruction; i++)
 	    reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);
-	    if (_param->_have_port_inst_ifetch_ptr)
-	    reg_PC_NEXT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
-	    reg_PC_NEXT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
-	    if (_param->_have_port_depth)
-	    reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
 	    
 	    reg_PC_NEXT_NEXT_VAL                    = 1; // address is valid
@@ -64,50 +87,73 @@
 	// =========================================
 	// transaction with icache
-	if ( (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) or not reg_PC_CURRENT_VAL)
-	  {
+	if (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK))
+          {
+            reg_PC_ACCESS_VAL = 0;
 #ifdef STATISTICS
             if (usage_is_set(_usage,USE_STATISTICS))
-              if (reg_PC_CURRENT_VAL)
-                {
+              {
                   (*_stat_nb_transaction_address) ++;
                   
                   for (uint32_t i=0; i<_param->_nb_instruction; i++)
-                    if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true)
+                    if (reg_PC_ACCESS_INSTRUCTION_ENABLE [i] == true)
                       (*_stat_sum_packet_size) ++;
                 }
 #endif
-
-
-	    Tcontrol_t pc_next_val = reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL;
-
-	    // next pc became current pc
-	    reg_PC_CURRENT_VAL                             = pc_next_val;
-
-	    // if pc_next is not valid : don't erase PC and PC_IS_DS_TAKE : this register is send a the predict (to compute pc_next)
-	    if (pc_next_val)
-	      {
-		reg_PC_CURRENT                             = reg_PC_NEXT                            ;
-		reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
-		reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
-		reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
-		reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
-
-		for (uint32_t i=0; i<_param->_nb_instruction; i++)
-		reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
-	    
-		reg_PC_NEXT_VAL                            = reg_PC_NEXT_NEXT_VAL       ;
-		// if pc_next_next is not valid : don't erase PC_NEXT and PC_NEXT_IS_DS_TAKE : this register is send a the predict (to compute pc_next)
-		if (reg_PC_NEXT_NEXT_VAL)
-		  {
-		    reg_PC_NEXT                            = reg_PC_NEXT_NEXT           ;
-		    reg_PC_NEXT_IS_DS_TAKE                 = reg_PC_NEXT_NEXT_IS_DS_TAKE;
-		  }
-		
-		// invalid next next pc
-		reg_PC_NEXT_NEXT_VAL                       = 0;
-	      }
-
-	  }
-	
+          }
+        
+        // Shift register
+
+        if (not reg_PC_ACCESS_VAL and reg_PC_CURRENT_VAL and reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL)
+          {
+            reg_PC_ACCESS_VAL  = 1; // new request
+            reg_PC_CURRENT_VAL = 0; // invalid current
+            
+            reg_PC_ACCESS                             = reg_PC_CURRENT                            ;
+            reg_PC_ACCESS_IS_DS_TAKE                  = reg_PC_CURRENT_IS_DS_TAKE                 ;
+            reg_PC_ACCESS_INST_IFETCH_PTR             = reg_PC_CURRENT_INST_IFETCH_PTR            ;
+            reg_PC_ACCESS_BRANCH_STATE                = reg_PC_CURRENT_BRANCH_STATE               ;
+            reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID = reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID;
+            
+            for (uint32_t i=0; i<_param->_nb_instruction; i++)
+              reg_PC_ACCESS_INSTRUCTION_ENABLE [i] = reg_PC_CURRENT_INSTRUCTION_ENABLE [i];
+          }
+        
+        if (not reg_PC_CURRENT_VAL)
+          {
+            bool val = reg_PC_NEXT_VAL;
+            reg_PC_CURRENT_VAL = val; // new PC_CURRENT if PC_NEXT is valid
+            reg_PC_NEXT_VAL    = 0;   // invalid next
+
+            if (val)
+              {
+                reg_PC_CURRENT                             = reg_PC_NEXT                            ;
+                reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
+                reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
+                reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
+                reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
+                
+                for (uint32_t i=0; i<_param->_nb_instruction; i++)
+                  reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
+              }
+          }
+
+        if (not reg_PC_NEXT_VAL)
+          {
+            bool val = reg_PC_NEXT_NEXT_VAL;
+            reg_PC_NEXT_VAL      = val; // new PC_NEXT if PC_NEXT_NEXT is valid
+            reg_PC_NEXT_NEXT_VAL = 0;   // invalid next_next
+            
+            if (val)
+              {
+                reg_PC_NEXT                             = reg_PC_NEXT_NEXT                            ;
+                reg_PC_NEXT_IS_DS_TAKE                  = reg_PC_NEXT_NEXT_IS_DS_TAKE                 ;
+//              reg_PC_NEXT_INST_IFETCH_PTR             = reg_PC_NEXT_NEXT_INST_IFETCH_PTR            ;
+//              reg_PC_NEXT_BRANCH_STATE                = reg_PC_NEXT_NEXT_BRANCH_STATE               ;
+//              reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID;
+             
+//              for (uint32_t i=0; i<_param->_nb_instruction; i++)
+//                reg_PC_NEXT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE [i];
+              }
+          }
 
 	// =========================================
@@ -121,4 +167,6 @@
 	    log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT     : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS_NEXT    ),PORT_READ(in_EVENT_ADDRESS_NEXT    )<<2);
 	    log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT_VAL : %d"  ,PORT_READ(in_EVENT_ADDRESS_NEXT_VAL));
+
+	    reg_PC_ACCESS_VAL                       = 0;
 	    reg_PC_CURRENT_VAL                      = 0;
 	    reg_PC_NEXT_VAL                         = 1;
@@ -157,9 +205,58 @@
       }
 
-#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE)
+#if defined(DEBUG) and DEBUG_Address_management and (DEBUG >= DEBUG_TRACE)
     log_printf(TRACE,Address_management,FUNCTION,"  * Dump PC");
-    log_printf(TRACE,Address_management,FUNCTION,"    * Current   : %d %d 0x%.8x (%.8x)",reg_PC_CURRENT_VAL  , reg_PC_CURRENT_IS_DS_TAKE  , reg_PC_CURRENT  , reg_PC_CURRENT  <<2);
-    log_printf(TRACE,Address_management,FUNCTION,"    * Next      : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_VAL     , reg_PC_NEXT_IS_DS_TAKE     , reg_PC_NEXT     , reg_PC_NEXT     <<2);    
-    log_printf(TRACE,Address_management,FUNCTION,"    * Next_Next : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT, reg_PC_NEXT_NEXT<<2);    
+    {
+      std::string instruction_enable;
+      for (uint32_t i=0; i<_param->_nb_instruction; ++i)
+        instruction_enable += toString(reg_PC_ACCESS_INSTRUCTION_ENABLE [i])+ " ";
+
+      log_printf(TRACE,Address_management,FUNCTION,"    * Access    : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s",
+                 reg_PC_ACCESS_VAL,
+                 reg_PC_ACCESS_IS_DS_TAKE,
+                 reg_PC_ACCESS,
+                 reg_PC_ACCESS<<2,
+                 reg_PC_ACCESS_BRANCH_STATE,
+                 reg_PC_ACCESS_INST_IFETCH_PTR,
+                 reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID,
+                 instruction_enable.c_str()
+                 );
+    }
+    {
+      std::string instruction_enable;
+      for (uint32_t i=0; i<_param->_nb_instruction; ++i)
+        instruction_enable += toString(reg_PC_CURRENT_INSTRUCTION_ENABLE [i])+ " ";
+
+      log_printf(TRACE,Address_management,FUNCTION,"    * Current   : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s",
+                 reg_PC_CURRENT_VAL,
+                 reg_PC_CURRENT_IS_DS_TAKE,
+                 reg_PC_CURRENT,
+                 reg_PC_CURRENT<<2,
+                 reg_PC_CURRENT_BRANCH_STATE,
+                 reg_PC_CURRENT_INST_IFETCH_PTR,
+                 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID,
+                 instruction_enable.c_str()
+                 );
+    }
+    {
+      std::string instruction_enable;
+      for (uint32_t i=0; i<_param->_nb_instruction; ++i)
+        instruction_enable += toString(reg_PC_NEXT_INSTRUCTION_ENABLE [i])+ " ";
+
+      log_printf(TRACE,Address_management,FUNCTION,"    * Next      : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s",
+                 reg_PC_NEXT_VAL,
+                 reg_PC_NEXT_IS_DS_TAKE,
+                 reg_PC_NEXT,
+                 reg_PC_NEXT<<2,
+                 reg_PC_NEXT_BRANCH_STATE,
+                 reg_PC_NEXT_INST_IFETCH_PTR,
+                 reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID,
+                 instruction_enable.c_str());
+    }
+    log_printf(TRACE,Address_management,FUNCTION,"    * Next_Next : %d %d 0x%.8x (%.8x)",
+               reg_PC_NEXT_NEXT_VAL,
+               reg_PC_NEXT_NEXT_IS_DS_TAKE,
+               reg_PC_NEXT_NEXT,
+               reg_PC_NEXT_NEXT<<2);    
 #endif 
 
