Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp	(revision 101)
@@ -250,218 +250,218 @@
       LABEL("Iteration %d",iteration);
 
-      // PREDICT
-      {
-	in_PREDICT_ACK  ->write((rand()%100)<percent_transaction_predict);
+//       // PREDICT
+//       {
+// 	in_PREDICT_ACK  ->write((rand()%100)<percent_transaction_predict);
 	
-	SC_START(0);
-
-	Taddress_t addr  = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read();
-
-	uint32_t   begin = addr%_param->_nb_instruction;
-	uint32_t   end   = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1);
-	Tcontrol_t take  = (nb_packet_in%jump)==0;
+// 	SC_START(0);
+
+// 	Taddress_t addr  = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read();
+
+// 	uint32_t   begin = addr%_param->_nb_instruction;
+// 	uint32_t   end   = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1);
+// 	Tcontrol_t take  = (nb_packet_in%jump)==0;
 	
-	if (take)
-	  addr += 0x100;
-	else
-	  addr += end-begin+1;
-
-	for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	in_PREDICT_INSTRUCTION_ENABLE     [i] ->write((i>=begin) and (i<=end));
-	in_PREDICT_PC_NEXT                    ->write(addr);
-	in_PREDICT_PC_NEXT_IS_DS_TAKE         ->write(take);
-	in_PREDICT_INST_IFETCH_PTR            ->write(0);
-	in_PREDICT_BRANCH_STATE               ->write(0);
-	in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0);
-      }
-
-      // DECOD
-      {
-	uint32_t nb_decod = (rand()%_param->_nb_instruction);
-
-	for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	  in_DECOD_ACK [i]->write(i<=nb_decod);
-      }
-
-      // EVENT
-      in_EVENT_VAL             ->write((rand()%100)<percent_transaction_event  );
-      in_EVENT_ADDRESS         ->write(0x77);
-      in_EVENT_ADDRESS_NEXT    ->write(0x171);
-      Tcontrol_t is_ds_take = rand();
-      in_EVENT_ADDRESS_NEXT_VAL->write(is_ds_take);
-      in_EVENT_IS_DS_TAKE      ->write(is_ds_take);
-
-      // ICACHE_REQ
-      in_ICACHE_REQ_ACK->write((rand()%100)<percent_transaction_icache_req);
-
-      // ICACHE_RSP
-      {
-	Tcontrol_t val = false;
-	if (not cache->empty())
-	  {
-	    slot_t<cache_req_t *> cache_rsp = cache->read();
-
-	    val = (cache_rsp._delay == 0);
+// 	if (take)
+// 	  addr += 0x100;
+// 	else
+// 	  addr += end-begin+1;
+
+// 	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+// 	in_PREDICT_INSTRUCTION_ENABLE     [i] ->write((i>=begin) and (i<=end));
+// 	in_PREDICT_PC_NEXT                    ->write(addr);
+// 	in_PREDICT_PC_NEXT_IS_DS_TAKE         ->write(take);
+// 	in_PREDICT_INST_IFETCH_PTR            ->write(0);
+// 	in_PREDICT_BRANCH_STATE               ->write(0);
+// 	in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0);
+//       }
+
+//       // DECOD
+//       {
+// 	uint32_t nb_decod = (rand()%_param->_nb_instruction);
+
+// 	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+// 	  in_DECOD_ACK [i]->write(i<=nb_decod);
+//       }
+
+//       // EVENT
+//       in_EVENT_VAL             ->write((rand()%100)<percent_transaction_event  );
+//       in_EVENT_ADDRESS         ->write(0x77);
+//       in_EVENT_ADDRESS_NEXT    ->write(0x171);
+//       Tcontrol_t is_ds_take = rand();
+//       in_EVENT_ADDRESS_NEXT_VAL->write(is_ds_take);
+//       in_EVENT_IS_DS_TAKE      ->write(is_ds_take);
+
+//       // ICACHE_REQ
+//       in_ICACHE_REQ_ACK->write((rand()%100)<percent_transaction_icache_req);
+
+//       // ICACHE_RSP
+//       {
+// 	Tcontrol_t val = false;
+// 	if (not cache->empty())
+// 	  {
+// 	    slot_t<cache_req_t *> cache_rsp = cache->read();
+
+// 	    val = (cache_rsp._delay == 0);
 	    
-	    Tpacket_t  packet  = cache_rsp._data->packet ;
-	    Taddress_t address = cache_rsp._data->address;
+// 	    Tpacket_t  packet  = cache_rsp._data->packet ;
+// 	    Taddress_t address = cache_rsp._data->address;
 	    
-	    in_ICACHE_RSP_PACKET_ID      ->write(packet);
-	    for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	    in_ICACHE_RSP_INSTRUCTION [i]->write(address+i);
-	    in_ICACHE_RSP_ERROR          ->write(0);
-	  }
-
-	in_ICACHE_RSP_VAL->write(val);
-      }
-
-      //-------------------------------------------------
-      SC_START(0);
-      //-------------------------------------------------
-
-      if (out_ICACHE_REQ_VAL->read() and in_ICACHE_REQ_ACK->read())
-	{
-	  LABEL("ICACHE_REQ : Transaction accepted");
-
-	  Tpacket_t  packet  = (_param->_have_port_ifetch_queue_ptr)?out_ICACHE_REQ_PACKET_ID->read():0;
-	  Taddress_t address = out_ICACHE_REQ_ADDRESS->read();
-
-	  TEST(bool      ,slot_use[packet], false);
-	  TEST(Taddress_t,address         ,c_addr);
-
-	  slot_use[packet] = true;
-
-	  uint32_t delay;
-	  if ((rand()%100)<percent_hit)
-	    delay = 1;
-	  else
-	    delay = delay_miss_min + (rand()%(delay_miss_max-delay_miss_min+1));
-
-	  cache_req_t * cache_req = new cache_req_t(packet,address);
-	  cache->push(delay,cache_req);
-
-	  c_val = 0;
-	  nb_packet_in ++;
-	}
-
-      {
-	bool find=false;
-
-	Taddress_t addr=out_DECOD_ADDRESS->read();
-	for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	  if (out_DECOD_VAL[i]->read() and in_DECOD_ACK [i]->read())
-	    {
-	      Tinstruction_t inst = out_DECOD_INSTRUCTION[i]->read();
-	      LABEL("DECOD [%d]  : Transaction accepted",i);
-	      LABEL("  address     : 0x%x",addr);
-	      LABEL("  instruction : 0x%x",inst);
-
-	      find = true;
-	      TEST(Tinstruction_t,inst,addr+i);
-	    }
-
-	if (find)
-	  {
-	    if (_param->_have_port_inst_ifetch_ptr)
-	    TEST(Tinst_ifetch_ptr_t, out_DECOD_INST_IFETCH_PTR            ->read(), 0);
-	    TEST(Tbranch_state_t   , out_DECOD_BRANCH_STATE               ->read(), 0);
-	    if (_param->_have_port_depth)
-	    TEST(Tprediction_ptr_t , out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(), 0);
-	    TEST(Texception_t      , out_DECOD_EXCEPTION                  ->read(), 0);
-	  }
-      }
+// 	    in_ICACHE_RSP_PACKET_ID      ->write(packet);
+// 	    for (uint32_t i=0; i<_param->_nb_instruction; i++)
+// 	    in_ICACHE_RSP_INSTRUCTION [i]->write(address+i);
+// 	    in_ICACHE_RSP_ERROR          ->write(0);
+// 	  }
+
+// 	in_ICACHE_RSP_VAL->write(val);
+//       }
+
+//       //-------------------------------------------------
+//       SC_START(0);
+//       //-------------------------------------------------
+
+//       if (out_ICACHE_REQ_VAL->read() and in_ICACHE_REQ_ACK->read())
+// 	{
+// 	  LABEL("ICACHE_REQ : Transaction accepted");
+
+// 	  Tpacket_t  packet  = (_param->_have_port_ifetch_queue_ptr)?out_ICACHE_REQ_PACKET_ID->read():0;
+// 	  Taddress_t address = out_ICACHE_REQ_ADDRESS->read();
+
+// 	  TEST(bool      ,slot_use[packet], false);
+// 	  TEST(Taddress_t,address         ,c_addr);
+
+// 	  slot_use[packet] = true;
+
+// 	  uint32_t delay;
+// 	  if ((rand()%100)<percent_hit)
+// 	    delay = 1;
+// 	  else
+// 	    delay = delay_miss_min + (rand()%(delay_miss_max-delay_miss_min+1));
+
+// 	  cache_req_t * cache_req = new cache_req_t(packet,address);
+// 	  cache->push(delay,cache_req);
+
+// 	  c_val = 0;
+// 	  nb_packet_in ++;
+// 	}
+
+//       {
+// 	bool find=false;
+
+// 	Taddress_t addr=out_DECOD_ADDRESS->read();
+// 	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+// 	  if (out_DECOD_VAL[i]->read() and in_DECOD_ACK [i]->read())
+// 	    {
+// 	      Tinstruction_t inst = out_DECOD_INSTRUCTION[i]->read();
+// 	      LABEL("DECOD [%d]  : Transaction accepted",i);
+// 	      LABEL("  address     : 0x%x",addr);
+// 	      LABEL("  instruction : 0x%x",inst);
+
+// 	      find = true;
+// 	      TEST(Tinstruction_t,inst,addr+i);
+// 	    }
+
+// 	if (find)
+// 	  {
+// 	    if (_param->_have_port_inst_ifetch_ptr)
+// 	    TEST(Tinst_ifetch_ptr_t, out_DECOD_INST_IFETCH_PTR            ->read(), 0);
+// 	    TEST(Tbranch_state_t   , out_DECOD_BRANCH_STATE               ->read(), 0);
+// 	    if (_param->_have_port_depth)
+// 	    TEST(Tprediction_ptr_t , out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(), 0);
+// 	    TEST(Texception_t      , out_DECOD_EXCEPTION                  ->read(), 0);
+// 	  }
+//       }
       
-      if (in_ICACHE_RSP_VAL->read() and out_ICACHE_RSP_ACK->read())
-	{
-	  LABEL("ICACHE_RSP : Transaction accepted");
-
-	  slot_use[cache->read()._data->packet] = false;
-
-	  cache->pop();
-	}
-
-      if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())
-	{
-	  LABEL("PREDICT    : Transaction accepted");
-
-	  if (c_val)
-	  TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS          ->read(),c_addr      );
-	  TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT           ->read(),n_addr      );
-	  TEST(Tcontrol_t        ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take);
-
-	  nn_val        = true;
-	  nn_addr       = in_PREDICT_PC_NEXT           ->read();
-	  nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read();
+//       if (in_ICACHE_RSP_VAL->read() and out_ICACHE_RSP_ACK->read())
+// 	{
+// 	  LABEL("ICACHE_RSP : Transaction accepted");
+
+// 	  slot_use[cache->read()._data->packet] = false;
+
+// 	  cache->pop();
+// 	}
+
+//       if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())
+// 	{
+// 	  LABEL("PREDICT    : Transaction accepted");
+
+// 	  if (c_val)
+// 	  TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS          ->read(),c_addr      );
+// 	  TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT           ->read(),n_addr      );
+// 	  TEST(Tcontrol_t        ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take);
+
+// 	  nn_val        = true;
+// 	  nn_addr       = in_PREDICT_PC_NEXT           ->read();
+// 	  nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read();
 	
-	  for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	  n_enable [i]  = in_PREDICT_INSTRUCTION_ENABLE [i]->read();
-	}
-
-      if (not c_val)
-	{
-	  if (n_val and nn_val)
-	    {
-	      c_val        = 1;
-	      c_addr       = n_addr;
-	      c_is_ds_take = n_is_ds_take;
-
-	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
-		c_enable [i] = n_enable [i];
+// 	  for (uint32_t i=0; i<_param->_nb_instruction; i++)
+// 	  n_enable [i]  = in_PREDICT_INSTRUCTION_ENABLE [i]->read();
+// 	}
+
+//       if (not c_val)
+// 	{
+// 	  if (n_val and nn_val)
+// 	    {
+// 	      c_val        = 1;
+// 	      c_addr       = n_addr;
+// 	      c_is_ds_take = n_is_ds_take;
+
+// 	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
+// 		c_enable [i] = n_enable [i];
 	      
-	      n_val        = 1;
-	      n_addr       = nn_addr;
-	      n_is_ds_take = nn_is_ds_take;
+// 	      n_val        = 1;
+// 	      n_addr       = nn_addr;
+// 	      n_is_ds_take = nn_is_ds_take;
 	      
-	      nn_val       = 0;
-	    }
-	}
-
-      if (in_EVENT_VAL->read() and out_EVENT_ACK->read())
-	{
-	  LABEL("EVENT      : Transaction accepted");
-
-	  c_val           = false;
-	  n_val           = true;
-
-	  n_addr          = in_EVENT_ADDRESS->read();
-	  n_is_ds_take    = in_EVENT_IS_DS_TAKE->read();
-	  nn_val          = in_EVENT_ADDRESS_NEXT_VAL->read();
-	  nn_addr         = in_EVENT_ADDRESS_NEXT    ->read();
-          nn_is_ds_take   = 0;
-
-	  n_enable [0] = 1;
-	  for (uint32_t i=1; i<_param->_nb_instruction; i++)
-	    n_enable [i] = 0;
-	}
+// 	      nn_val       = 0;
+// 	    }
+// 	}
+
+//       if (in_EVENT_VAL->read() and out_EVENT_ACK->read())
+// 	{
+// 	  LABEL("EVENT      : Transaction accepted");
+
+// 	  c_val           = false;
+// 	  n_val           = true;
+
+// 	  n_addr          = in_EVENT_ADDRESS->read();
+// 	  n_is_ds_take    = in_EVENT_IS_DS_TAKE->read();
+// 	  nn_val          = in_EVENT_ADDRESS_NEXT_VAL->read();
+// 	  nn_addr         = in_EVENT_ADDRESS_NEXT    ->read();
+//           nn_is_ds_take   = 0;
+
+// 	  n_enable [0] = 1;
+// 	  for (uint32_t i=1; i<_param->_nb_instruction; i++)
+// 	    n_enable [i] = 0;
+// 	}
 
       
-      {
-	string str_c_enable = "";
-	string str_n_enable = "";
-
-	for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	  {
-	    str_c_enable += " " + toString(c_enable [i]);
-	    str_n_enable += " " + toString(n_enable [i]);
-	  }
-
-	LABEL("-----------------------------------");
-	LABEL("  * nb_packet_in  : %d",nb_packet_in);
-	LABEL("  * nb_packet_out : %d",nb_packet_out);
-	LABEL("  * pc   : %d %d %.8x %s",c_val  ,c_is_ds_take , c_addr ,str_c_enable.c_str());
-	if (nn_val)
-	  {
-	LABEL("  * pc+4 : %d %d %.8x %s",n_val  ,n_is_ds_take , n_addr ,str_n_enable.c_str());
-	  }
-	else
-	  {
-	LABEL("  * pc+4 : %d %d %.8x"   ,n_val  ,n_is_ds_take , n_addr );
-	  }
-	LABEL("  * pc+8 : %d %d %.8x"   ,nn_val ,nn_is_ds_take, nn_addr);
-	LABEL("-----------------------------------");
-      }
-
-      SC_START(1);
-      cache->transition();
+//       {
+// 	string str_c_enable = "";
+// 	string str_n_enable = "";
+
+// 	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+// 	  {
+// 	    str_c_enable += " " + toString(c_enable [i]);
+// 	    str_n_enable += " " + toString(n_enable [i]);
+// 	  }
+
+// 	LABEL("-----------------------------------");
+// 	LABEL("  * nb_packet_in  : %d",nb_packet_in);
+// 	LABEL("  * nb_packet_out : %d",nb_packet_out);
+// 	LABEL("  * pc   : %d %d %.8x %s",c_val  ,c_is_ds_take , c_addr ,str_c_enable.c_str());
+// 	if (nn_val)
+// 	  {
+// 	LABEL("  * pc+4 : %d %d %.8x %s",n_val  ,n_is_ds_take , n_addr ,str_n_enable.c_str());
+// 	  }
+// 	else
+// 	  {
+// 	LABEL("  * pc+4 : %d %d %.8x"   ,n_val  ,n_is_ds_take , n_addr );
+// 	  }
+// 	LABEL("  * pc+8 : %d %d %.8x"   ,nn_val ,nn_is_ds_take, nn_addr);
+// 	LABEL("-----------------------------------");
+//       }
+
+//       SC_START(1);
+//       cache->transition();
     }
 
