Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/test.cpp (revision 101) @@ -80,4 +80,28 @@ } + { + cout << "------------------------------------------------------" << endl; + + Instance * instance = new Instance ("../../../Files/Instance_scalar_3.cfg", + generator1, + _get_custom_information + ); + instance->toFile("data_out"); + + delete instance; + } + + { + cout << "------------------------------------------------------" << endl; + + Instance * instance = new Instance ("../../../Files/Instance_scalar_4.cfg", + generator1, + _get_custom_information + ); + instance->toFile("data_out"); + + delete instance; + } + delete configuration1; delete instance1; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h (revision 101) @@ -28,8 +28,8 @@ void operation_l_addc (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); void operation_l_sub (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); -//void operation_l_mul (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); -//void operation_l_mulu (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); -//void operation_l_div (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); -//void operation_l_divu (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); + void operation_l_mul (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); + void operation_l_mulu (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); + void operation_l_div (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); + void operation_l_divu (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); void operation_l_and (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); void operation_l_or (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp (revision 101) @@ -90,5 +90,7 @@ bool overflow = ovf (param->_size_data,gpr1,gpr2,gpr3); - bool carry_out = carry(param->_size_data,gpr1,gpr2,gpr3); +// bool carry_out = carry(param->_size_data,gpr1,gpr2,gpr3); + // In ISA : l.sub don't change flag carry + bool carry_out = get_flag(op->_data_rc,FLAG_CY); // Result @@ -104,4 +106,126 @@ #undef FUNCTION +#define FUNCTION "Functionnal_unit::operation_l_mul" + void operation_l_mul (execute_operation_t * op, execute_register_t * reg, execute_param_t * param) + { + log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_mul"); + + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr3 ; + bool overflow ; + bool carry_out ; + + if (param->_size_data == 32) + { + int64_t res = static_cast(gpr1) * static_cast(gpr2); + + log_printf(TRACE,Functionnal_unit,FUNCTION," * res : %llx",res); + + gpr3 = param->_mask_data & static_cast(res); + carry_out = res != gpr3; + overflow = carry_out; + } + else + { + throw ERRORMORPHEO(FUNCTION,_("64 bits multiplcation : not yet implemented\n")); + } + + // Result + op->_timing = param->_timing[op->_type][op->_operation]; + op->_data_rd = gpr3; + op->_data_re = 0; + op->_data_re = set_flag(op->_data_re,FLAG_OV,overflow ); + op->_data_re = set_flag(op->_data_re,FLAG_CY,carry_out); + op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; + op->_no_sequence = 0; + //op->_address = 0; + }; + +#undef FUNCTION +#define FUNCTION "Functionnal_unit::operation_l_mulu" + void operation_l_mulu (execute_operation_t * op, execute_register_t * reg, execute_param_t * param) + { + log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_mulu"); + + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,op->_data_rb); + Tgeneral_data_t gpr3 ; + bool overflow ; + bool carry_out ; + + if (param->_size_data == 32) + { + uint64_t res = static_cast(gpr1) * static_cast(gpr2); + + log_printf(TRACE,Functionnal_unit,FUNCTION," * res : %llx",res); + + gpr3 = param->_mask_data & static_cast(res); + carry_out = res != gpr3; + overflow = carry_out; + } + else + { + throw ERRORMORPHEO(FUNCTION,_("64 bits multiplcation : not yet implemented\n")); + } + + // Result + op->_timing = param->_timing[op->_type][op->_operation]; + op->_data_rd = gpr3; + op->_data_re = 0; + op->_data_re = set_flag(op->_data_re,FLAG_OV,overflow ); + op->_data_re = set_flag(op->_data_re,FLAG_CY,carry_out); + op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; + op->_no_sequence = 0; + //op->_address = 0; + }; + +#undef FUNCTION +#define FUNCTION "Functionnal_unit::operation_l_div" + void operation_l_div (execute_operation_t * op, execute_register_t * reg, execute_param_t * param) + { + log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_div"); + + Tgeneral_data_t gpr1 = signed(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = signed(param->_size_data,op->_data_rb); + Tgeneral_data_t gpr3 = (gpr2!=0)?(gpr1/gpr2):0; + bool overflow = ovf (param->_size_data,gpr1,gpr2,gpr3); + bool carry_out = (gpr2==0); + + // Result + op->_timing = param->_timing[op->_type][op->_operation]; + op->_data_rd = gpr3; + op->_data_re = 0; + op->_data_re = set_flag(op->_data_re,FLAG_OV,overflow ); + op->_data_re = set_flag(op->_data_re,FLAG_CY,carry_out); + op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; + op->_no_sequence = 0; + //op->_address = 0; + }; + +#undef FUNCTION +#define FUNCTION "Functionnal_unit::operation_l_divu" + void operation_l_divu (execute_operation_t * op, execute_register_t * reg, execute_param_t * param) + { + log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_divu"); + + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,op->_data_rb); + Tgeneral_data_t gpr3 = (gpr2!=0)?(gpr1/gpr2):0; + bool overflow = ovf (param->_size_data,gpr1,gpr2,gpr3); + bool carry_out = (gpr2==0); + + // Result + op->_timing = param->_timing[op->_type][op->_operation]; + op->_data_rd = gpr3; + op->_data_re = 0; + op->_data_re = set_flag(op->_data_re,FLAG_OV,overflow ); + op->_data_re = set_flag(op->_data_re,FLAG_CY,carry_out); + op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; + op->_no_sequence = 0; + //op->_address = 0; + }; + +#undef FUNCTION #define FUNCTION "Functionnal_unit::operation_l_and" void operation_l_and (execute_operation_t * op, execute_register_t * reg, execute_param_t * param) @@ -465,4 +589,5 @@ Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); + // Tgeneral_data_t is unsigned bool f_out = (gpr1 >= gpr2); @@ -485,4 +610,5 @@ Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); + // Tgeneral_data_t is unsigned bool f_out = (gpr1 > gpr2); @@ -505,4 +631,5 @@ Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); + // Tgeneral_data_t is unsigned bool f_out = (gpr1 <= gpr2); @@ -525,4 +652,5 @@ Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); + // Tgeneral_data_t is unsigned bool f_out = (gpr1 < gpr2); @@ -544,20 +672,18 @@ Tgeneral_data_t gpr1 = op->_data_ra; Tgeneral_data_t gpr2 = (op->_has_immediat==1)?op->_immediat:op->_data_rb; - - log_printf(TRACE,Functionnal_unit,FUNCTION," * data_ra : %.8x",unsigned(param->_size_data,op->_data_ra)); - log_printf(TRACE,Functionnal_unit,FUNCTION," * data_ras : %.8x", signed(param->_size_data,op->_data_ra)); - log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rb : %.8x",unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb)); - log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rbs : %.8x", signed(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb)); - + bool f_out; - switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) - { - case 1 /*b01*/ : f_out = 1 ; break; - case 2 /*b10*/ : f_out = 0 ; break; - default : f_out = signed(param->_size_data,gpr1) >= signed(param->_size_data,gpr2); break; - } - - log_printf(TRACE,Functionnal_unit,FUNCTION," * f_out : %.8x",f_out); + if (param->_size_data == 32) + f_out = static_cast(gpr1) >= static_cast(gpr2); + else + f_out = static_cast(gpr1) >= static_cast(gpr2); + +// switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) +// { +// case 1 /*b01*/ : f_out = 1 ; break; +// case 2 /*b10*/ : f_out = 0 ; break; +// default : f_out = signed(param->_size_data,gpr1) >= signed(param->_size_data,gpr2); break; +// } // Result @@ -581,10 +707,15 @@ bool f_out; - switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) - { - case 1 /*b01*/ : f_out = 1; break; - case 2 /*b10*/ : f_out = 0; break; - default : f_out = signed(param->_size_data,gpr1) > signed(param->_size_data,gpr2); break; - } + if (param->_size_data == 32) + f_out = static_cast(gpr1) > static_cast(gpr2); + else + f_out = static_cast(gpr1) > static_cast(gpr2); + +// switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) +// { +// case 1 /*b01*/ : f_out = 1; break; +// case 2 /*b10*/ : f_out = 0; break; +// default : f_out = signed(param->_size_data,gpr1) > signed(param->_size_data,gpr2); break; +// } // Result @@ -608,10 +739,15 @@ bool f_out; - switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) - { - case 1 /*b01*/ : f_out = 0; break; - case 2 /*b10*/ : f_out = 1; break; - default : f_out = signed(param->_size_data,gpr1) <= signed(param->_size_data,gpr2); break; - } + if (param->_size_data == 32) + f_out = static_cast(gpr1) <= static_cast(gpr2); + else + f_out = static_cast(gpr1) <= static_cast(gpr2); + +// switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) +// { +// case 1 /*b01*/ : f_out = 0; break; +// case 2 /*b10*/ : f_out = 1; break; +// default : f_out = signed(param->_size_data,gpr1) <= signed(param->_size_data,gpr2); break; +// } // Result @@ -635,10 +771,15 @@ bool f_out; - switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) - { - case 1 /*b01*/ : f_out = 0; break; - case 2 /*b10*/ : f_out = 1; break; - default : f_out = signed(param->_size_data,gpr1) < signed(param->_size_data,gpr2); break; - } + if (param->_size_data == 32) + f_out = static_cast(gpr1) < static_cast(gpr2); + else + f_out = static_cast(gpr1) < static_cast(gpr2); + +// switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) +// { +// case 1 /*b01*/ : f_out = 0; break; +// case 2 /*b10*/ : f_out = 1; break; +// default : f_out = signed(param->_size_data,gpr1) < signed(param->_size_data,gpr2); break; +// } // Result Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp (revision 101) @@ -18,5 +18,5 @@ public : const Tcontext_t _front_end_id ; public : const Tcontext_t _ooo_engine_id; -public : const Tpacket_t _packet_id ; +public : const uint32_t _packet_id ; public : const Toperation_t _operation ; public : const Ttype_t _type ; @@ -40,5 +40,5 @@ Tcontext_t front_end_id , Tcontext_t ooo_engine_id, - Tpacket_t packet_id , + uint32_t packet_id , Toperation_t operation , Ttype_t type , @@ -356,11 +356,11 @@ transaction_in.push_back(execute_transaction(_param,0,0,0, 99,OPERATION_FIND_L_FL1 ,TYPE_FIND,0,0 ,0x80000000,0x0 ,0 ,1,63,32 ,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); -// transaction_in.push_back(execute_transaction(_param,0,0,0,100,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12344321,0x1 ,0 ,1,63,0x12344320,1,15,0 ,EXCEPTION_NONE ,0)); -// transaction_in.push_back(execute_transaction(_param,0,0,0,101,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12345678,0xffffffff,0 ,1,56,0x12345679,1,3 ,0 ,EXCEPTION_NONE ,0)); -// transaction_in.push_back(execute_transaction(_param,0,0,0,102,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12345678,0x12345678,0 ,1,56,0x0 ,1,3 ,0 ,EXCEPTION_NONE ,0)); -// transaction_in.push_back(execute_transaction(_param,0,0,0,103,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x0 ,0x0 ,0 ,1,56,0x0 ,1,3 ,0 ,EXCEPTION_NONE ,0)); -// transaction_in.push_back(execute_transaction(_param,0,0,0,104,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x70000000,0x90000000,0 ,1,56,0x0 ,1,3 ,FLAG_CY ,EXCEPTION_NONE ,0)); -// transaction_in.push_back(execute_transaction(_param,0,0,0,105,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x80001000,0x80000000,0 ,1,1 ,0x1000 ,1,0 ,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); -// transaction_in.push_back(execute_transaction(_param,0,0,0,106,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x00000001,0x7fffffff,FLAG_CY|FLAG_OV,1,1 ,0x80000000,1,0 , FLAG_OV,EXCEPTION_ALU_RANGE,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,100,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12344321,0x1 ,0 ,1,63,0x12344320,1,15,0 ,EXCEPTION_NONE ,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,101,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12345678,0xffffffff,0 ,1,56,0x12345679,1,3 ,0 ,EXCEPTION_NONE ,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,102,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12345678,0x12345678,0 ,1,56,0x0 ,1,3 ,0 ,EXCEPTION_NONE ,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,103,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x0 ,0x0 ,0 ,1,56,0x0 ,1,3 ,0 ,EXCEPTION_NONE ,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,104,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x70000000,0x90000000,0 ,1,56,0xe0000000,1,3 , FLAG_OV,EXCEPTION_ALU_RANGE,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,105,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x80001000,0x80000000,0 ,1,1 ,0x1000 ,1,0 , FLAG_OV,EXCEPTION_ALU_RANGE,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,106,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x00000001,0x7fffffff,FLAG_CY|FLAG_OV,1,1 ,0x80000002,1,0 ,FLAG_CY ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0,120,OPERATION_TEST_L_SFEQ ,TYPE_TEST,0,0 ,0xdead ,0xdead ,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // + == + @@ -440,5 +440,5 @@ transaction_in.push_back(execute_transaction(_param,0,0,0,232,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0x21071981,0x25071959,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // + < + transaction_in.push_back(execute_transaction(_param,0,0,0,233,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbeef,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - == - - transaction_in.push_back(execute_transaction(_param,0,0,0,234,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbabe,0xdeadbeef,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - > - + transaction_in.push_back(execute_transaction(_param,0,0,0,234,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbabe,0xdeadbeef,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - > - transaction_in.push_back(execute_transaction(_param,0,0,0,235,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbabe,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - < - transaction_in.push_back(execute_transaction(_param,0,0,0,236,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbeef,0x21524111,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - == + (in unsigned) @@ -569,4 +569,18 @@ transaction_in.push_back(execute_transaction(_param,0,0,0,628,OPERATION_SPECIAL_L_MFSPR ,TYPE_SPECIAL,1,GROUP_CUSTOM_7<<11, 0,0x0 ,0 ,1,63,0xa ,0, 0,0 ,EXCEPTION_ALU_NONE ,0,(GROUP_CUSTOM_7<<11)|0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,700,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x00000001,0x00000001,0 ,1,63,0x00000001,1,15,0 ,EXCEPTION_NONE ,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,701,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x00002107,0x00001981,0 ,1,63,0x034a5387,1,15,0 ,EXCEPTION_NONE ,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x00048698,0x0000dead,0 ,1,63,0xefc6c4b8,1,15,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x40000000,0x00000002,0 ,1,63,0x80000000,1,15, FLAG_OV,EXCEPTION_ALU_RANGE,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x40000000,0x00000004,0 ,1,63,0x00000000,1,15,FLAG_CY ,EXCEPTION_NONE ,0)); + + transaction_in.push_back(execute_transaction(_param,0,0,0,700,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00000001,0x00000001,0 ,1,63,0x00000001,1,15,0 ,EXCEPTION_NONE ,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,701,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00002107,0x00001981,0 ,1,63,0x034a5387,1,15,0 ,EXCEPTION_NONE ,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00048698,0x0000dead,0 ,1,63,0xefc6c4b8,1,15,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x40000000,0x00000002,0 ,1,63,0x80000000,1,15, FLAG_OV,EXCEPTION_ALU_RANGE,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x40000000,0x00000004,0 ,1,63,0x00000000,1,15,FLAG_CY ,EXCEPTION_NONE ,0)); + + + LABEL("Reset"); in_NRESET.write(0); @@ -585,7 +599,7 @@ LABEL("Iteration %d",iteration); - + while (nb_transaction_out > 0) - { + { Tcontrol_t val = ((rand()%100) < percent_transaction_execute_in) and not transaction_in.empty(); in_EXECUTE_IN_VAL .write(val); @@ -601,5 +615,5 @@ in_EXECUTE_IN_OOO_ENGINE_ID .write(transaction_in.front()._ooo_engine_id); if (_param->_have_port_rob_ptr) - in_EXECUTE_IN_PACKET_ID .write(transaction_in.front()._packet_id ); + in_EXECUTE_IN_PACKET_ID .write(static_cast(transaction_in.front()._packet_id)); in_EXECUTE_IN_OPERATION .write(transaction_in.front()._operation ); in_EXECUTE_IN_TYPE .write(transaction_in.front()._type ); @@ -624,5 +638,5 @@ // TEST if (_param->_have_port_rob_ptr) - TEST(Tpacket_t , out_EXECUTE_OUT_PACKET_ID .read(), transaction_out.front()._packet_id ); + TEST(Tpacket_t , out_EXECUTE_OUT_PACKET_ID .read(), static_cast(transaction_out.front()._packet_id )); if (_param->_have_port_context_id) TEST(Tcontext_t , out_EXECUTE_OUT_CONTEXT_ID .read(), transaction_out.front()._context_id ); @@ -649,5 +663,4 @@ TEST(Tgeneral_data_t , out_EXECUTE_OUT_DATA_RD .read(), transaction_out.front()._data_rd ); TEST(Tgeneral_data_t , out_EXECUTE_OUT_ADDRESS .read(), transaction_out.front()._address ); - break; } @@ -659,5 +672,4 @@ TEST(Tgeneral_data_t , out_EXECUTE_OUT_DATA_RD .read(), transaction_out.front()._data_rd ); TEST(Tgeneral_data_t , out_EXECUTE_OUT_ADDRESS .read(), transaction_out.front()._address ); - break; } @@ -685,7 +697,8 @@ SC_START(1); - } + } } + /******************************************************** * Simulation - End Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp (revision 101) @@ -174,6 +174,6 @@ if (_param->_timing[TYPE_ALU ][OPERATION_ALU_L_ADDC ]._latence > 0) _function_execute[TYPE_ALU ][OPERATION_ALU_L_ADDC ] = &(operation_l_addc ); -// if (_param->_timing[TYPE_ALU ][OPERATION_ALU_L_SUB ]._latence > 0) -// _function_execute[TYPE_ALU ][OPERATION_ALU_L_SUB ] = &(operation_l_sub ); + if (_param->_timing[TYPE_ALU ][OPERATION_ALU_L_SUB ]._latence > 0) + _function_execute[TYPE_ALU ][OPERATION_ALU_L_SUB ] = &(operation_l_sub ); if (_param->_timing[TYPE_ALU ][OPERATION_ALU_L_AND ]._latence > 0) _function_execute[TYPE_ALU ][OPERATION_ALU_L_AND ] = &(operation_l_and ); @@ -214,12 +214,12 @@ if (_param->_timing[TYPE_TEST ][OPERATION_TEST_L_SFNE ]._latence > 0) _function_execute[TYPE_TEST ][OPERATION_TEST_L_SFNE ] = &(operation_l_sfne ); -// if (_param->_timing[TYPE_MUL ][OPERATION_MUL_L_MUL ]._latence > 0) -// _function_execute[TYPE_MUL ][OPERATION_MUL_L_MUL ] = &(operation_l_mul ); -// if (_param->_timing[TYPE_MUL ][OPERATION_MUL_L_MULU ]._latence > 0) -// _function_execute[TYPE_DIV ][OPERATION_MUL_L_MULU ] = &(operation_l_mulu ); -// if (_param->_timing[TYPE_DIV ][OPERATION_DIV_L_DIV ]._latence > 0) -// _function_execute[TYPE_DIV ][OPERATION_DIV_L_DIV ] = &(operation_l_div ); -// if (_param->_timing[TYPE_DIV ][OPERATION_DIV_L_DIVU ]._latence > 0) -// _function_execute[TYPE_DIV ][OPERATION_DIV_L_DIVU ] = &(operation_l_divu ); + if (_param->_timing[TYPE_MUL ][OPERATION_MUL_L_MUL ]._latence > 0) + _function_execute[TYPE_MUL ][OPERATION_MUL_L_MUL ] = &(operation_l_mul ); + if (_param->_timing[TYPE_MUL ][OPERATION_MUL_L_MULU ]._latence > 0) + _function_execute[TYPE_MUL ][OPERATION_MUL_L_MULU ] = &(operation_l_mulu ); + if (_param->_timing[TYPE_DIV ][OPERATION_DIV_L_DIV ]._latence > 0) + _function_execute[TYPE_DIV ][OPERATION_DIV_L_DIV ] = &(operation_l_div ); + if (_param->_timing[TYPE_DIV ][OPERATION_DIV_L_DIVU ]._latence > 0) + _function_execute[TYPE_DIV ][OPERATION_DIV_L_DIVU ] = &(operation_l_divu ); if (_param->_timing[TYPE_EXTEND ][OPERATION_EXTEND_L_EXTEND_S ]._latence > 0) _function_execute[TYPE_EXTEND ][OPERATION_EXTEND_L_EXTEND_S ] = &(operation_l_extend_s); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h (revision 101) @@ -133,6 +133,6 @@ // Address's Read must be aligned - if ((address & _mask_addr) != 0) - TEST_KO(" Address is not aligned"); +// if ((address & _mask_addr) != 0) +// TEST_KO(" Address is not aligned"); if (context>_nb_context) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp (revision 101) @@ -24,6 +24,6 @@ void Load_store_unit::function_speculative_load_commit_genMealy_dcache (void) { - log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); - log_printf(FUNC,Load_store_unit,FUNCTION,"End"); + log_begin(Load_store_unit,FUNCTION); + log_end (Load_store_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp (revision 101) @@ -24,5 +24,6 @@ void Load_store_unit::function_speculative_load_commit_genMealy_insert (void) { - log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); + log_begin(Load_store_unit,FUNCTION); + log_function(Load_store_unit,FUNCTION,_name.c_str()); // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -52,5 +53,5 @@ PORT_WRITE(out_MEMORY_IN_ACK [i], ack [i]); - log_printf(FUNC,Load_store_unit,FUNCTION,"End"); + log_end(Load_store_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp (revision 101) @@ -24,6 +24,6 @@ void Load_store_unit::function_speculative_load_commit_genMealy_retire (void) { - log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); - log_printf(FUNC,Load_store_unit,FUNCTION,"End"); + log_begin(Load_store_unit,FUNCTION); + log_end (Load_store_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (revision 101) @@ -24,5 +24,6 @@ void Load_store_unit::function_speculative_load_commit_genMoore (void) { - log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); + log_begin(Load_store_unit,FUNCTION); + log_function(Load_store_unit,FUNCTION,_name.c_str()); // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -44,7 +45,7 @@ // Test store and load queue - log_printf(TRACE,Load_store_unit,FUNCTION,"genMoore : Test MEMORY_OUT"); - - log_printf(TRACE,Load_store_unit,FUNCTION," * Load queue"); + log_printf(TRACE,Load_store_unit,FUNCTION," * Test MEMORY_OUT"); + + log_printf(TRACE,Load_store_unit,FUNCTION," * Load queue"); for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++) // for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++) @@ -71,5 +72,6 @@ _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed, _load_queue [internal_MEMORY_OUT_PTR]._access_size); - log_printf(TRACE,Load_store_unit,FUNCTION," * data : %.8x",data_new); + log_printf(TRACE,Load_store_unit,FUNCTION," * data (old) : %.8x",data_old); + log_printf(TRACE,Load_store_unit,FUNCTION," * data (new) : %.8x",data_new); log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata); log_printf(TRACE,Load_store_unit,FUNCTION," * shift : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift); @@ -91,5 +93,5 @@ if (not internal_MEMORY_OUT_VAL) { - log_printf(TRACE,Load_store_unit,FUNCTION," * Store queue"); + log_printf(TRACE,Load_store_unit,FUNCTION," * Store queue"); if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) { @@ -143,5 +145,5 @@ Tdcache_data_t dcache_req_wdata ; - log_printf(TRACE,Load_store_unit,FUNCTION,"genMoore : Test DCACHE_REQ"); + log_printf(TRACE,Load_store_unit,FUNCTION," * Test DCACHE_REQ"); internal_DCACHE_REQ_VAL = 0; @@ -152,5 +154,5 @@ if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE) { - log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue[%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ); + log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ); internal_DCACHE_REQ_VAL = 1; @@ -169,6 +171,11 @@ dcache_req_packet_id = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write); - dcache_req_address = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address & _param->_mask_address_msb; + dcache_req_address = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb; dcache_req_type = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation); + +// log_printf(TRACE,Load_store_unit,FUNCTION," * address : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address); +// log_printf(TRACE,Load_store_unit,FUNCTION," * mask : %.8x",_param->_mask_address_msb); + log_printf(TRACE,Load_store_unit,FUNCTION," * dcache_req_address : %.8x",dcache_req_address); + #ifdef SYSTEMC_VHDL_COMPATIBILITY dcache_req_wdata = 0; @@ -210,5 +217,5 @@ PORT_WRITE(out_DCACHE_REQ_WDATA [0], dcache_req_wdata ); - log_printf(FUNC,Load_store_unit,FUNCTION,"End"); + log_end(Load_store_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (revision 101) @@ -260,4 +260,6 @@ ( internal_MEMORY_IN_ACK == 1)) { + log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_IN [%d]",internal_MEMORY_IN_PORT); + // Test operation : //~~~~~~~~~~~~~~~~~ @@ -440,5 +442,5 @@ (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) { - log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT transaction"); + log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT[0] transaction"); switch (internal_MEMORY_OUT_SELECT_QUEUE) @@ -498,5 +500,5 @@ (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1)) { - log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ"); + log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ[0]"); switch (internal_DCACHE_REQ_SELECT_QUEUE) @@ -602,5 +604,5 @@ ( internal_DCACHE_RSP_ACK == 1)) { - log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_RSP"); + log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_RSP [0]"); // don't use context_id : because there are one queue for all thread @@ -610,5 +612,7 @@ Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR [0]); - log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id); + log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d" , packet_id); + log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x", rdata); + log_printf(TRACE,Load_store_unit,FUNCTION," * error : %d" , error); if (DCACHE_RSP_IS_LOAD(packet_id) == 1) @@ -623,5 +627,6 @@ throw ErrorMorpheo(_("Receive of respons, but the corresponding operation don't wait a respons.")); #endif - + + _load_queue [packet_id]._rdata = rdata; if (error != DCACHE_ERROR_NONE) @@ -639,6 +644,5 @@ // FIXME : convention : if bus error, the cache return the fautive address ! // But, the load's address is aligned ! - _load_queue [packet_id]._rdata = rdata; - + switch (_load_queue [packet_id]._state) { @@ -695,5 +699,5 @@ uint32_t j = (*_speculative_access_queue_control)[i]; - log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.6d, %.2d, %s", + log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.4d, %.2d, %s", j, _speculative_access_queue[j]._context_id , @@ -719,5 +723,5 @@ uint32_t j = i; - log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.6d, %.2d, %s", + log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s", j, _load_queue[j]._context_id , Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl.cpp (revision 101) @@ -33,5 +33,7 @@ (_param->_size_queue, _param->_size_internal_queue, - 0 + 0, + false, + false ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h (revision 101) @@ -14,5 +14,5 @@ #include -#include +#include #include "Common/include/ToString.h" #include "Common/include/Debug.h" @@ -99,5 +99,5 @@ // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - private : std::queue * _queue; + private : std::list * _queue; // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ private : Tcontrol_t internal_EXECUTE_QUEUE_IN_ACK ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp (revision 101) @@ -96,5 +96,5 @@ // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - _queue = new std::queue; + _queue = new std::list; #ifdef POSITION Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_deallocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_deallocation.cpp (revision 101) @@ -72,5 +72,5 @@ { delete _queue->front(); - _queue->pop(); + _queue->pop_front(); } delete _queue; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_genMoore.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_genMoore.cpp (revision 101) @@ -23,5 +23,6 @@ void Execute_queue::genMoore (void) { - log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); + log_begin(Execute_queue,FUNCTION); + log_function(Execute_queue,FUNCTION,_name.c_str()); // -----[ Interface "execute_queue_in" ]-------------------------------- @@ -59,5 +60,5 @@ } - log_printf(FUNC,Execute_queue,FUNCTION,"End"); + log_end(Execute_queue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_transition.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_transition.cpp (revision 101) @@ -23,5 +23,6 @@ void Execute_queue::transition (void) { - log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); + log_begin(Execute_queue,FUNCTION); + log_function(Execute_queue,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) @@ -32,6 +33,5 @@ // > 2) flush all slot in one cycle - while (_queue->empty() == false) - _queue->pop(); + _queue->clear(); } else @@ -53,5 +53,5 @@ PORT_READ(in_EXECUTE_QUEUE_IN_DATA )); - _queue->push(entry); + _queue->push_back(entry); } @@ -60,5 +60,5 @@ { delete _queue->front(); - _queue->pop(); + _queue->pop_front(); } } @@ -69,4 +69,31 @@ #endif +#if DEBUG_Execute_queue and (DEBUG >= DEBUG_TRACE) + log_printf(TRACE,Execute_queue,FUNCTION," * Dump Execute_queue"); + { + uint32_t i=0; + for (std::list::iterator it=_queue->begin(); + it!=_queue->end(); + ++it) + { + log_printf(TRACE,Execute_queue,FUNCTION," [%d] %.2d %.2d %.2d, %.4d, %.1d, %.2d %.1d, %.8x %.8x", + i, + (*it)->_context_id , + (*it)->_front_end_id , + (*it)->_ooo_engine_id, + (*it)->_packet_id , + //(*it)->_operation , + //(*it)->_type , + (*it)->_flags , + (*it)->_exception , + (*it)->_no_sequence , + (*it)->_address , + (*it)->_data + ); + i++; + } + } +#endif + #if defined(STATISTICS) or defined(VHDL_TESTBENCH) @@ -74,5 +101,5 @@ #endif - log_printf(FUNC,Execute_queue,FUNCTION,"End"); + log_end(Execute_queue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl.cpp (revision 101) @@ -35,5 +35,7 @@ (_param->_size_queue, _param->_size_internal_queue, - 0 + 0, + false, + false ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp (revision 101) @@ -23,5 +23,6 @@ void Write_queue::genMoore (void) { - log_printf(FUNC,Write_queue,FUNCTION,"Begin"); + log_begin(Write_queue,FUNCTION); + log_function(Write_queue,FUNCTION,_name.c_str()); // -----[ Interface "Write_queue_in" ]-------------------------------- @@ -109,5 +110,5 @@ } } - log_printf(FUNC,Write_queue,FUNCTION,"End"); + log_end(Write_queue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp (revision 101) @@ -24,5 +24,6 @@ void Write_queue::transition (void) { - log_printf(FUNC,Write_queue,FUNCTION,"Begin"); + log_begin(Write_queue,FUNCTION); + log_function(Write_queue,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) @@ -87,9 +88,40 @@ #endif +#if DEBUG_Write_queue and (DEBUG >= DEBUG_TRACE) + log_printf(TRACE,Write_queue,FUNCTION," * Dump Write_queue"); + { + uint32_t i=0; + + for (std::list::iterator it=_queue->begin(); + it!=_queue->end(); + ++it) + { + log_printf(TRACE,Write_queue,FUNCTION," [%d] %.2d %.2d %.2d, %.4d, %.1d %.4d %.8x, %.1d %.4d %.1d, %.2d %.1d, %.8x", + i, + (*it)->_context_id , + (*it)->_front_end_id , + (*it)->_ooo_engine_id, + (*it)->_packet_id , + //(*it)->_operation , + //(*it)->_type , + (*it)->_write_rd , + (*it)->_num_reg_rd , + (*it)->_data_rd , + (*it)->_write_re , + (*it)->_num_reg_re , + (*it)->_data_re , + (*it)->_exception , + (*it)->_no_sequence , + (*it)->_address ); + i++; + } + } +#endif + #if defined(STATISTICS) or defined(VHDL_TESTBENCH) end_cycle (); #endif - log_printf(FUNC,Write_queue,FUNCTION,"End"); + log_end(Write_queue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Parameters.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Parameters.cpp (revision 101) @@ -104,5 +104,6 @@ 0, nb_general_register[i], - 1); + 1, + "1"); __param_spr [i] = new morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters @@ -122,5 +123,6 @@ 0, nb_special_register[i], - 1); + 1, + "1"); _param_gpr [i] = new morpheo::behavioural::generic::registerfile::Parameters (__param_gpr [i]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 101) @@ -213,4 +213,17 @@ // Initialisation + const bool test1 = true; + const bool test2 = true; + const bool test3 = true; + const bool test4 = true; + const bool test5 = true; + const bool test6 = true; + const bool test7 = true; + const bool test8 = true; + const bool test9 = true; + const bool test10 = true; + const bool test11 = true; + const bool test12 = true; + const uint32_t seed = 0; //const uint32_t seed = static_cast(time(NULL)); @@ -264,5 +277,5 @@ uint32_t context = rand()%_param->_nb_context; - if (1) + if (test1) { SC_START(3); @@ -285,13 +298,25 @@ TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); - do - { - in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event); - - SC_START(1); - } - while (not ( in_DECOD_EVENT_VAL [port]->read() and - out_DECOD_EVENT_ACK [port]->read())); - in_DECOD_EVENT_VAL [port]->write(0); + in_DECOD_EVENT_VAL [port]->write(1); + + SC_START(0); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0); + + SC_START(1); + + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(0); + + LABEL("msync (send decod)"); + SC_START(0); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1); + + SC_START(1); + + in_DECOD_EVENT_VAL [port]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(1); LABEL("msync (wait end)"); @@ -300,102 +325,16 @@ SC_START(3); - in_NB_INST_DECOD_ALL [context]->write(0); - in_NB_INST_COMMIT_ALL [context]->write(1); - in_NB_INST_COMMIT_MEM [context]->write(0); - - SC_START(1); - - LABEL("msync (send decod)"); - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); - - SC_START(3); - - in_NB_INST_DECOD_ALL [context]->write(1); - SC_START(1); - - LABEL("msync (wait end)"); - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); - in_NB_INST_DECOD_ALL [context]->write(0); - in_NB_INST_COMMIT_MEM [context]->write(1); - - SC_START(3); - - in_NB_INST_COMMIT_MEM [context]->write(0); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); + in_NB_INST_COMMIT_ALL [context]->write(0); + SC_START(1); TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); } - if (1) + if (test2) { SC_START(3); - + LABEL("psync (begin)"); - in_NB_INST_DECOD_ALL [context]->write(1); - in_NB_INST_COMMIT_ALL [context]->write(1); - in_NB_INST_COMMIT_MEM [context]->write(1); - - uint32_t port = rand()%_param->_nb_decod_unit; - - in_DECOD_EVENT_CONTEXT_ID [port]->write(context); - in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0); - in_DECOD_EVENT_ADDRESS [port]->write(0x200); - in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe); - if (_param->_have_port_depth) - in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); - in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC); - - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); - - do - { - in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event); - - SC_START(1); - } - while (not ( in_DECOD_EVENT_VAL [port]->read() and - out_DECOD_EVENT_ACK [port]->read())); - in_DECOD_EVENT_VAL [port]->write(0); - - LABEL("psync (wait end)"); - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); - - SC_START(3); - - in_NB_INST_DECOD_ALL [context]->write(0); - in_NB_INST_COMMIT_ALL [context]->write(0); - in_NB_INST_COMMIT_MEM [context]->write(0); - - SC_START(1); - - bool find = false; - do - { - in_EVENT_ACK [context]->write(rand()%percent_transaction_event); - - SC_START(0); - - if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read()) - { - TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201); - TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe); - TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0); - TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0); - - find = true; - } - - SC_START(1); - } - while (not find); - - in_EVENT_ACK [context]->write(0); - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); - } - - if (1) - { - SC_START(3); - - LABEL("csync (begin)"); in_NB_INST_DECOD_ALL [context]->write(1); in_NB_INST_COMMIT_ALL [context]->write(1); @@ -410,27 +349,38 @@ if (_param->_have_port_depth) in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); - in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC); - - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); - - do - { - in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event); - - SC_START(1); - } - while (not ( in_DECOD_EVENT_VAL [port]->read() and - out_DECOD_EVENT_ACK [port]->read())); - in_DECOD_EVENT_VAL [port]->write(0); - - LABEL("csync (wait end)"); - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); - - SC_START(3); - + in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC); + + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + + in_DECOD_EVENT_VAL [port]->write(1); + + SC_START(0); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0); + + SC_START(1); + in_NB_INST_DECOD_ALL [context]->write(0); in_NB_INST_COMMIT_ALL [context]->write(0); in_NB_INST_COMMIT_MEM [context]->write(0); - + + LABEL("psync (send decod)"); + SC_START(0); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1); + + SC_START(1); + + in_DECOD_EVENT_VAL [port]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(1); + + LABEL("psync (wait end)"); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); + + SC_START(3); + + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); + in_NB_INST_COMMIT_ALL [context]->write(0); + SC_START(1); @@ -448,19 +398,21 @@ TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0); TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0); - - find = true; - } - - SC_START(1); - } - while (not find); + + find = true; + } + + SC_START(1); + } + while (not find); + in_EVENT_ACK [context]->write(0); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); } - if (1) + if (test3) { SC_START(3); - LABEL("spr (begin)"); + LABEL("csync (begin)"); in_NB_INST_DECOD_ALL [context]->write(1); in_NB_INST_COMMIT_ALL [context]->write(1); @@ -471,6 +423,85 @@ in_DECOD_EVENT_CONTEXT_ID [port]->write(context); in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0); - in_DECOD_EVENT_ADDRESS [port]->write(0x100); - in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef); + in_DECOD_EVENT_ADDRESS [port]->write(0x300); + in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdead0300); + if (_param->_have_port_depth) + in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); + in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC); + + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + + in_DECOD_EVENT_VAL [port]->write(1); + + SC_START(0); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0); + + SC_START(1); + + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(0); + + LABEL("csync (send decod)"); + SC_START(0); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1); + + SC_START(1); + + in_DECOD_EVENT_VAL [port]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(1); + + LABEL("csync (wait end)"); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); + + SC_START(3); + + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); + in_NB_INST_COMMIT_ALL [context]->write(0); + + SC_START(1); + + bool find = false; + do + { + in_EVENT_ACK [context]->write(rand()%percent_transaction_event); + + SC_START(0); + + if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read()) + { + TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x301); + TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdead0300); + TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0); + TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0); + + find = true; + } + + SC_START(1); + } + while (not find); + + in_EVENT_ACK [context]->write(0); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + + } + + if (test4) + { + SC_START(3); + + LABEL("spr_access (begin)"); + in_NB_INST_DECOD_ALL [context]->write(1); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(1); + + uint32_t port = rand()%_param->_nb_decod_unit; + + in_DECOD_EVENT_CONTEXT_ID [port]->write(context); + in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0); + in_DECOD_EVENT_ADDRESS [port]->write(0x400); + in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdead0400); if (_param->_have_port_depth) in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); @@ -479,46 +510,39 @@ TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); - do - { - in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event); - - SC_START(1); - } - while (not ( in_DECOD_EVENT_VAL [port]->read() and - out_DECOD_EVENT_ACK [port]->read())); - in_DECOD_EVENT_VAL [port]->write(0); - - LABEL("spr (wait end)"); - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); - - SC_START(3); - + in_DECOD_EVENT_VAL [port]->write(1); + + SC_START(0); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0); + + SC_START(1); + in_NB_INST_DECOD_ALL [context]->write(0); in_NB_INST_COMMIT_ALL [context]->write(0); in_NB_INST_COMMIT_MEM [context]->write(0); - - SC_START(1); - - LABEL("spr (send decod)"); - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); - - SC_START(3); - - in_NB_INST_DECOD_ALL [context]->write(1); - SC_START(1); - - LABEL("spr (wait end)"); - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); - in_NB_INST_DECOD_ALL [context]->write(0); - in_NB_INST_COMMIT_ALL [context]->write(1); - - SC_START(3); - - in_NB_INST_COMMIT_ALL [context]->write(0); + + LABEL("spr_access (send decod)"); + SC_START(0); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1); + + SC_START(1); + + in_DECOD_EVENT_VAL [port]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(1); + + LABEL("spr_access (wait end)"); + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); + + SC_START(3); + + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); + in_NB_INST_COMMIT_ALL [context]->write(0); + SC_START(1); TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); } - if (1) + if (test5) { SC_START(3); @@ -610,5 +634,5 @@ } - if (1) + if (test6) { SC_START(3); @@ -697,5 +721,5 @@ } - if (1) + if (test7) { SC_START(3); @@ -791,5 +815,5 @@ } - if (1) + if (test8) { SC_START(3); @@ -885,5 +909,5 @@ } - if (1) + if (test9) { SC_START(3); @@ -979,5 +1003,5 @@ } - if (1) + if (test10) { SC_START(3); @@ -1073,5 +1097,5 @@ } - if (1) + if (test11) { SC_START(3); @@ -1167,5 +1191,5 @@ } - if (1) + if (test12) { SC_START(3); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h (revision 101) @@ -197,4 +197,5 @@ public : void transition (void); public : void genMoore (void); + public : void genMealy_decod_event (void); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h (revision 101) @@ -29,17 +29,17 @@ CONTEXT_STATE_KO_EXCEP_ADDR , // update address manager CONTEXT_STATE_KO_EXCEP_SPR , // update spr (epc, esr, sr[DSX]) - CONTEXT_STATE_KO_MISS , // wait end of event (miss (branch, load)) CONTEXT_STATE_KO_MISS_ADDR , // update address manager - CONTEXT_STATE_KO_MSYNC , // wait completion of all memory operation - CONTEXT_STATE_KO_MSYNC_ISSUE , // issue msync operation + CONTEXT_STATE_KO_MISS_WAITEND , // wait end of event (miss (branch, load)) +// CONTEXT_STATE_KO_MSYNC , // wait completion of all memory operation +// CONTEXT_STATE_KO_MSYNC_ISSUE , // issue msync operation CONTEXT_STATE_KO_MSYNC_EXEC , // wait completion of msync operation - CONTEXT_STATE_KO_PSYNC , // wait completion of all operation and after flush pipeline +// CONTEXT_STATE_KO_PSYNC , // wait completion of all operation and after flush pipeline CONTEXT_STATE_KO_PSYNC_FLUSH , // wait completion of all CONTEXT_STATE_KO_PSYNC_ADDR , // wait completion of all - CONTEXT_STATE_KO_CSYNC , // wait completion of all operation and after flush pipeline and flush ALL units (MMU, cache ...) +// CONTEXT_STATE_KO_CSYNC , // wait completion of all operation and after flush pipeline and flush ALL units (MMU, cache ...) CONTEXT_STATE_KO_CSYNC_FLUSH , CONTEXT_STATE_KO_CSYNC_ADDR , - CONTEXT_STATE_KO_SPR , // wait completion of all operation - CONTEXT_STATE_KO_SPR_ISSUE , // issue spr's access +// CONTEXT_STATE_KO_SPR , // wait completion of all operation +// CONTEXT_STATE_KO_SPR_ISSUE , // issue spr's access CONTEXT_STATE_KO_SPR_EXEC // wait completion of all operation (spr access) } context_state_t; @@ -60,17 +60,17 @@ case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_ADDR : return "context_state_ko_excep_addr" ; break; case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_SPR : return "context_state_ko_excep_spr" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS : return "context_state_ko_miss" ; break; case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_ADDR : return "context_state_ko_miss_addr" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC : return "context_state_ko_msync" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE : return "context_state_ko_msync_issue" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_WAITEND : return "context_state_ko_miss_waitend"; break; +// case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC : return "context_state_ko_msync" ; break; +// case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE : return "context_state_ko_msync_issue" ; break; case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_EXEC : return "context_state_ko_msync_exec" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC : return "context_state_ko_psync" ; break; +// case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC : return "context_state_ko_psync" ; break; case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_FLUSH : return "context_state_ko_psync_flush" ; break; case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_ADDR : return "context_state_ko_psync_addr" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC : return "context_state_ko_csync" ; break; +// case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC : return "context_state_ko_csync" ; break; case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_FLUSH : return "context_state_ko_csync_flush" ; break; case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_ADDR : return "context_state_ko_csync_addr" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR : return "context_state_ko_spr" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_ISSUE : return "context_state_ko_spr_issue" ; break; +// case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR : return "context_state_ko_spr" ; break; +// case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_ISSUE : return "context_state_ko_spr_issue" ; break; case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_EXEC : return "context_state_ko_spr_exec" ; break; default : return "" ; break; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State.cpp (revision 101) @@ -82,9 +82,9 @@ } - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - { - internal_DECOD_EVENT_ACK [i] = 1; - PORT_WRITE(out_DECOD_EVENT_ACK [i], internal_DECOD_EVENT_ACK [i]); - } +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// { +// internal_DECOD_EVENT_ACK [i] = 1; +// PORT_WRITE(out_DECOD_EVENT_ACK [i], internal_DECOD_EVENT_ACK [i]); +// } internal_COMMIT_EVENT_ACK = 1; @@ -112,4 +112,27 @@ dont_initialize (); sensitive << (*(in_CLOCK)).neg(); // use internal register + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Context_State,FUNCTION,_("Method - genMealy_decod_event")); + + SC_METHOD (genMealy_decod_event); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // use internal register + for (uint32_t i=0; i<_param->_nb_decod_unit; ++i) + { + sensitive << (*(in_DECOD_EVENT_VAL [i])) // not necessary + << (*(in_DECOD_EVENT_TYPE [i])); + if (_param->_have_port_context_id) + sensitive << (*(in_DECOD_EVENT_CONTEXT_ID [i])); + } + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + sensitive << (*(in_NB_INST_DECOD_ALL [i])) + << (*(in_NB_INST_COMMIT_ALL [i])) + << (*(in_NB_INST_COMMIT_MEM [i])); + } # ifdef SYSTEMCASS_SPECIFIC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp (revision 101) @@ -105,7 +105,8 @@ context_state_t state = reg_STATE [i]; - PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], ((state==CONTEXT_STATE_OK ) or - (state==CONTEXT_STATE_KO_MSYNC_ISSUE) or - (state==CONTEXT_STATE_KO_SPR_ISSUE ))); +// PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], ((state==CONTEXT_STATE_OK ) or +// (state==CONTEXT_STATE_KO_MSYNC_ISSUE) or +// (state==CONTEXT_STATE_KO_SPR_ISSUE ))); + PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], (state==CONTEXT_STATE_OK)); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (revision 101) @@ -35,4 +35,145 @@ { // ------------------------------------------------------------------- + // -----[ next state ]------------------------------------------------ + // ------------------------------------------------------------------- + for (uint32_t i=0; i<_param->_nb_context; i++) + { +// uint32_t x = _param->_link_context_to_decod_unit [i]; + + Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); +// Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); + + context_state_t state = reg_STATE [i]; + + switch (state) + { + case CONTEXT_STATE_OK : + { + // nothing, wait an event + break; + } + case CONTEXT_STATE_KO_EXCEP : + { + // Wait end of all instruction + if (inst_all == 0) + state = CONTEXT_STATE_KO_EXCEP_ADDR; + break; + } + case CONTEXT_STATE_KO_EXCEP_ADDR : + { + // nothing, wait the update of internal register (pc) + break; + } + case CONTEXT_STATE_KO_MISS_WAITEND : + { + // Wait end of all instruction + if (inst_all == 0) + +// state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) + state = CONTEXT_STATE_KO_MISS_ADDR; + break; + } + case CONTEXT_STATE_KO_EXCEP_SPR : + { + // nothing, wait the update of internal register (epcr, eear, sr, esr) + break; + } + case CONTEXT_STATE_KO_MISS_ADDR : + { + // nothing, wait the update of internal register (pc) + break; + } +// case CONTEXT_STATE_KO_PSYNC : +// { +// // Wait end of all instruction +// if (inst_all == 0) +// state = CONTEXT_STATE_KO_PSYNC_FLUSH; +// break; +// } + case CONTEXT_STATE_KO_PSYNC_FLUSH : + { + // nothing, wait end of flush (ifetch) + if (inst_all == 0) +// state = CONTEXT_STATE_KO_PSYNC_ADDR; + state = CONTEXT_STATE_OK; + + break; + } + case CONTEXT_STATE_KO_PSYNC_ADDR : + { + // nothing, wait the pc write + break; + } +// case CONTEXT_STATE_KO_CSYNC : +// { +// // Wait end of all instruction +// if (inst_all == 0) +// state = CONTEXT_STATE_KO_CSYNC_FLUSH; +// break; +// } + case CONTEXT_STATE_KO_CSYNC_FLUSH : + { + // nothing, wait end of flush (all internal structure) + if (inst_all == 0) + state = CONTEXT_STATE_KO_CSYNC_ADDR; + break; + } + case CONTEXT_STATE_KO_CSYNC_ADDR : + { + // nothing, wait the pc write + break; + } +// case CONTEXT_STATE_KO_MSYNC : +// { +// // Wait end of memory instruction +// if (inst_mem == 0) +// state = CONTEXT_STATE_KO_MSYNC_ISSUE; +// break; +// } +// case CONTEXT_STATE_KO_MSYNC_ISSUE : +// { +// // Wait the msync issue +// if (inst_mem != 0) +// state = CONTEXT_STATE_KO_MSYNC_EXEC; +// break; +// } + case CONTEXT_STATE_KO_MSYNC_EXEC : + { + // Wait the end of msync + if (inst_all == 0) + state = CONTEXT_STATE_OK; + break; + } +// case CONTEXT_STATE_KO_SPR : +// { +// // Wait end of all instruction +// if (inst_all == 0) +// state = CONTEXT_STATE_KO_SPR_ISSUE; +// break; +// } +// case CONTEXT_STATE_KO_SPR_ISSUE : +// { +// // Wait the spr_access issue +// if (inst_all != 0) +// state = CONTEXT_STATE_KO_SPR_EXEC; +// break; +// } + case CONTEXT_STATE_KO_SPR_EXEC : + { + // Wait the spr_access execution + if (inst_all == 0) + state = CONTEXT_STATE_OK; + break; + } + + default : + { + throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); + } + } + reg_STATE [i] = state; + } + + // ------------------------------------------------------------------- // -----[ BRANCH_EVENT ]---------------------------------------------- // ------------------------------------------------------------------- @@ -57,5 +198,5 @@ // priority : miss > excep > spr/sync - uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == EVENT_TYPE_EXCEPTION)?1:0); + uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); uint8_t priority1 = 2; // miss @@ -71,5 +212,6 @@ { Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); - reg_STATE [i] = CONTEXT_STATE_KO_MISS; +// reg_STATE [i] = CONTEXT_STATE_KO_MISS_ADDR; + reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next @@ -107,5 +249,5 @@ // miss > excep > spr/sync - uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); + uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; @@ -120,4 +262,6 @@ if (is_valid) { + log_printf(TRACE,Context_State,FUNCTION," * is_valid"); + // decod : // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) @@ -130,4 +274,6 @@ case EVENT_TYPE_EXCEPTION : { + log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION"); + state_next = CONTEXT_STATE_KO_EXCEP; @@ -136,32 +282,44 @@ case EVENT_TYPE_SPR_ACCESS : { - state_next = CONTEXT_STATE_KO_SPR ; + log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS"); + +// state_next = CONTEXT_STATE_KO_SPR ; + state_next = CONTEXT_STATE_KO_SPR_EXEC; address++; // take next address - if (is_delay_slot) - throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); +// if (is_delay_slot) +// throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); break; } case EVENT_TYPE_MSYNC : { - state_next = CONTEXT_STATE_KO_MSYNC; + log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC"); + +// state_next = CONTEXT_STATE_KO_MSYNC; + state_next = CONTEXT_STATE_KO_MSYNC_EXEC; address++; // take next address - if (is_delay_slot) - throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); +// if (is_delay_slot) +// throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n"); break; } case EVENT_TYPE_PSYNC : { - state_next = CONTEXT_STATE_KO_PSYNC; + log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC"); + +// state_next = CONTEXT_STATE_KO_PSYNC; + state_next = CONTEXT_STATE_KO_PSYNC_FLUSH; address++; // take next address if (is_delay_slot) - throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); + throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n"); break; } case EVENT_TYPE_CSYNC : { - state_next = CONTEXT_STATE_KO_CSYNC; + log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC"); + +// state_next = CONTEXT_STATE_KO_CSYNC; + state_next = CONTEXT_STATE_KO_CSYNC_FLUSH; address++; // take next address if (is_delay_slot) - throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); + throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n"); break; } @@ -210,5 +368,5 @@ // miss > excep > spr/sync - uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); + uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); uint8_t priority1 = 1; // exception @@ -277,5 +435,5 @@ // // miss > excep > spr/sync -// uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); +// uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); // uint8_t priority1 = 2; // miss @@ -323,4 +481,8 @@ } case CONTEXT_STATE_KO_MISS_ADDR : +// { +// reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) +// break; +// } case CONTEXT_STATE_KO_PSYNC_ADDR : case CONTEXT_STATE_KO_CSYNC_ADDR : @@ -357,139 +519,4 @@ reg_STATE [i] = CONTEXT_STATE_OK; } - - // ------------------------------------------------------------------- - // -----[ next state ]------------------------------------------------ - // ------------------------------------------------------------------- - for (uint32_t i=0; i<_param->_nb_context; i++) - { -// uint32_t x = _param->_link_context_to_decod_unit [i]; - - Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); - Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); - - context_state_t state = reg_STATE [i]; - - switch (state) - { - case CONTEXT_STATE_OK : - { - // nothing, wait an event - break; - } - case CONTEXT_STATE_KO_EXCEP : - { - // Wait end of all instruction - if (inst_all == 0) - state = CONTEXT_STATE_KO_EXCEP_ADDR; - break; - } - case CONTEXT_STATE_KO_MISS : - { - // Wait end of all instruction - if (inst_all == 0) - state = CONTEXT_STATE_KO_MISS_ADDR; - break; - } - case CONTEXT_STATE_KO_EXCEP_ADDR : - { - // nothing, wait the update of internal register (pc) - break; - } - case CONTEXT_STATE_KO_EXCEP_SPR : - { - // nothing, wait the update of internal register (epcr, eear, sr, esr) - break; - } - case CONTEXT_STATE_KO_MISS_ADDR : - { - // nothing, wait the update of internal register (pc) - break; - } - case CONTEXT_STATE_KO_PSYNC : - { - // Wait end of all instruction - if (inst_all == 0) -// state = CONTEXT_STATE_KO_PSYNC_FLUSH; - state = CONTEXT_STATE_KO_PSYNC_ADDR ; - break; - } -// case CONTEXT_STATE_KO_PSYNC_FLUSH : -// { -// // nothing, wait end of flush (ifetch) -// break; -// } - case CONTEXT_STATE_KO_PSYNC_ADDR : - { - // nothing, wait the pc write - break; - } - case CONTEXT_STATE_KO_CSYNC : - { - // Wait end of all instruction - if (inst_all == 0) - state = CONTEXT_STATE_KO_CSYNC_ADDR ; -// state = CONTEXT_STATE_KO_CSYNC_FLUSH; - break; - } -// case CONTEXT_STATE_KO_CSYNC_FLUSH : -// { -// // nothing, wait end of flush (all internal structure) -// break; -// } - case CONTEXT_STATE_KO_CSYNC_ADDR : - { - // nothing, wait the pc write - break; - } - case CONTEXT_STATE_KO_MSYNC : - { - // Wait end of memory instruction - if (inst_mem == 0) - state = CONTEXT_STATE_KO_MSYNC_ISSUE; - break; - } - case CONTEXT_STATE_KO_MSYNC_ISSUE : - { - // Wait the msync issue - if (inst_mem != 0) - state = CONTEXT_STATE_KO_MSYNC_EXEC; - break; - } - case CONTEXT_STATE_KO_MSYNC_EXEC : - { - // Wait the end of msync - if (inst_mem == 0) - state = CONTEXT_STATE_OK; - break; - } - case CONTEXT_STATE_KO_SPR : - { - // Wait end of all instruction - if (inst_all == 0) - state = CONTEXT_STATE_KO_SPR_ISSUE; - break; - } - case CONTEXT_STATE_KO_SPR_ISSUE : - { - // Wait the spr_access issue - if (inst_all != 0) - state = CONTEXT_STATE_KO_SPR_EXEC; - break; - } - case CONTEXT_STATE_KO_SPR_EXEC : - { - // Wait the spr_access execution - if (inst_all == 0) - state = CONTEXT_STATE_OK; - break; - } - - default : - { - throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); - } - } - reg_STATE [i] = state; - } for (uint32_t i=0; i<_param->_nb_context; ++i) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp (revision 101) @@ -29,7 +29,12 @@ void instruction_decod (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod"," * instruction : decod"); + // instruction_decod_type_0 (inst,param); uint32_t opcod = range(inst->_instruction,31,26); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[ 0][opcod]) (inst,param); } @@ -43,5 +48,10 @@ void instruction_decod_type_1 (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod_type_1"," * instruction : decod type_1"); + uint32_t opcod = range(inst->_instruction, 7, 0); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[ 1][opcod]) (inst,param); } @@ -49,5 +59,10 @@ void instruction_decod_type_2 (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod_type_2"," * instruction : decod type_2"); + uint32_t opcod = range(inst->_instruction, 7, 0); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[ 2][opcod]) (inst,param); } @@ -55,6 +70,11 @@ void instruction_decod_type_3 (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod_type_3"," * instruction : decod type_3"); + uint32_t opcod = ((range(inst->_instruction, 9, 8)<<4) | (range(inst->_instruction, 3, 0))); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[ 3][opcod]) (inst,param); } @@ -62,5 +82,10 @@ void instruction_decod_type_4 (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod_type_4"," * instruction : decod type_4"); + uint32_t opcod = range(inst->_instruction,25,21); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[ 4][opcod]) (inst,param); } @@ -68,5 +93,10 @@ void instruction_decod_type_5 (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod_type_5"," * instruction : decod type_5"); + uint32_t opcod = range(inst->_instruction,25,21); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[ 5][opcod]) (inst,param); } @@ -74,5 +104,10 @@ void instruction_decod_type_6 (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod_type_6"," * instruction : decod type_6"); + uint32_t opcod = range(inst->_instruction, 7, 6); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[ 6][opcod]) (inst,param); } @@ -80,5 +115,10 @@ void instruction_decod_type_7 (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod_type_7"," * instruction : decod type_7"); + uint32_t opcod = range(inst->_instruction, 3, 0); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[ 7][opcod]) (inst,param); } @@ -86,5 +126,10 @@ void instruction_decod_type_8 (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod_type_8"," * instruction : decod type_8"); + uint32_t opcod = range(inst->_instruction,16,16); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[ 8][opcod]) (inst,param); } @@ -92,5 +137,10 @@ void instruction_decod_type_9 (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod_type_9"," * instruction : decod type_9"); + uint32_t opcod = range(inst->_instruction,25,23); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[ 9][opcod]) (inst,param); } @@ -98,5 +148,10 @@ void instruction_decod_type_10 (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod_type_10"," * instruction : decod type_10"); + uint32_t opcod = range(inst->_instruction,25,24); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[10][opcod]) (inst,param); } @@ -104,5 +159,10 @@ void instruction_decod_type_11 (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod_type_11"," * instruction : decod type_11"); + uint32_t opcod = range(inst->_instruction, 7, 6); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[11][opcod]) (inst,param); } @@ -110,5 +170,10 @@ void instruction_decod_type_12 (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod_type_12"," * instruction : decod type_12"); + uint32_t opcod = range(inst->_instruction, 7, 6); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[12][opcod]) (inst,param); } @@ -116,5 +181,10 @@ void instruction_decod_type_13 (decod_instruction_t * inst, decod_param_t * param) { + log_printf(TRACE,Decod,"instruction_decod_type_13"," * instruction : decod type_13"); + uint32_t opcod = range(inst->_instruction, 7, 6); + + log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod); + (* param->_function_decod[13][opcod]) (inst,param); } @@ -122,5 +192,7 @@ void instruction_illegal (decod_instruction_t * inst, decod_param_t * param) { - log_printf(TRACE,Decod,"instruction_illegal","instruction_illegal"); + log_printf(TRACE,Decod,"instruction_illegal"," * instruction : illegal"); + + msgWarning(_("Instruction \"%.8x\" at address \"%.8x\" is illegal.\n"),inst->_instruction,inst->_address); inst->_exception_use = EXCEPTION_USE_ILLEGAL_INSTRUCTION; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h (revision 101) @@ -156,5 +156,5 @@ 0xe1e4f801,x,y,z, BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0,0x0, - 0,TYPE_ALU,OPERATION_ALU_L_ADD,false, + 0,TYPE_ALU,OPERATION_ALU_L_ADDC,false, 0,0x00000000,1, 4,1,31,1,SPR_LOGIC_SR_CY_OV,1,15,1,SPR_LOGIC_SR_CY_OV, EXCEPTION_USE_RANGE,EVENT_TYPE_NONE)); @@ -192,5 +192,5 @@ 0xa0ecffff,x,y,z, BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0, - 0,TYPE_ALU,OPERATION_ALU_L_ADD,false, + 0,TYPE_ALU,OPERATION_ALU_L_ADDC,false, 1,0xffffffff,1,12,0, 0,1,SPR_LOGIC_SR_CY_OV,1,7 ,1,SPR_LOGIC_SR_CY_OV, EXCEPTION_USE_RANGE,EVENT_TYPE_NONE)); @@ -201,5 +201,5 @@ 0xa1110000,x,y,z, BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0, - 0,TYPE_ALU,OPERATION_ALU_L_ADD,false, + 0,TYPE_ALU,OPERATION_ALU_L_ADDC,false, 1,0x00000000,1,17,0, 0,1,SPR_LOGIC_SR_CY_OV,1,8 ,1,SPR_LOGIC_SR_CY_OV, EXCEPTION_USE_RANGE,EVENT_TYPE_NONE)); @@ -210,5 +210,5 @@ 0xa2a707bd,x,y,z, BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0, - 0,TYPE_ALU,OPERATION_ALU_L_ADD,false, + 0,TYPE_ALU,OPERATION_ALU_L_ADDC,false, 1,0x000007bd,1, 7,0, 0,1,SPR_LOGIC_SR_CY_OV,1,21,1,SPR_LOGIC_SR_CY_OV, EXCEPTION_USE_RANGE,EVENT_TYPE_NONE)); @@ -358,5 +358,5 @@ 0x23000000,x,y,z, BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0, - 0,TYPE_SPECIAL,OPERATION_SPECIAL_L_CSYNC,false, + 0,TYPE_MEMORY,OPERATION_MEMORY_SYNCHRONIZATION,false, 0,0 ,0,0 ,0,0 ,0,0 ,0,0 ,0,0 , EXCEPTION_USE_NONE,EVENT_TYPE_CSYNC)); @@ -498,5 +498,5 @@ BRANCH_STATE_NONE,0,BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK,1, z, // branch_address_dest can be determined if BRANCH_STATE != NONE (also : previous prediction) 0,TYPE_BRANCH,OPERATION_BRANCH_L_JALR,false, - 0,0 ,0,0 ,1,20,0,0,1,9 ,0,0, + 1,z+1,0,0 ,1,20,0,0,1,9 ,0,0, EXCEPTION_USE_NONE,EVENT_TYPE_NONE)); SEQ; @@ -605,5 +605,5 @@ 0x22000000,x,y,z, 0,0,0,0,0,0, - TYPE_SPECIAL,OPERATION_SPECIAL_L_MSYNC,false, + TYPE_MEMORY,OPERATION_MEMORY_SYNCHRONIZATION,false, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, EXCEPTION_USE_NONE,EVENT_TYPE_MSYNC)); @@ -713,5 +713,5 @@ 0x22800000,x,y,z, 0,0,0,0,0,0, - TYPE_SPECIAL,OPERATION_SPECIAL_L_PSYNC,false, + TYPE_MEMORY,OPERATION_MEMORY_SYNCHRONIZATION,false, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, EXCEPTION_USE_NONE,EVENT_TYPE_PSYNC)); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp (revision 101) @@ -99,4 +99,5 @@ // ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ," in_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH_VAL ," in_CONTEXT_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context); ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t ); @@ -178,4 +179,5 @@ // INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH_VAL ,_param->_nb_context); for (uint32_t i=0; i<_param->_nb_context; i++) if (_param->_have_port_depth) @@ -221,4 +223,7 @@ LABEL("Loop of Test"); + + for (uint32_t i=0; i<_param->_nb_context; i++) + in_CONTEXT_DEPTH_VAL [i]->write(1); for (uint32_t iteration=0; iteration_have_port_depth) sensitive << (*(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i])); + sensitive << (*(in_CONTEXT_DEPTH_VAL [i])); if (_param->_have_port_depth) sensitive << (*(in_CONTEXT_DEPTH [i])); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp (revision 101) @@ -23,9 +23,9 @@ void Decod::allocation ( #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics * param_statistics + morpheo::behavioural::Parameters_Statistics * param_statistics #else - void + void #endif - ) + ) { log_printf(FUNC,Decod,FUNCTION,"Begin"); @@ -34,9 +34,9 @@ Entity * entity = _component->set_entity (_name - ,"Decod" + ,"Decod" #ifdef POSITION - ,COMBINATORY + ,COMBINATORY #endif - ); + ); _interfaces = entity->set_interfaces(); @@ -46,9 +46,9 @@ Interface * interface = _interfaces->set_interface("" #ifdef POSITION - ,IN - ,SOUTH, - "Generalist interface" + ,IN + ,SOUTH, + "Generalist interface" #endif - ); + ); in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); @@ -77,5 +77,5 @@ } - // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { ALLOC1_INTERFACE("decod", OUT, EAST, "Instructiont decoded", _param->_nb_inst_decod); @@ -129,8 +129,9 @@ ALLOC1_SIGNAL_IN (in_CONTEXT_DECOD_ENABLE,"decod_enable",Tcontrol_t,1); + ALLOC1_SIGNAL_IN (in_CONTEXT_DEPTH_VAL ,"depth_val" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN (in_CONTEXT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); } - // ~~~~~[ Interface : "context_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "context_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { ALLOC_INTERFACE("context_event", OUT, NORTH, "context's evenement"); @@ -164,25 +165,25 @@ // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ _priority = new generic::priority::Priority (_name+"_priority" , - _param->_priority , - _param->_load_balancing, - _param->_nb_context , - _param->_nb_inst_fetch , - _param->_nb_context_select); + _param->_priority , + _param->_load_balancing, + _param->_nb_context , + _param->_nb_inst_fetch , + _param->_nb_context_select); const uint32_t nb_opcod_type = 14; const uint32_t tab_opcod_type [] = {MAX_OPCOD_0, - MAX_OPCOD_1 , - MAX_OPCOD_2 , - MAX_OPCOD_3 , - MAX_OPCOD_4 , - MAX_OPCOD_5 , - MAX_OPCOD_6 , - MAX_OPCOD_7 , - MAX_OPCOD_8 , - MAX_OPCOD_9 , - MAX_OPCOD_10, - MAX_OPCOD_11, - MAX_OPCOD_12, - MAX_OPCOD_13}; + MAX_OPCOD_1 , + MAX_OPCOD_2 , + MAX_OPCOD_3 , + MAX_OPCOD_4 , + MAX_OPCOD_5 , + MAX_OPCOD_6 , + MAX_OPCOD_7 , + MAX_OPCOD_8 , + MAX_OPCOD_9 , + MAX_OPCOD_10, + MAX_OPCOD_11, + MAX_OPCOD_12, + MAX_OPCOD_13}; _function_decod = new function_decod_t *** [_param->_nb_context]; @@ -190,262 +191,262 @@ for (uint32_t i=0; i<_param->_nb_context; i++) { - _function_decod [i] = new function_decod_t ** [nb_opcod_type]; - _function_custom [i] = new function_decod_t ** [nb_opcod_type]; - for (uint32_t j=0; j_instruction_implemeted[i][INSTRUCTION_L_ADD ]) _function_decod[i][ 3][OPCOD_L_ADD ] = &(instruction_l_add ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_ADDC ]) _function_decod[i][ 3][OPCOD_L_ADDC ] = &(instruction_l_addc ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_ADDI ]) _function_decod[i][ 0][OPCOD_L_ADDI ] = &(instruction_l_addi ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_ADDIC ]) _function_decod[i][ 0][OPCOD_L_ADDIC ] = &(instruction_l_addic ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_AND ]) _function_decod[i][ 3][OPCOD_L_AND ] = &(instruction_l_and ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_ANDI ]) _function_decod[i][ 0][OPCOD_L_ANDI ] = &(instruction_l_andi ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_BF ]) _function_decod[i][ 0][OPCOD_L_BF ] = &(instruction_l_bf ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_BNF ]) _function_decod[i][ 0][OPCOD_L_BNF ] = &(instruction_l_bnf ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CMOV ]) _function_decod[i][ 3][OPCOD_L_CMOV ] = &(instruction_l_cmov ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CSYNC ]) _function_decod[i][ 9][OPCOD_L_CSYNC ] = &(instruction_l_csync ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_DIV ]) _function_decod[i][ 3][OPCOD_L_DIV ] = &(instruction_l_div ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_DIVU ]) _function_decod[i][ 3][OPCOD_L_DIVU ] = &(instruction_l_divu ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_EXTBS ]) _function_decod[i][12][OPCOD_L_EXTBS ] = &(instruction_l_extbs ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_EXTBZ ]) _function_decod[i][12][OPCOD_L_EXTBZ ] = &(instruction_l_extbz ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_EXTHS ]) _function_decod[i][12][OPCOD_L_EXTHS ] = &(instruction_l_exths ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_EXTHZ ]) _function_decod[i][12][OPCOD_L_EXTHZ ] = &(instruction_l_exthz ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_EXTWS ]) _function_decod[i][13][OPCOD_L_EXTWS ] = &(instruction_l_extws ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_EXTWZ ]) _function_decod[i][13][OPCOD_L_EXTWZ ] = &(instruction_l_extwz ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_FF1 ]) _function_decod[i][ 3][OPCOD_L_FF1 ] = &(instruction_l_ff1 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_FL1 ]) _function_decod[i][ 3][OPCOD_L_FL1 ] = &(instruction_l_fl1 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_J ]) _function_decod[i][ 0][OPCOD_L_J ] = &(instruction_l_j ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_JAL ]) _function_decod[i][ 0][OPCOD_L_JAL ] = &(instruction_l_jal ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_JALR ]) _function_decod[i][ 0][OPCOD_L_JALR ] = &(instruction_l_jalr ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_JR ]) _function_decod[i][ 0][OPCOD_L_JR ] = &(instruction_l_jr ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_LBS ]) _function_decod[i][ 0][OPCOD_L_LBS ] = &(instruction_l_lbs ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_LBZ ]) _function_decod[i][ 0][OPCOD_L_LBZ ] = &(instruction_l_lbz ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_LD ]) _function_decod[i][ 0][OPCOD_L_LD ] = &(instruction_l_ld ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_LHS ]) _function_decod[i][ 0][OPCOD_L_LHS ] = &(instruction_l_lhs ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_LHZ ]) _function_decod[i][ 0][OPCOD_L_LHZ ] = &(instruction_l_lhz ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_LWS ]) _function_decod[i][ 0][OPCOD_L_LWS ] = &(instruction_l_lws ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_LWZ ]) _function_decod[i][ 0][OPCOD_L_LWZ ] = &(instruction_l_lwz ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_MAC ]) _function_decod[i][ 7][OPCOD_L_MAC ] = &(instruction_l_mac ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_MACI ]) _function_decod[i][ 0][OPCOD_L_MACI ] = &(instruction_l_maci ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_MACRC ]) _function_decod[i][ 8][OPCOD_L_MACRC ] = &(instruction_l_macrc ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_MFSPR ]) _function_decod[i][ 0][OPCOD_L_MFSPR ] = &(instruction_l_mfspr ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_MOVHI ]) _function_decod[i][ 8][OPCOD_L_MOVHI ] = &(instruction_l_movhi ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_MSB ]) _function_decod[i][ 7][OPCOD_L_MSB ] = &(instruction_l_msb ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_MSYNC ]) _function_decod[i][ 9][OPCOD_L_MSYNC ] = &(instruction_l_msync ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_MTSPR ]) _function_decod[i][ 0][OPCOD_L_MTSPR ] = &(instruction_l_mtspr ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_MUL ]) _function_decod[i][ 3][OPCOD_L_MUL ] = &(instruction_l_mul ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_MULI ]) _function_decod[i][ 0][OPCOD_L_MULI ] = &(instruction_l_muli ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_MULU ]) _function_decod[i][ 3][OPCOD_L_MULU ] = &(instruction_l_mulu ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_NOP ]) _function_decod[i][10][OPCOD_L_NOP ] = &(instruction_l_nop ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_OR ]) _function_decod[i][ 3][OPCOD_L_OR ] = &(instruction_l_or ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_ORI ]) _function_decod[i][ 0][OPCOD_L_ORI ] = &(instruction_l_ori ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_PSYNC ]) _function_decod[i][ 9][OPCOD_L_PSYNC ] = &(instruction_l_psync ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_RFE ]) _function_decod[i][ 0][OPCOD_L_RFE ] = &(instruction_l_rfe ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_ROR ]) _function_decod[i][11][OPCOD_L_ROR ] = &(instruction_l_ror ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_RORI ]) _function_decod[i][ 6][OPCOD_L_RORI ] = &(instruction_l_rori ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SB ]) _function_decod[i][ 0][OPCOD_L_SB ] = &(instruction_l_sb ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SD ]) _function_decod[i][ 0][OPCOD_L_SD ] = &(instruction_l_sd ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFEQ ]) _function_decod[i][ 4][OPCOD_L_SFEQ ] = &(instruction_l_sfeq ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFEQI ]) _function_decod[i][ 5][OPCOD_L_SFEQI ] = &(instruction_l_sfeqi ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGES ]) _function_decod[i][ 4][OPCOD_L_SFGES ] = &(instruction_l_sfges ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGESI ]) _function_decod[i][ 5][OPCOD_L_SFGESI ] = &(instruction_l_sfgesi ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGEU ]) _function_decod[i][ 4][OPCOD_L_SFGEU ] = &(instruction_l_sfgeu ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGEUI ]) _function_decod[i][ 5][OPCOD_L_SFGEUI ] = &(instruction_l_sfgeui ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGTS ]) _function_decod[i][ 4][OPCOD_L_SFGTS ] = &(instruction_l_sfgts ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGTSI ]) _function_decod[i][ 5][OPCOD_L_SFGTSI ] = &(instruction_l_sfgtsi ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGTU ]) _function_decod[i][ 4][OPCOD_L_SFGTU ] = &(instruction_l_sfgtu ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGTUI ]) _function_decod[i][ 5][OPCOD_L_SFGTUI ] = &(instruction_l_sfgtui ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLES ]) _function_decod[i][ 4][OPCOD_L_SFLES ] = &(instruction_l_sfles ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLESI ]) _function_decod[i][ 5][OPCOD_L_SFLESI ] = &(instruction_l_sflesi ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLEU ]) _function_decod[i][ 4][OPCOD_L_SFLEU ] = &(instruction_l_sfleu ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLEUI ]) _function_decod[i][ 5][OPCOD_L_SFLEUI ] = &(instruction_l_sfleui ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLTS ]) _function_decod[i][ 4][OPCOD_L_SFLTS ] = &(instruction_l_sflts ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLTSI ]) _function_decod[i][ 5][OPCOD_L_SFLTSI ] = &(instruction_l_sfltsi ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLTU ]) _function_decod[i][ 4][OPCOD_L_SFLTU ] = &(instruction_l_sfltu ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLTUI ]) _function_decod[i][ 5][OPCOD_L_SFLTUI ] = &(instruction_l_sfltui ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFNE ]) _function_decod[i][ 4][OPCOD_L_SFNE ] = &(instruction_l_sfne ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFNEI ]) _function_decod[i][ 5][OPCOD_L_SFNEI ] = &(instruction_l_sfnei ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SH ]) _function_decod[i][ 0][OPCOD_L_SH ] = &(instruction_l_sh ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SLL ]) _function_decod[i][11][OPCOD_L_SLL ] = &(instruction_l_sll ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SLLI ]) _function_decod[i][ 6][OPCOD_L_SLLI ] = &(instruction_l_slli ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SRA ]) _function_decod[i][11][OPCOD_L_SRA ] = &(instruction_l_sra ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SRAI ]) _function_decod[i][ 6][OPCOD_L_SRAI ] = &(instruction_l_srai ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SRL ]) _function_decod[i][11][OPCOD_L_SRL ] = &(instruction_l_srl ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SRLI ]) _function_decod[i][ 6][OPCOD_L_SRLI ] = &(instruction_l_srli ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SUB ]) _function_decod[i][ 3][OPCOD_L_SUB ] = &(instruction_l_sub ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SW ]) _function_decod[i][ 0][OPCOD_L_SW ] = &(instruction_l_sw ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_SYS ]) _function_decod[i][ 9][OPCOD_L_SYS ] = &(instruction_l_sys ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_TRAP ]) _function_decod[i][ 9][OPCOD_L_TRAP ] = &(instruction_l_trap ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_XOR ]) _function_decod[i][ 3][OPCOD_L_XOR ] = &(instruction_l_xor ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_XORI ]) _function_decod[i][ 0][OPCOD_L_XORI ] = &(instruction_l_xori ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_ADD_D ]) _function_decod[i][ 1][OPCOD_LF_ADD_D ] = &(instruction_lf_add_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_ADD_S ]) _function_decod[i][ 1][OPCOD_LF_ADD_S ] = &(instruction_lf_add_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_DIV_D ]) _function_decod[i][ 1][OPCOD_LF_DIV_D ] = &(instruction_lf_div_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_DIV_S ]) _function_decod[i][ 1][OPCOD_LF_DIV_S ] = &(instruction_lf_div_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_FTOI_D ]) _function_decod[i][ 1][OPCOD_LF_FTOI_D ] = &(instruction_lf_ftoi_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_FTOI_S ]) _function_decod[i][ 1][OPCOD_LF_FTOI_S ] = &(instruction_lf_ftoi_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_ITOF_D ]) _function_decod[i][ 1][OPCOD_LF_ITOF_D ] = &(instruction_lf_itof_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_ITOF_S ]) _function_decod[i][ 1][OPCOD_LF_ITOF_S ] = &(instruction_lf_itof_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_MADD_D ]) _function_decod[i][ 1][OPCOD_LF_MADD_D ] = &(instruction_lf_madd_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_MADD_S ]) _function_decod[i][ 1][OPCOD_LF_MADD_S ] = &(instruction_lf_madd_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_MUL_D ]) _function_decod[i][ 1][OPCOD_LF_MUL_D ] = &(instruction_lf_mul_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_MUL_S ]) _function_decod[i][ 1][OPCOD_LF_MUL_S ] = &(instruction_lf_mul_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_REM_D ]) _function_decod[i][ 1][OPCOD_LF_REM_D ] = &(instruction_lf_rem_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_REM_S ]) _function_decod[i][ 1][OPCOD_LF_REM_S ] = &(instruction_lf_rem_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFEQ_D ]) _function_decod[i][ 1][OPCOD_LF_SFEQ_D ] = &(instruction_lf_sfeq_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFEQ_S ]) _function_decod[i][ 1][OPCOD_LF_SFEQ_S ] = &(instruction_lf_sfeq_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFGE_D ]) _function_decod[i][ 1][OPCOD_LF_SFGE_D ] = &(instruction_lf_sfge_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFGE_S ]) _function_decod[i][ 1][OPCOD_LF_SFGE_S ] = &(instruction_lf_sfge_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFGT_D ]) _function_decod[i][ 1][OPCOD_LF_SFGT_D ] = &(instruction_lf_sfgt_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFGT_S ]) _function_decod[i][ 1][OPCOD_LF_SFGT_S ] = &(instruction_lf_sfgt_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFLE_D ]) _function_decod[i][ 1][OPCOD_LF_SFLE_D ] = &(instruction_lf_sfle_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFLE_S ]) _function_decod[i][ 1][OPCOD_LF_SFLE_S ] = &(instruction_lf_sfle_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFLT_D ]) _function_decod[i][ 1][OPCOD_LF_SFLT_D ] = &(instruction_lf_sflt_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFLT_S ]) _function_decod[i][ 1][OPCOD_LF_SFLT_S ] = &(instruction_lf_sflt_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFNE_D ]) _function_decod[i][ 1][OPCOD_LF_SFNE_D ] = &(instruction_lf_sfne_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFNE_S ]) _function_decod[i][ 1][OPCOD_LF_SFNE_S ] = &(instruction_lf_sfne_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SUB_D ]) _function_decod[i][ 1][OPCOD_LF_SUB_D ] = &(instruction_lf_sub_d ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SUB_S ]) _function_decod[i][ 1][OPCOD_LF_SUB_S ] = &(instruction_lf_sub_s ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADD_B ]) _function_decod[i][ 2][OPCOD_LV_ADD_B ] = &(instruction_lv_add_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADD_H ]) _function_decod[i][ 2][OPCOD_LV_ADD_H ] = &(instruction_lv_add_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADDS_B ]) _function_decod[i][ 2][OPCOD_LV_ADDS_B ] = &(instruction_lv_adds_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADDS_H ]) _function_decod[i][ 2][OPCOD_LV_ADDS_H ] = &(instruction_lv_adds_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADDU_B ]) _function_decod[i][ 2][OPCOD_LV_ADDU_B ] = &(instruction_lv_addu_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADDU_H ]) _function_decod[i][ 2][OPCOD_LV_ADDU_H ] = &(instruction_lv_addu_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADDUS_B ]) _function_decod[i][ 2][OPCOD_LV_ADDUS_B ] = &(instruction_lv_addus_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADDUS_H ]) _function_decod[i][ 2][OPCOD_LV_ADDUS_H ] = &(instruction_lv_addus_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_EQ_B]) _function_decod[i][ 2][OPCOD_LV_ALL_EQ_B] = &(instruction_lv_all_eq_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_EQ_H]) _function_decod[i][ 2][OPCOD_LV_ALL_EQ_H] = &(instruction_lv_all_eq_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_GE_B]) _function_decod[i][ 2][OPCOD_LV_ALL_GE_B] = &(instruction_lv_all_ge_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_GE_H]) _function_decod[i][ 2][OPCOD_LV_ALL_GE_H] = &(instruction_lv_all_ge_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_GT_B]) _function_decod[i][ 2][OPCOD_LV_ALL_GT_B] = &(instruction_lv_all_gt_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_GT_H]) _function_decod[i][ 2][OPCOD_LV_ALL_GT_H] = &(instruction_lv_all_gt_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_LE_B]) _function_decod[i][ 2][OPCOD_LV_ALL_LE_B] = &(instruction_lv_all_le_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_LE_H]) _function_decod[i][ 2][OPCOD_LV_ALL_LE_H] = &(instruction_lv_all_le_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_LT_B]) _function_decod[i][ 2][OPCOD_LV_ALL_LT_B] = &(instruction_lv_all_lt_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_LT_H]) _function_decod[i][ 2][OPCOD_LV_ALL_LT_H] = &(instruction_lv_all_lt_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_NE_B]) _function_decod[i][ 2][OPCOD_LV_ALL_NE_B] = &(instruction_lv_all_ne_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_NE_H]) _function_decod[i][ 2][OPCOD_LV_ALL_NE_H] = &(instruction_lv_all_ne_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_AND ]) _function_decod[i][ 2][OPCOD_LV_AND ] = &(instruction_lv_and ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_EQ_B]) _function_decod[i][ 2][OPCOD_LV_ANY_EQ_B] = &(instruction_lv_any_eq_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_EQ_H]) _function_decod[i][ 2][OPCOD_LV_ANY_EQ_H] = &(instruction_lv_any_eq_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_GE_B]) _function_decod[i][ 2][OPCOD_LV_ANY_GE_B] = &(instruction_lv_any_ge_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_GE_H]) _function_decod[i][ 2][OPCOD_LV_ANY_GE_H] = &(instruction_lv_any_ge_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_GT_B]) _function_decod[i][ 2][OPCOD_LV_ANY_GT_B] = &(instruction_lv_any_gt_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_GT_H]) _function_decod[i][ 2][OPCOD_LV_ANY_GT_H] = &(instruction_lv_any_gt_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_LE_B]) _function_decod[i][ 2][OPCOD_LV_ANY_LE_B] = &(instruction_lv_any_le_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_LE_H]) _function_decod[i][ 2][OPCOD_LV_ANY_LE_H] = &(instruction_lv_any_le_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_LT_B]) _function_decod[i][ 2][OPCOD_LV_ANY_LT_B] = &(instruction_lv_any_lt_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_LT_H]) _function_decod[i][ 2][OPCOD_LV_ANY_LT_H] = &(instruction_lv_any_lt_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_NE_B]) _function_decod[i][ 2][OPCOD_LV_ANY_NE_B] = &(instruction_lv_any_ne_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_NE_H]) _function_decod[i][ 2][OPCOD_LV_ANY_NE_H] = &(instruction_lv_any_ne_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_AVG_B ]) _function_decod[i][ 2][OPCOD_LV_AVG_B ] = &(instruction_lv_avg_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_AVG_H ]) _function_decod[i][ 2][OPCOD_LV_AVG_H ] = &(instruction_lv_avg_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_EQ_B]) _function_decod[i][ 2][OPCOD_LV_CMP_EQ_B] = &(instruction_lv_cmp_eq_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_EQ_H]) _function_decod[i][ 2][OPCOD_LV_CMP_EQ_H] = &(instruction_lv_cmp_eq_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_GE_B]) _function_decod[i][ 2][OPCOD_LV_CMP_GE_B] = &(instruction_lv_cmp_ge_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_GE_H]) _function_decod[i][ 2][OPCOD_LV_CMP_GE_H] = &(instruction_lv_cmp_ge_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_GT_B]) _function_decod[i][ 2][OPCOD_LV_CMP_GT_B] = &(instruction_lv_cmp_gt_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_GT_H]) _function_decod[i][ 2][OPCOD_LV_CMP_GT_H] = &(instruction_lv_cmp_gt_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_LE_B]) _function_decod[i][ 2][OPCOD_LV_CMP_LE_B] = &(instruction_lv_cmp_le_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_LE_H]) _function_decod[i][ 2][OPCOD_LV_CMP_LE_H] = &(instruction_lv_cmp_le_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_LT_B]) _function_decod[i][ 2][OPCOD_LV_CMP_LT_B] = &(instruction_lv_cmp_lt_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_LT_H]) _function_decod[i][ 2][OPCOD_LV_CMP_LT_H] = &(instruction_lv_cmp_lt_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_NE_B]) _function_decod[i][ 2][OPCOD_LV_CMP_NE_B] = &(instruction_lv_cmp_ne_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_NE_H]) _function_decod[i][ 2][OPCOD_LV_CMP_NE_H] = &(instruction_lv_cmp_ne_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MADDS_H ]) _function_decod[i][ 2][OPCOD_LV_MADDS_H ] = &(instruction_lv_madds_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MAX_B ]) _function_decod[i][ 2][OPCOD_LV_MAX_B ] = &(instruction_lv_max_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MAX_H ]) _function_decod[i][ 2][OPCOD_LV_MAX_H ] = &(instruction_lv_max_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MERGE_B ]) _function_decod[i][ 2][OPCOD_LV_MERGE_B ] = &(instruction_lv_merge_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MERGE_H ]) _function_decod[i][ 2][OPCOD_LV_MERGE_H ] = &(instruction_lv_merge_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MIN_B ]) _function_decod[i][ 2][OPCOD_LV_MIN_B ] = &(instruction_lv_min_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MIN_H ]) _function_decod[i][ 2][OPCOD_LV_MIN_H ] = &(instruction_lv_min_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MSUBS_H ]) _function_decod[i][ 2][OPCOD_LV_MSUBS_H ] = &(instruction_lv_msubs_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MULS_H ]) _function_decod[i][ 2][OPCOD_LV_MULS_H ] = &(instruction_lv_muls_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_NAND ]) _function_decod[i][ 2][OPCOD_LV_NAND ] = &(instruction_lv_nand ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_NOR ]) _function_decod[i][ 2][OPCOD_LV_NOR ] = &(instruction_lv_nor ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_OR ]) _function_decod[i][ 2][OPCOD_LV_OR ] = &(instruction_lv_or ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PACK_B ]) _function_decod[i][ 2][OPCOD_LV_PACK_B ] = &(instruction_lv_pack_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PACK_H ]) _function_decod[i][ 2][OPCOD_LV_PACK_H ] = &(instruction_lv_pack_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PACKS_B ]) _function_decod[i][ 2][OPCOD_LV_PACKS_B ] = &(instruction_lv_packs_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PACKS_H ]) _function_decod[i][ 2][OPCOD_LV_PACKS_H ] = &(instruction_lv_packs_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PACKUS_B]) _function_decod[i][ 2][OPCOD_LV_PACKUS_B] = &(instruction_lv_packus_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PACKUS_H]) _function_decod[i][ 2][OPCOD_LV_PACKUS_H] = &(instruction_lv_packus_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PERM_N ]) _function_decod[i][ 2][OPCOD_LV_PERM_N ] = &(instruction_lv_perm_n ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_RL_B ]) _function_decod[i][ 2][OPCOD_LV_RL_B ] = &(instruction_lv_rl_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_RL_H ]) _function_decod[i][ 2][OPCOD_LV_RL_H ] = &(instruction_lv_rl_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SLL ]) _function_decod[i][ 2][OPCOD_LV_SLL ] = &(instruction_lv_sll ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SLL_B ]) _function_decod[i][ 2][OPCOD_LV_SLL_B ] = &(instruction_lv_sll_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SLL_H ]) _function_decod[i][ 2][OPCOD_LV_SLL_H ] = &(instruction_lv_sll_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SRA_B ]) _function_decod[i][ 2][OPCOD_LV_SRA_B ] = &(instruction_lv_sra_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SRA_H ]) _function_decod[i][ 2][OPCOD_LV_SRA_H ] = &(instruction_lv_sra_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SRL ]) _function_decod[i][ 2][OPCOD_LV_SRL ] = &(instruction_lv_srl ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SRL_B ]) _function_decod[i][ 2][OPCOD_LV_SRL_B ] = &(instruction_lv_srl_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SRL_H ]) _function_decod[i][ 2][OPCOD_LV_SRL_H ] = &(instruction_lv_srl_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUB_B ]) _function_decod[i][ 2][OPCOD_LV_SUB_B ] = &(instruction_lv_sub_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUB_H ]) _function_decod[i][ 2][OPCOD_LV_SUB_H ] = &(instruction_lv_sub_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUBS_B ]) _function_decod[i][ 2][OPCOD_LV_SUBS_B ] = &(instruction_lv_subs_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUBS_H ]) _function_decod[i][ 2][OPCOD_LV_SUBS_H ] = &(instruction_lv_subs_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUBU_B ]) _function_decod[i][ 2][OPCOD_LV_SUBU_B ] = &(instruction_lv_subu_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUBU_H ]) _function_decod[i][ 2][OPCOD_LV_SUBU_H ] = &(instruction_lv_subu_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUBUS_B ]) _function_decod[i][ 2][OPCOD_LV_SUBUS_B ] = &(instruction_lv_subus_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUBUS_H ]) _function_decod[i][ 2][OPCOD_LV_SUBUS_H ] = &(instruction_lv_subus_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_UNPACK_B]) _function_decod[i][ 2][OPCOD_LV_UNPACK_B] = &(instruction_lv_unpack_b ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_UNPACK_H]) _function_decod[i][ 2][OPCOD_LV_UNPACK_H] = &(instruction_lv_unpack_h ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_XOR ]) _function_decod[i][ 2][OPCOD_LV_XOR ] = &(instruction_lv_xor ); - - // Custom Instruction - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST1 ]) _function_decod [i][ 0][OPCOD_L_CUST1 ] = &(instruction_l_custom ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST2 ]) _function_decod [i][ 0][OPCOD_L_CUST2 ] = &(instruction_l_custom ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST3 ]) _function_decod [i][ 0][OPCOD_L_CUST3 ] = &(instruction_l_custom ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST4 ]) _function_decod [i][ 0][OPCOD_L_CUST4 ] = &(instruction_l_custom ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST5 ]) _function_decod [i][ 0][OPCOD_L_CUST5 ] = &(instruction_l_custom ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST6 ]) _function_decod [i][ 0][OPCOD_L_CUST6 ] = &(instruction_l_custom ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST7 ]) _function_decod [i][ 0][OPCOD_L_CUST7 ] = &(instruction_l_custom ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST8 ]) _function_decod [i][ 0][OPCOD_L_CUST8 ] = &(instruction_l_custom ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_D ]) _function_decod [i][ 1][OPCOD_LF_CUST1_D ] = &(instruction_lf_custom); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_S ]) _function_decod [i][ 1][OPCOD_LF_CUST1_S ] = &(instruction_lf_custom); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST1 ]) _function_decod [i][ 2][OPCOD_LV_CUST1 ] = &(instruction_lv_custom); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST2 ]) _function_decod [i][ 2][OPCOD_LV_CUST2 ] = &(instruction_lv_custom); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST3 ]) _function_decod [i][ 2][OPCOD_LV_CUST3 ] = &(instruction_lv_custom); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST4 ]) _function_decod [i][ 2][OPCOD_LV_CUST4 ] = &(instruction_lv_custom); - - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST1 ]) _function_custom[i][ 0][OPCOD_L_CUST1 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_1 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST2 ]) _function_custom[i][ 0][OPCOD_L_CUST2 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_2 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST3 ]) _function_custom[i][ 0][OPCOD_L_CUST3 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_3 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST4 ]) _function_custom[i][ 0][OPCOD_L_CUST4 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_4 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST5 ]) _function_custom[i][ 0][OPCOD_L_CUST5 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_5 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST6 ]) _function_custom[i][ 0][OPCOD_L_CUST6 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_6 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST7 ]) _function_custom[i][ 0][OPCOD_L_CUST7 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_7 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST8 ]) _function_custom[i][ 0][OPCOD_L_CUST8 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_8 ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_D ]) _function_custom[i][ 1][OPCOD_LF_CUST1_D ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LF_1_D); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_S ]) _function_custom[i][ 1][OPCOD_LF_CUST1_S ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LF_1_S); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST1 ]) _function_custom[i][ 2][OPCOD_LV_CUST1 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_1 ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST2 ]) _function_custom[i][ 2][OPCOD_LV_CUST2 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_2 ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST3 ]) _function_custom[i][ 2][OPCOD_LV_CUST3 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_3 ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST4 ]) _function_custom[i][ 2][OPCOD_LV_CUST4 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_4 ); + _function_decod [i] = new function_decod_t ** [nb_opcod_type]; + _function_custom [i] = new function_decod_t ** [nb_opcod_type]; + for (uint32_t j=0; j_instruction_implemeted[i][INSTRUCTION_L_ADD ]) _function_decod[i][ 3][OPCOD_L_ADD ] = &(instruction_l_add ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_ADDC ]) _function_decod[i][ 3][OPCOD_L_ADDC ] = &(instruction_l_addc ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_ADDI ]) _function_decod[i][ 0][OPCOD_L_ADDI ] = &(instruction_l_addi ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_ADDIC ]) _function_decod[i][ 0][OPCOD_L_ADDIC ] = &(instruction_l_addic ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_AND ]) _function_decod[i][ 3][OPCOD_L_AND ] = &(instruction_l_and ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_ANDI ]) _function_decod[i][ 0][OPCOD_L_ANDI ] = &(instruction_l_andi ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_BF ]) _function_decod[i][ 0][OPCOD_L_BF ] = &(instruction_l_bf ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_BNF ]) _function_decod[i][ 0][OPCOD_L_BNF ] = &(instruction_l_bnf ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CMOV ]) _function_decod[i][ 3][OPCOD_L_CMOV ] = &(instruction_l_cmov ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CSYNC ]) _function_decod[i][ 9][OPCOD_L_CSYNC ] = &(instruction_l_csync ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_DIV ]) _function_decod[i][ 3][OPCOD_L_DIV ] = &(instruction_l_div ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_DIVU ]) _function_decod[i][ 3][OPCOD_L_DIVU ] = &(instruction_l_divu ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_EXTBS ]) _function_decod[i][12][OPCOD_L_EXTBS ] = &(instruction_l_extbs ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_EXTBZ ]) _function_decod[i][12][OPCOD_L_EXTBZ ] = &(instruction_l_extbz ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_EXTHS ]) _function_decod[i][12][OPCOD_L_EXTHS ] = &(instruction_l_exths ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_EXTHZ ]) _function_decod[i][12][OPCOD_L_EXTHZ ] = &(instruction_l_exthz ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_EXTWS ]) _function_decod[i][13][OPCOD_L_EXTWS ] = &(instruction_l_extws ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_EXTWZ ]) _function_decod[i][13][OPCOD_L_EXTWZ ] = &(instruction_l_extwz ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_FF1 ]) _function_decod[i][ 3][OPCOD_L_FF1 ] = &(instruction_l_ff1 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_FL1 ]) _function_decod[i][ 3][OPCOD_L_FL1 ] = &(instruction_l_fl1 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_J ]) _function_decod[i][ 0][OPCOD_L_J ] = &(instruction_l_j ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_JAL ]) _function_decod[i][ 0][OPCOD_L_JAL ] = &(instruction_l_jal ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_JALR ]) _function_decod[i][ 0][OPCOD_L_JALR ] = &(instruction_l_jalr ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_JR ]) _function_decod[i][ 0][OPCOD_L_JR ] = &(instruction_l_jr ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_LBS ]) _function_decod[i][ 0][OPCOD_L_LBS ] = &(instruction_l_lbs ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_LBZ ]) _function_decod[i][ 0][OPCOD_L_LBZ ] = &(instruction_l_lbz ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_LD ]) _function_decod[i][ 0][OPCOD_L_LD ] = &(instruction_l_ld ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_LHS ]) _function_decod[i][ 0][OPCOD_L_LHS ] = &(instruction_l_lhs ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_LHZ ]) _function_decod[i][ 0][OPCOD_L_LHZ ] = &(instruction_l_lhz ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_LWS ]) _function_decod[i][ 0][OPCOD_L_LWS ] = &(instruction_l_lws ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_LWZ ]) _function_decod[i][ 0][OPCOD_L_LWZ ] = &(instruction_l_lwz ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_MAC ]) _function_decod[i][ 7][OPCOD_L_MAC ] = &(instruction_l_mac ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_MACI ]) _function_decod[i][ 0][OPCOD_L_MACI ] = &(instruction_l_maci ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_MACRC ]) _function_decod[i][ 8][OPCOD_L_MACRC ] = &(instruction_l_macrc ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_MFSPR ]) _function_decod[i][ 0][OPCOD_L_MFSPR ] = &(instruction_l_mfspr ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_MOVHI ]) _function_decod[i][ 8][OPCOD_L_MOVHI ] = &(instruction_l_movhi ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_MSB ]) _function_decod[i][ 7][OPCOD_L_MSB ] = &(instruction_l_msb ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_MSYNC ]) _function_decod[i][ 9][OPCOD_L_MSYNC ] = &(instruction_l_msync ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_MTSPR ]) _function_decod[i][ 0][OPCOD_L_MTSPR ] = &(instruction_l_mtspr ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_MUL ]) _function_decod[i][ 3][OPCOD_L_MUL ] = &(instruction_l_mul ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_MULI ]) _function_decod[i][ 0][OPCOD_L_MULI ] = &(instruction_l_muli ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_MULU ]) _function_decod[i][ 3][OPCOD_L_MULU ] = &(instruction_l_mulu ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_NOP ]) _function_decod[i][10][OPCOD_L_NOP ] = &(instruction_l_nop ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_OR ]) _function_decod[i][ 3][OPCOD_L_OR ] = &(instruction_l_or ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_ORI ]) _function_decod[i][ 0][OPCOD_L_ORI ] = &(instruction_l_ori ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_PSYNC ]) _function_decod[i][ 9][OPCOD_L_PSYNC ] = &(instruction_l_psync ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_RFE ]) _function_decod[i][ 0][OPCOD_L_RFE ] = &(instruction_l_rfe ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_ROR ]) _function_decod[i][11][OPCOD_L_ROR ] = &(instruction_l_ror ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_RORI ]) _function_decod[i][ 6][OPCOD_L_RORI ] = &(instruction_l_rori ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SB ]) _function_decod[i][ 0][OPCOD_L_SB ] = &(instruction_l_sb ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SD ]) _function_decod[i][ 0][OPCOD_L_SD ] = &(instruction_l_sd ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFEQ ]) _function_decod[i][ 4][OPCOD_L_SFEQ ] = &(instruction_l_sfeq ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFEQI ]) _function_decod[i][ 5][OPCOD_L_SFEQI ] = &(instruction_l_sfeqi ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGES ]) _function_decod[i][ 4][OPCOD_L_SFGES ] = &(instruction_l_sfges ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGESI ]) _function_decod[i][ 5][OPCOD_L_SFGESI ] = &(instruction_l_sfgesi ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGEU ]) _function_decod[i][ 4][OPCOD_L_SFGEU ] = &(instruction_l_sfgeu ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGEUI ]) _function_decod[i][ 5][OPCOD_L_SFGEUI ] = &(instruction_l_sfgeui ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGTS ]) _function_decod[i][ 4][OPCOD_L_SFGTS ] = &(instruction_l_sfgts ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGTSI ]) _function_decod[i][ 5][OPCOD_L_SFGTSI ] = &(instruction_l_sfgtsi ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGTU ]) _function_decod[i][ 4][OPCOD_L_SFGTU ] = &(instruction_l_sfgtu ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFGTUI ]) _function_decod[i][ 5][OPCOD_L_SFGTUI ] = &(instruction_l_sfgtui ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLES ]) _function_decod[i][ 4][OPCOD_L_SFLES ] = &(instruction_l_sfles ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLESI ]) _function_decod[i][ 5][OPCOD_L_SFLESI ] = &(instruction_l_sflesi ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLEU ]) _function_decod[i][ 4][OPCOD_L_SFLEU ] = &(instruction_l_sfleu ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLEUI ]) _function_decod[i][ 5][OPCOD_L_SFLEUI ] = &(instruction_l_sfleui ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLTS ]) _function_decod[i][ 4][OPCOD_L_SFLTS ] = &(instruction_l_sflts ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLTSI ]) _function_decod[i][ 5][OPCOD_L_SFLTSI ] = &(instruction_l_sfltsi ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLTU ]) _function_decod[i][ 4][OPCOD_L_SFLTU ] = &(instruction_l_sfltu ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFLTUI ]) _function_decod[i][ 5][OPCOD_L_SFLTUI ] = &(instruction_l_sfltui ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFNE ]) _function_decod[i][ 4][OPCOD_L_SFNE ] = &(instruction_l_sfne ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SFNEI ]) _function_decod[i][ 5][OPCOD_L_SFNEI ] = &(instruction_l_sfnei ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SH ]) _function_decod[i][ 0][OPCOD_L_SH ] = &(instruction_l_sh ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SLL ]) _function_decod[i][11][OPCOD_L_SLL ] = &(instruction_l_sll ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SLLI ]) _function_decod[i][ 6][OPCOD_L_SLLI ] = &(instruction_l_slli ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SRA ]) _function_decod[i][11][OPCOD_L_SRA ] = &(instruction_l_sra ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SRAI ]) _function_decod[i][ 6][OPCOD_L_SRAI ] = &(instruction_l_srai ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SRL ]) _function_decod[i][11][OPCOD_L_SRL ] = &(instruction_l_srl ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SRLI ]) _function_decod[i][ 6][OPCOD_L_SRLI ] = &(instruction_l_srli ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SUB ]) _function_decod[i][ 3][OPCOD_L_SUB ] = &(instruction_l_sub ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SW ]) _function_decod[i][ 0][OPCOD_L_SW ] = &(instruction_l_sw ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_SYS ]) _function_decod[i][ 9][OPCOD_L_SYS ] = &(instruction_l_sys ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_TRAP ]) _function_decod[i][ 9][OPCOD_L_TRAP ] = &(instruction_l_trap ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_XOR ]) _function_decod[i][ 3][OPCOD_L_XOR ] = &(instruction_l_xor ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_XORI ]) _function_decod[i][ 0][OPCOD_L_XORI ] = &(instruction_l_xori ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_ADD_D ]) _function_decod[i][ 1][OPCOD_LF_ADD_D ] = &(instruction_lf_add_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_ADD_S ]) _function_decod[i][ 1][OPCOD_LF_ADD_S ] = &(instruction_lf_add_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_DIV_D ]) _function_decod[i][ 1][OPCOD_LF_DIV_D ] = &(instruction_lf_div_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_DIV_S ]) _function_decod[i][ 1][OPCOD_LF_DIV_S ] = &(instruction_lf_div_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_FTOI_D ]) _function_decod[i][ 1][OPCOD_LF_FTOI_D ] = &(instruction_lf_ftoi_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_FTOI_S ]) _function_decod[i][ 1][OPCOD_LF_FTOI_S ] = &(instruction_lf_ftoi_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_ITOF_D ]) _function_decod[i][ 1][OPCOD_LF_ITOF_D ] = &(instruction_lf_itof_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_ITOF_S ]) _function_decod[i][ 1][OPCOD_LF_ITOF_S ] = &(instruction_lf_itof_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_MADD_D ]) _function_decod[i][ 1][OPCOD_LF_MADD_D ] = &(instruction_lf_madd_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_MADD_S ]) _function_decod[i][ 1][OPCOD_LF_MADD_S ] = &(instruction_lf_madd_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_MUL_D ]) _function_decod[i][ 1][OPCOD_LF_MUL_D ] = &(instruction_lf_mul_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_MUL_S ]) _function_decod[i][ 1][OPCOD_LF_MUL_S ] = &(instruction_lf_mul_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_REM_D ]) _function_decod[i][ 1][OPCOD_LF_REM_D ] = &(instruction_lf_rem_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_REM_S ]) _function_decod[i][ 1][OPCOD_LF_REM_S ] = &(instruction_lf_rem_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFEQ_D ]) _function_decod[i][ 1][OPCOD_LF_SFEQ_D ] = &(instruction_lf_sfeq_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFEQ_S ]) _function_decod[i][ 1][OPCOD_LF_SFEQ_S ] = &(instruction_lf_sfeq_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFGE_D ]) _function_decod[i][ 1][OPCOD_LF_SFGE_D ] = &(instruction_lf_sfge_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFGE_S ]) _function_decod[i][ 1][OPCOD_LF_SFGE_S ] = &(instruction_lf_sfge_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFGT_D ]) _function_decod[i][ 1][OPCOD_LF_SFGT_D ] = &(instruction_lf_sfgt_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFGT_S ]) _function_decod[i][ 1][OPCOD_LF_SFGT_S ] = &(instruction_lf_sfgt_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFLE_D ]) _function_decod[i][ 1][OPCOD_LF_SFLE_D ] = &(instruction_lf_sfle_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFLE_S ]) _function_decod[i][ 1][OPCOD_LF_SFLE_S ] = &(instruction_lf_sfle_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFLT_D ]) _function_decod[i][ 1][OPCOD_LF_SFLT_D ] = &(instruction_lf_sflt_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFLT_S ]) _function_decod[i][ 1][OPCOD_LF_SFLT_S ] = &(instruction_lf_sflt_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFNE_D ]) _function_decod[i][ 1][OPCOD_LF_SFNE_D ] = &(instruction_lf_sfne_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SFNE_S ]) _function_decod[i][ 1][OPCOD_LF_SFNE_S ] = &(instruction_lf_sfne_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SUB_D ]) _function_decod[i][ 1][OPCOD_LF_SUB_D ] = &(instruction_lf_sub_d ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_SUB_S ]) _function_decod[i][ 1][OPCOD_LF_SUB_S ] = &(instruction_lf_sub_s ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADD_B ]) _function_decod[i][ 2][OPCOD_LV_ADD_B ] = &(instruction_lv_add_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADD_H ]) _function_decod[i][ 2][OPCOD_LV_ADD_H ] = &(instruction_lv_add_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADDS_B ]) _function_decod[i][ 2][OPCOD_LV_ADDS_B ] = &(instruction_lv_adds_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADDS_H ]) _function_decod[i][ 2][OPCOD_LV_ADDS_H ] = &(instruction_lv_adds_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADDU_B ]) _function_decod[i][ 2][OPCOD_LV_ADDU_B ] = &(instruction_lv_addu_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADDU_H ]) _function_decod[i][ 2][OPCOD_LV_ADDU_H ] = &(instruction_lv_addu_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADDUS_B ]) _function_decod[i][ 2][OPCOD_LV_ADDUS_B ] = &(instruction_lv_addus_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ADDUS_H ]) _function_decod[i][ 2][OPCOD_LV_ADDUS_H ] = &(instruction_lv_addus_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_EQ_B]) _function_decod[i][ 2][OPCOD_LV_ALL_EQ_B] = &(instruction_lv_all_eq_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_EQ_H]) _function_decod[i][ 2][OPCOD_LV_ALL_EQ_H] = &(instruction_lv_all_eq_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_GE_B]) _function_decod[i][ 2][OPCOD_LV_ALL_GE_B] = &(instruction_lv_all_ge_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_GE_H]) _function_decod[i][ 2][OPCOD_LV_ALL_GE_H] = &(instruction_lv_all_ge_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_GT_B]) _function_decod[i][ 2][OPCOD_LV_ALL_GT_B] = &(instruction_lv_all_gt_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_GT_H]) _function_decod[i][ 2][OPCOD_LV_ALL_GT_H] = &(instruction_lv_all_gt_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_LE_B]) _function_decod[i][ 2][OPCOD_LV_ALL_LE_B] = &(instruction_lv_all_le_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_LE_H]) _function_decod[i][ 2][OPCOD_LV_ALL_LE_H] = &(instruction_lv_all_le_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_LT_B]) _function_decod[i][ 2][OPCOD_LV_ALL_LT_B] = &(instruction_lv_all_lt_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_LT_H]) _function_decod[i][ 2][OPCOD_LV_ALL_LT_H] = &(instruction_lv_all_lt_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_NE_B]) _function_decod[i][ 2][OPCOD_LV_ALL_NE_B] = &(instruction_lv_all_ne_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ALL_NE_H]) _function_decod[i][ 2][OPCOD_LV_ALL_NE_H] = &(instruction_lv_all_ne_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_AND ]) _function_decod[i][ 2][OPCOD_LV_AND ] = &(instruction_lv_and ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_EQ_B]) _function_decod[i][ 2][OPCOD_LV_ANY_EQ_B] = &(instruction_lv_any_eq_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_EQ_H]) _function_decod[i][ 2][OPCOD_LV_ANY_EQ_H] = &(instruction_lv_any_eq_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_GE_B]) _function_decod[i][ 2][OPCOD_LV_ANY_GE_B] = &(instruction_lv_any_ge_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_GE_H]) _function_decod[i][ 2][OPCOD_LV_ANY_GE_H] = &(instruction_lv_any_ge_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_GT_B]) _function_decod[i][ 2][OPCOD_LV_ANY_GT_B] = &(instruction_lv_any_gt_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_GT_H]) _function_decod[i][ 2][OPCOD_LV_ANY_GT_H] = &(instruction_lv_any_gt_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_LE_B]) _function_decod[i][ 2][OPCOD_LV_ANY_LE_B] = &(instruction_lv_any_le_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_LE_H]) _function_decod[i][ 2][OPCOD_LV_ANY_LE_H] = &(instruction_lv_any_le_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_LT_B]) _function_decod[i][ 2][OPCOD_LV_ANY_LT_B] = &(instruction_lv_any_lt_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_LT_H]) _function_decod[i][ 2][OPCOD_LV_ANY_LT_H] = &(instruction_lv_any_lt_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_NE_B]) _function_decod[i][ 2][OPCOD_LV_ANY_NE_B] = &(instruction_lv_any_ne_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_ANY_NE_H]) _function_decod[i][ 2][OPCOD_LV_ANY_NE_H] = &(instruction_lv_any_ne_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_AVG_B ]) _function_decod[i][ 2][OPCOD_LV_AVG_B ] = &(instruction_lv_avg_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_AVG_H ]) _function_decod[i][ 2][OPCOD_LV_AVG_H ] = &(instruction_lv_avg_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_EQ_B]) _function_decod[i][ 2][OPCOD_LV_CMP_EQ_B] = &(instruction_lv_cmp_eq_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_EQ_H]) _function_decod[i][ 2][OPCOD_LV_CMP_EQ_H] = &(instruction_lv_cmp_eq_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_GE_B]) _function_decod[i][ 2][OPCOD_LV_CMP_GE_B] = &(instruction_lv_cmp_ge_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_GE_H]) _function_decod[i][ 2][OPCOD_LV_CMP_GE_H] = &(instruction_lv_cmp_ge_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_GT_B]) _function_decod[i][ 2][OPCOD_LV_CMP_GT_B] = &(instruction_lv_cmp_gt_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_GT_H]) _function_decod[i][ 2][OPCOD_LV_CMP_GT_H] = &(instruction_lv_cmp_gt_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_LE_B]) _function_decod[i][ 2][OPCOD_LV_CMP_LE_B] = &(instruction_lv_cmp_le_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_LE_H]) _function_decod[i][ 2][OPCOD_LV_CMP_LE_H] = &(instruction_lv_cmp_le_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_LT_B]) _function_decod[i][ 2][OPCOD_LV_CMP_LT_B] = &(instruction_lv_cmp_lt_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_LT_H]) _function_decod[i][ 2][OPCOD_LV_CMP_LT_H] = &(instruction_lv_cmp_lt_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_NE_B]) _function_decod[i][ 2][OPCOD_LV_CMP_NE_B] = &(instruction_lv_cmp_ne_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CMP_NE_H]) _function_decod[i][ 2][OPCOD_LV_CMP_NE_H] = &(instruction_lv_cmp_ne_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MADDS_H ]) _function_decod[i][ 2][OPCOD_LV_MADDS_H ] = &(instruction_lv_madds_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MAX_B ]) _function_decod[i][ 2][OPCOD_LV_MAX_B ] = &(instruction_lv_max_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MAX_H ]) _function_decod[i][ 2][OPCOD_LV_MAX_H ] = &(instruction_lv_max_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MERGE_B ]) _function_decod[i][ 2][OPCOD_LV_MERGE_B ] = &(instruction_lv_merge_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MERGE_H ]) _function_decod[i][ 2][OPCOD_LV_MERGE_H ] = &(instruction_lv_merge_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MIN_B ]) _function_decod[i][ 2][OPCOD_LV_MIN_B ] = &(instruction_lv_min_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MIN_H ]) _function_decod[i][ 2][OPCOD_LV_MIN_H ] = &(instruction_lv_min_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MSUBS_H ]) _function_decod[i][ 2][OPCOD_LV_MSUBS_H ] = &(instruction_lv_msubs_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_MULS_H ]) _function_decod[i][ 2][OPCOD_LV_MULS_H ] = &(instruction_lv_muls_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_NAND ]) _function_decod[i][ 2][OPCOD_LV_NAND ] = &(instruction_lv_nand ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_NOR ]) _function_decod[i][ 2][OPCOD_LV_NOR ] = &(instruction_lv_nor ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_OR ]) _function_decod[i][ 2][OPCOD_LV_OR ] = &(instruction_lv_or ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PACK_B ]) _function_decod[i][ 2][OPCOD_LV_PACK_B ] = &(instruction_lv_pack_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PACK_H ]) _function_decod[i][ 2][OPCOD_LV_PACK_H ] = &(instruction_lv_pack_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PACKS_B ]) _function_decod[i][ 2][OPCOD_LV_PACKS_B ] = &(instruction_lv_packs_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PACKS_H ]) _function_decod[i][ 2][OPCOD_LV_PACKS_H ] = &(instruction_lv_packs_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PACKUS_B]) _function_decod[i][ 2][OPCOD_LV_PACKUS_B] = &(instruction_lv_packus_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PACKUS_H]) _function_decod[i][ 2][OPCOD_LV_PACKUS_H] = &(instruction_lv_packus_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_PERM_N ]) _function_decod[i][ 2][OPCOD_LV_PERM_N ] = &(instruction_lv_perm_n ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_RL_B ]) _function_decod[i][ 2][OPCOD_LV_RL_B ] = &(instruction_lv_rl_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_RL_H ]) _function_decod[i][ 2][OPCOD_LV_RL_H ] = &(instruction_lv_rl_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SLL ]) _function_decod[i][ 2][OPCOD_LV_SLL ] = &(instruction_lv_sll ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SLL_B ]) _function_decod[i][ 2][OPCOD_LV_SLL_B ] = &(instruction_lv_sll_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SLL_H ]) _function_decod[i][ 2][OPCOD_LV_SLL_H ] = &(instruction_lv_sll_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SRA_B ]) _function_decod[i][ 2][OPCOD_LV_SRA_B ] = &(instruction_lv_sra_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SRA_H ]) _function_decod[i][ 2][OPCOD_LV_SRA_H ] = &(instruction_lv_sra_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SRL ]) _function_decod[i][ 2][OPCOD_LV_SRL ] = &(instruction_lv_srl ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SRL_B ]) _function_decod[i][ 2][OPCOD_LV_SRL_B ] = &(instruction_lv_srl_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SRL_H ]) _function_decod[i][ 2][OPCOD_LV_SRL_H ] = &(instruction_lv_srl_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUB_B ]) _function_decod[i][ 2][OPCOD_LV_SUB_B ] = &(instruction_lv_sub_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUB_H ]) _function_decod[i][ 2][OPCOD_LV_SUB_H ] = &(instruction_lv_sub_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUBS_B ]) _function_decod[i][ 2][OPCOD_LV_SUBS_B ] = &(instruction_lv_subs_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUBS_H ]) _function_decod[i][ 2][OPCOD_LV_SUBS_H ] = &(instruction_lv_subs_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUBU_B ]) _function_decod[i][ 2][OPCOD_LV_SUBU_B ] = &(instruction_lv_subu_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUBU_H ]) _function_decod[i][ 2][OPCOD_LV_SUBU_H ] = &(instruction_lv_subu_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUBUS_B ]) _function_decod[i][ 2][OPCOD_LV_SUBUS_B ] = &(instruction_lv_subus_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_SUBUS_H ]) _function_decod[i][ 2][OPCOD_LV_SUBUS_H ] = &(instruction_lv_subus_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_UNPACK_B]) _function_decod[i][ 2][OPCOD_LV_UNPACK_B] = &(instruction_lv_unpack_b ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_UNPACK_H]) _function_decod[i][ 2][OPCOD_LV_UNPACK_H] = &(instruction_lv_unpack_h ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_XOR ]) _function_decod[i][ 2][OPCOD_LV_XOR ] = &(instruction_lv_xor ); + + // Custom Instruction + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST1 ]) _function_decod [i][ 0][OPCOD_L_CUST1 ] = &(instruction_l_custom ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST2 ]) _function_decod [i][ 0][OPCOD_L_CUST2 ] = &(instruction_l_custom ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST3 ]) _function_decod [i][ 0][OPCOD_L_CUST3 ] = &(instruction_l_custom ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST4 ]) _function_decod [i][ 0][OPCOD_L_CUST4 ] = &(instruction_l_custom ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST5 ]) _function_decod [i][ 0][OPCOD_L_CUST5 ] = &(instruction_l_custom ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST6 ]) _function_decod [i][ 0][OPCOD_L_CUST6 ] = &(instruction_l_custom ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST7 ]) _function_decod [i][ 0][OPCOD_L_CUST7 ] = &(instruction_l_custom ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST8 ]) _function_decod [i][ 0][OPCOD_L_CUST8 ] = &(instruction_l_custom ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_D ]) _function_decod [i][ 1][OPCOD_LF_CUST1_D ] = &(instruction_lf_custom); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_S ]) _function_decod [i][ 1][OPCOD_LF_CUST1_S ] = &(instruction_lf_custom); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST1 ]) _function_decod [i][ 2][OPCOD_LV_CUST1 ] = &(instruction_lv_custom); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST2 ]) _function_decod [i][ 2][OPCOD_LV_CUST2 ] = &(instruction_lv_custom); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST3 ]) _function_decod [i][ 2][OPCOD_LV_CUST3 ] = &(instruction_lv_custom); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST4 ]) _function_decod [i][ 2][OPCOD_LV_CUST4 ] = &(instruction_lv_custom); + + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST1 ]) _function_custom[i][ 0][OPCOD_L_CUST1 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_1 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST2 ]) _function_custom[i][ 0][OPCOD_L_CUST2 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_2 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST3 ]) _function_custom[i][ 0][OPCOD_L_CUST3 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_3 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST4 ]) _function_custom[i][ 0][OPCOD_L_CUST4 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_4 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST5 ]) _function_custom[i][ 0][OPCOD_L_CUST5 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_5 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST6 ]) _function_custom[i][ 0][OPCOD_L_CUST6 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_6 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST7 ]) _function_custom[i][ 0][OPCOD_L_CUST7 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_7 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST8 ]) _function_custom[i][ 0][OPCOD_L_CUST8 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_8 ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_D ]) _function_custom[i][ 1][OPCOD_LF_CUST1_D ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LF_1_D); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_S ]) _function_custom[i][ 1][OPCOD_LF_CUST1_S ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LF_1_S); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST1 ]) _function_custom[i][ 2][OPCOD_LV_CUST1 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_1 ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST2 ]) _function_custom[i][ 2][OPCOD_LV_CUST2 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_2 ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST3 ]) _function_custom[i][ 2][OPCOD_LV_CUST3 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_3 ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST4 ]) _function_custom[i][ 2][OPCOD_LV_CUST4 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_4 ); } @@ -455,6 +456,6 @@ for (uint32_t i=0; i<_param->_nb_context; i++) _decod_param [i] = new decod_param_t (_param->_size_general_data, - _function_decod [i], - _function_custom[i]); + _function_decod [i], + _function_custom[i]); #ifdef POSITION Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp (revision 101) @@ -79,4 +79,5 @@ DELETE1_SIGNAL(in_CONTEXT_DECOD_ENABLE, _param->_nb_context,1); + DELETE1_SIGNAL(in_CONTEXT_DEPTH_VAL , _param->_nb_context,1); DELETE1_SIGNAL(in_CONTEXT_DEPTH , _param->_nb_context,_param->_size_depth); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp (revision 101) @@ -77,4 +77,5 @@ { log_printf(TRACE,Decod,FUNCTION," * IFETCH [%d][%d]",x,y); + log_printf(TRACE,Decod,FUNCTION," * decod_ack [%d] : %d",i,PORT_READ(in_DECOD_ACK [i])); can_continue [x] = can_continue_next [x]; @@ -145,5 +146,5 @@ PORT_WRITE(out_DECOD_READ_RC [i], _decod_instruction->_read_rc ); PORT_WRITE(out_DECOD_NUM_REG_RC [i], _decod_instruction->_num_reg_rc ); - PORT_WRITE(out_DECOD_WRITE_RD [i], _decod_instruction->_write_rd ); + PORT_WRITE(out_DECOD_WRITE_RD [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0); PORT_WRITE(out_DECOD_NUM_REG_RD [i], _decod_instruction->_num_reg_rd ); PORT_WRITE(out_DECOD_WRITE_RE [i], _decod_instruction->_write_re ); @@ -152,7 +153,14 @@ // PORT_WRITE(out_DECOD_EXCEPTION [i], _decod_instruction->_exception ); + // Branch predictor can accept : the depth is valid + log_printf(TRACE,Decod,FUNCTION," * context_depth_val : %d",PORT_READ(in_CONTEXT_DEPTH_VAL [x])); + decod_val [i] &= PORT_READ(in_CONTEXT_DEPTH_VAL [x]); + ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_DEPTH_VAL [x]); + if (type == TYPE_BRANCH) { log_printf(TRACE,Decod,FUNCTION," * type is branch"); + log_printf(TRACE,Decod,FUNCTION," * predict_ack : %d",PORT_READ(in_PREDICT_ACK [i])); + log_printf(TRACE,Decod,FUNCTION," * address src : %.8x (%.8x)",_decod_instruction->_address ,_decod_instruction->_address <<2); log_printf(TRACE,Decod,FUNCTION," * address dest : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2); @@ -160,7 +168,7 @@ predict_val [i] = ifetch_ack [x][y] // and decod_val [i] ; - decod_val [i] &= PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable - ifetch_ack [x][y] &= PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack - + decod_val [i] &= PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable + ifetch_ack [x][y] &= PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack + if (_param->_have_port_context_id) PORT_WRITE(out_PREDICT_CONTEXT_ID [i],x); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp (revision 101) @@ -102,4 +102,5 @@ ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_DEPTH_MAX ," in_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_DEPTH_FULL ," in_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_NB_INST_ALL ,"out_NB_INST_ALL ",Tcounter_t ,_param->_nb_context); @@ -166,9 +167,10 @@ INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_EXCEPTION ,_param->_nb_inst_decod); - for (uint32_t i=0; i<_param->_nb_context; ++i) - if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL(_Decod_queue, in_DEPTH_MIN [i]); + if (_param->_have_port_depth) + { + INSTANCE1_SC_SIGNAL(_Decod_queue, in_DEPTH_MIN ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod_queue, in_DEPTH_MAX ,_param->_nb_context); - + } + INSTANCE1_SC_SIGNAL(_Decod_queue, in_DEPTH_FULL ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod_queue,out_NB_INST_ALL ,_param->_nb_context); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -344,4 +346,5 @@ DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context); DELETE1_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_DEPTH_FULL ,_param->_nb_context); DELETE1_SC_SIGNAL(out_NB_INST_ALL ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h (revision 101) @@ -119,4 +119,5 @@ public : SC_IN (Tdepth_t ) ** in_DEPTH_MIN ;//[nb_context] public : SC_IN (Tdepth_t ) ** in_DEPTH_MAX ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_DEPTH_FULL ;//[nb_context] // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue.cpp (revision 101) @@ -107,6 +107,9 @@ { if (_param->_have_port_depth) + { sensitive << (*(in_DEPTH_MIN [i])); sensitive << (*(in_DEPTH_MAX [i])); + } + sensitive << (*(in_DEPTH_FULL[i])); } @@ -119,6 +122,8 @@ { if (_param->_have_port_depth) + { (*(out_DECOD_OUT_VAL [i])) (*(in_DEPTH_MIN [j])); (*(out_DECOD_OUT_VAL [i])) (*(in_DEPTH_MAX [j])); + } } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp (revision 101) @@ -117,6 +117,7 @@ ALLOC1_INTERFACE("depth",IN ,NORTH,"Depth", _param->_nb_context); - ALLOC1_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth ); - ALLOC1_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth+1); + ALLOC1_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_IN ( in_DEPTH_FULL ,"full" ,Tcontrol_t ,1); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp (revision 101) @@ -77,6 +77,7 @@ DELETE1_SIGNAL(out_DECOD_OUT_EXCEPTION ,_param->_nb_inst_decod,_param->_size_exception ); - DELETE1_SIGNAL( in_DEPTH_MIN ,_param->_nb_context,_param->_size_depth ); - DELETE1_SIGNAL( in_DEPTH_MAX ,_param->_nb_context,_param->_size_depth+1); + DELETE1_SIGNAL( in_DEPTH_MIN ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL( in_DEPTH_MAX ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL( in_DEPTH_FULL ,_param->_nb_context,1); DELETE1_SIGNAL(out_NB_INST_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp (revision 101) @@ -42,11 +42,12 @@ Tdepth_t depth = reg_QUEUE->front()->_depth [i]; Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context]):0; - Tdepth_t depth_max = PORT_READ(in_DEPTH_MAX[context]); + Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX [context]):0; + Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL[context]); // is a valid instruction ? // If DEPTH_CURRENT : // equal at DEPTH_MIN -> not speculative - // not include ]DEPTH_MIN:DEPTH_MAX[ -> previous branch miss - // include ]DEPTH_MIN:DEPTH_MAX[ -> speculative + // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss + // include ]DEPTH_MIN:DEPTH_MAX] -> speculative // All case @@ -58,12 +59,22 @@ // ....... max ...X... min ....... KO - Tcontrol_t is_valid = ((depth == depth_min) or - ((depth_min < depth_max)? - (depth depth_min) or (depth < depth_max)))); + Tcontrol_t is_valid = ((depth == depth_min) or + depth_full or + ((depth_min <= depth_max)? + ((depth >= depth_min) and (depth <=depth_max)): + ((depth >= depth_min) or (depth <=depth_max)))); +// Tcontrol_t is_valid = ((depth == depth_min) or +// ((depth_min < depth_max)? +// (depth<=depth_max): +// ((depth > depth_min) or (depth <= depth_max)))); // Tcontrol_t is_valid = depth <= depth_max; - log_printf(TRACE,Decod_queue,FUNCTION,_(" * is_valid : %d"),is_valid); - + log_printf(TRACE,Decod_queue,FUNCTION," * is_valid : %d",is_valid); + log_printf(TRACE,Decod_queue,FUNCTION," * context : %d",context); + log_printf(TRACE,Decod_queue,FUNCTION," * depth : %d",depth); + log_printf(TRACE,Decod_queue,FUNCTION," * depth_min : %d",depth_min); + log_printf(TRACE,Decod_queue,FUNCTION," * depth_max : %d",depth_max); + log_printf(TRACE,Decod_queue,FUNCTION," * depth_full: %d",depth_full); + log_printf(TRACE,Decod_queue,FUNCTION," * address : 0x%x (0x%x)",reg_QUEUE->front()->_address[i],reg_QUEUE->front()->_address[i]<<2); internal_DECOD_OUT_VAL [i] = 1; // in all case, val is set (entry is not empty, and instruction is valid) if (is_valid) @@ -81,5 +92,5 @@ for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { - log_printf(TRACE,Decod_queue,FUNCTION,_(" * DECOD_OUT_VAL : %d"),val [i]); + log_printf(TRACE,Decod_queue,FUNCTION," * DECOD_OUT_VAL : %d",val [i]); PORT_WRITE(out_DECOD_OUT_VAL [i],val [i]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp (revision 101) @@ -135,5 +135,5 @@ { if ((*it)->_val [i]) - log_printf(TRACE,Decod_queue,FUNCTION," * [%d] %d, %d %d, %d %d %d %d, 0x%x, %d 0x%x, %d %d, %d %d, %d %d, %d %d, %d %d, %d %d" + log_printf(TRACE,Decod_queue,FUNCTION," * [%.4d] %.1d, %.3d %.2d, %.2d %.3d %.1d %.1d, 0x%.8x (0x%.8x), %.1d 0x%.8x, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d" ,i ,(*it)->_val [i] @@ -145,4 +145,5 @@ ,(*it)->_is_delay_slot [i] ,(*it)->_address [i] + ,(*it)->_address [i]<<2 ,(*it)->_has_immediat [i] ,(*it)->_immediat [i] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp (revision 101) @@ -104,8 +104,10 @@ ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_DEPTH_MAX ," in_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_DEPTH_FULL ," in_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,"out_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ," in_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH_VAL ," in_CONTEXT_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context); @@ -188,16 +190,17 @@ //INSTANCE1_SC_SIGNAL(_Decod_unit, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod); + if (_param->_have_port_depth) + { + INSTANCE1_SC_SIGNAL(_Decod_unit, in_DEPTH_MIN ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod_unit, in_DEPTH_MAX ,_param->_nb_context); - + } + INSTANCE1_SC_SIGNAL(_Decod_unit, in_DEPTH_FULL ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod_unit,out_NB_INST_DECOD_ALL ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod_unit, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context); - for (uint32_t i=0; i<_param->_nb_context; ++i) - if (_param->_have_port_depth) - { - INSTANCE_SC_SIGNAL(_Decod_unit, in_DEPTH_MIN [i]); - INSTANCE_SC_SIGNAL(_Decod_unit, in_CONTEXT_DEPTH [i]); - } + INSTANCE1_SC_SIGNAL(_Decod_unit, in_CONTEXT_DEPTH_VAL ,_param->_nb_context); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Decod_unit, in_CONTEXT_DEPTH ,_param->_nb_context); INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_VAL ); @@ -239,4 +242,7 @@ SC_START(5); in_NRESET->write(1); + + for (uint32_t i=0; i<_param->_nb_context; i++) + in_CONTEXT_DEPTH_VAL [i]->write(1); LABEL("Loop of Test"); @@ -515,8 +521,10 @@ DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context); DELETE1_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_DEPTH_FULL ,_param->_nb_context); DELETE1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context); DELETE1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_CONTEXT_DEPTH_VAL ,_param->_nb_context); DELETE1_SC_SIGNAL( in_CONTEXT_DEPTH ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h (revision 101) @@ -120,4 +120,5 @@ public : SC_IN (Tdepth_t ) ** in_DEPTH_MIN ;//[nb_context] public : SC_IN (Tdepth_t ) ** in_DEPTH_MAX ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_DEPTH_FULL ;//[nb_context] // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -126,4 +127,5 @@ // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ public : SC_IN (Tcontrol_t ) ** in_CONTEXT_DECOD_ENABLE ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_CONTEXT_DEPTH_VAL ;//[nb_context] public : SC_IN (Tdepth_t ) ** in_CONTEXT_DEPTH ;//[nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp (revision 101) @@ -128,6 +128,7 @@ ALLOC1_INTERFACE("depth",IN ,NORTH,"Depth", _param->_nb_context); - ALLOC1_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth ); - ALLOC1_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth+1); + ALLOC1_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_IN ( in_DEPTH_FULL ,"full" ,Tcontrol_t ,1); } @@ -144,4 +145,5 @@ ALLOC1_SIGNAL_IN (in_CONTEXT_DECOD_ENABLE,"decod_enable",Tcontrol_t,1); + ALLOC1_SIGNAL_IN (in_CONTEXT_DEPTH_VAL ,"depth_val" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN (in_CONTEXT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); } @@ -365,10 +367,12 @@ #ifdef POSITION - _component->interface_map (src ,"context"+toString(i), - dest,"context"+toString(i)); + _component->interface_map (src ,"context_"+toString(i), + dest,"context_"+toString(i)); #endif PORT_MAP(_component,src , "in_CONTEXT_"+toString(i)+"_DECOD_ENABLE", dest, "in_CONTEXT_"+toString(i)+"_DECOD_ENABLE"); + PORT_MAP(_component,src , "in_CONTEXT_"+toString(i)+"_DEPTH_VAL" , + dest, "in_CONTEXT_"+toString(i)+"_DEPTH_VAL" ); if (_param->_have_port_depth) PORT_MAP(_component,src , "in_CONTEXT_"+toString(i)+"_DEPTH" , @@ -516,8 +520,12 @@ if (_param->_have_port_depth) + { PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_MIN", dest, "in_DEPTH_"+toString(i)+"_MIN"); PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_MAX", dest, "in_DEPTH_"+toString(i)+"_MAX"); + } + PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_FULL", + dest, "in_DEPTH_"+toString(i)+"_FULL"); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp (revision 101) @@ -77,6 +77,7 @@ // DELETE1_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod,1 ); - DELETE1_SIGNAL( in_DEPTH_MIN ,_param->_nb_context,_param->_size_depth ); - DELETE1_SIGNAL( in_DEPTH_MAX ,_param->_nb_context,_param->_size_depth+1); + DELETE1_SIGNAL( in_DEPTH_MIN ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL( in_DEPTH_MAX ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL( in_DEPTH_FULL ,_param->_nb_context,1); DELETE1_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp (revision 101) @@ -91,11 +91,16 @@ ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_VAL ," in_DEPTH_PREDICTION_UNIT_VAL ",Tcontrol_t,_param->_nb_context); ALLOC1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_CURRENT ," in_DEPTH_PREDICTION_UNIT_CURRENT ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_MIN ," in_DEPTH_PREDICTION_UNIT_MIN ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_MAX ," in_DEPTH_PREDICTION_UNIT_MAX ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_FULL ," in_DEPTH_PREDICTION_UNIT_FULL ",Tcontrol_t,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_CONTEXT_STATE_MIN ,"out_DEPTH_CONTEXT_STATE_MIN ",Tdepth_t ,_param->_nb_context); ALLOC2_SC_SIGNAL(out_DEPTH_DECOD_UNIT_MIN ,"out_DEPTH_DECOD_UNIT_MIN ",Tdepth_t ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); ALLOC2_SC_SIGNAL(out_DEPTH_DECOD_UNIT_MAX ,"out_DEPTH_DECOD_UNIT_MAX ",Tdepth_t ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); - + ALLOC2_SC_SIGNAL(out_DEPTH_DECOD_UNIT_FULL ,"out_DEPTH_DECOD_UNIT_FULL ",Tcontrol_t,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + ALLOC2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH_VAL ,"out_CONTEXT_DECOD_UNIT_DEPTH_VAL ",Tcontrol_t,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); ALLOC2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH ,"out_CONTEXT_DECOD_UNIT_DEPTH ",Tdepth_t ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); @@ -153,16 +158,20 @@ INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_DEPTH ,_param->_nb_context); - for (uint32_t i=0; i<_param->_nb_context; ++i) - if (_param->_have_port_depth) - { - INSTANCE_SC_SIGNAL(_Front_end_Glue,out_DEPTH_MIN [i]); - INSTANCE_SC_SIGNAL(_Front_end_Glue, in_DEPTH_PREDICTION_UNIT_CURRENT [i]); - INSTANCE_SC_SIGNAL(_Front_end_Glue, in_DEPTH_PREDICTION_UNIT_MIN [i]); - INSTANCE_SC_SIGNAL(_Front_end_Glue,out_DEPTH_CONTEXT_STATE_MIN [i]); - } + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_DEPTH_PREDICTION_UNIT_VAL ,_param->_nb_context); + if (_param->_have_port_depth) + { + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_DEPTH_MIN ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_DEPTH_PREDICTION_UNIT_CURRENT ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_DEPTH_PREDICTION_UNIT_MIN ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_DEPTH_CONTEXT_STATE_MIN ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_DEPTH_MAX ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_DEPTH_PREDICTION_UNIT_MAX ,_param->_nb_context); INSTANCE2_SC_SIGNAL(_Front_end_Glue,out_DEPTH_DECOD_UNIT_MAX ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); - + } + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_DEPTH_FULL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_DEPTH_PREDICTION_UNIT_FULL ,_param->_nb_context); + INSTANCE2_SC_SIGNAL(_Front_end_Glue,out_DEPTH_DECOD_UNIT_FULL ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + INSTANCE2_SC_SIGNAL(_Front_end_Glue,out_CONTEXT_DECOD_UNIT_DEPTH_VAL ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); for (uint32_t i=0; i<_param->_nb_decod_unit; ++i) for (uint32_t j=0; j<_param->_decod_unit_nb_context [i]; ++j) @@ -259,12 +268,17 @@ DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context); DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_DEPTH_FULL ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_VAL ,_param->_nb_context); DELETE1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_CURRENT ,_param->_nb_context); DELETE1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_MIN ,_param->_nb_context); DELETE1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_MAX ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_FULL ,_param->_nb_context); DELETE1_SC_SIGNAL(out_DEPTH_CONTEXT_STATE_MIN ,_param->_nb_context); + DELETE2_SC_SIGNAL(out_DEPTH_DECOD_UNIT_MIN ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); DELETE2_SC_SIGNAL(out_DEPTH_DECOD_UNIT_MAX ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); - DELETE2_SC_SIGNAL(out_DEPTH_DECOD_UNIT_MIN ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); - + DELETE2_SC_SIGNAL(out_DEPTH_DECOD_UNIT_FULL ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + DELETE2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH_VAL ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); DELETE2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h (revision 101) @@ -115,16 +115,21 @@ public : SC_OUT(Tdepth_t ) ** out_DEPTH_MIN ;//[nb_context] public : SC_OUT(Tdepth_t ) ** out_DEPTH_MAX ;//[nb_context] - + public : SC_OUT(Tcontrol_t ) ** out_DEPTH_FULL ;//[nb_context] + + public : SC_IN (Tcontrol_t ) ** in_DEPTH_PREDICTION_UNIT_VAL ;//[nb_context] public : SC_IN (Tdepth_t ) ** in_DEPTH_PREDICTION_UNIT_CURRENT ;//[nb_context] public : SC_IN (Tdepth_t ) ** in_DEPTH_PREDICTION_UNIT_MIN ;//[nb_context] public : SC_IN (Tdepth_t ) ** in_DEPTH_PREDICTION_UNIT_MAX ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_DEPTH_PREDICTION_UNIT_FULL ;//[nb_context] //public : SC_OUT(Tdepth_t ) *** out_DEPTH_DECOD_UNIT_CURRENT ;//[nb_decod_unit][nb_decod_unit_context] public : SC_OUT(Tdepth_t ) *** out_DEPTH_DECOD_UNIT_MIN ;//[nb_decod_unit][nb_decod_unit_context] public : SC_OUT(Tdepth_t ) *** out_DEPTH_DECOD_UNIT_MAX ;//[nb_decod_unit][nb_decod_unit_context] + public : SC_OUT(Tcontrol_t ) *** out_DEPTH_DECOD_UNIT_FULL ;//[nb_decod_unit][nb_decod_unit_context] public : SC_OUT(Tdepth_t ) ** out_DEPTH_CONTEXT_STATE_MIN ;//[nb_context] // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) *** out_CONTEXT_DECOD_UNIT_DEPTH_VAL ;//[nb_decod_unit][nb_decod_unit_context] public : SC_OUT(Tdepth_t ) *** out_CONTEXT_DECOD_UNIT_DEPTH ;//[nb_decod_unit][nb_decod_unit_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp (revision 101) @@ -165,7 +165,9 @@ if (_param->_have_port_depth) sensitive << (*( in_DEPTH_PREDICTION_UNIT_CURRENT [i])) - << (*( in_DEPTH_PREDICTION_UNIT_MIN [i])); - - sensitive << (*( in_DEPTH_PREDICTION_UNIT_MAX [i])); + << (*( in_DEPTH_PREDICTION_UNIT_MIN [i])) + << (*( in_DEPTH_PREDICTION_UNIT_MAX [i])); + + sensitive << (*( in_DEPTH_PREDICTION_UNIT_VAL [i])) + << (*( in_DEPTH_PREDICTION_UNIT_FULL [i])); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp (revision 101) @@ -128,9 +128,12 @@ // ALLOC1_SIGNAL_OUT (out_DEPTH_CURRENT ,"CURRENT" ,Tdepth_t ,_param->_size_depth ); ALLOC1_SIGNAL_OUT (out_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth ); - ALLOC1_SIGNAL_OUT (out_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth+1); + ALLOC1_SIGNAL_OUT (out_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_OUT (out_DEPTH_FULL ,"FULL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_DEPTH_PREDICTION_UNIT_VAL ,"PREDICTION_UNIT_VAL" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_DEPTH_PREDICTION_UNIT_CURRENT ,"PREDICTION_UNIT_CURRENT" ,Tdepth_t ,_param->_size_depth ); ALLOC1_SIGNAL_IN ( in_DEPTH_PREDICTION_UNIT_MIN ,"PREDICTION_UNIT_MIN" ,Tdepth_t ,_param->_size_depth ); - ALLOC1_SIGNAL_IN ( in_DEPTH_PREDICTION_UNIT_MAX ,"PREDICTION_UNIT_MAX" ,Tdepth_t ,_param->_size_depth+1); + ALLOC1_SIGNAL_IN ( in_DEPTH_PREDICTION_UNIT_MAX ,"PREDICTION_UNIT_MAX" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_IN ( in_DEPTH_PREDICTION_UNIT_FULL ,"PREDICTION_UNIT_FULL" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT (out_DEPTH_CONTEXT_STATE_MIN ,"CONTEXT_STATE_MIN" ,Tdepth_t ,_param->_size_depth ); @@ -141,5 +144,6 @@ // _ALLOC2_SIGNAL_OUT(out_DEPTH_DECOD_UNIT_CURRENT ,"DECOD_UNIT_CURRENT" ,Tdepth_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); _ALLOC2_SIGNAL_OUT(out_DEPTH_DECOD_UNIT_MIN ,"DECOD_UNIT_MIN" ,Tdepth_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); - _ALLOC2_SIGNAL_OUT(out_DEPTH_DECOD_UNIT_MAX ,"DECOD_UNIT_MAX" ,Tdepth_t ,_param->_size_depth+1,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + _ALLOC2_SIGNAL_OUT(out_DEPTH_DECOD_UNIT_MAX ,"DECOD_UNIT_MAX" ,Tdepth_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + _ALLOC2_SIGNAL_OUT(out_DEPTH_DECOD_UNIT_FULL ,"DECOD_UNIT_FULL" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); } @@ -148,4 +152,5 @@ ALLOC2_INTERFACE("context",OUT,EAST,_("context"),_param->_nb_decod_unit,_param->_translate_context_id_from_decod_unit[it1].size()); + _ALLOC2_SIGNAL_OUT(out_CONTEXT_DECOD_UNIT_DEPTH_VAL ,"DECOD_UNIT_DEPTH_VAL" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); _ALLOC2_SIGNAL_OUT(out_CONTEXT_DECOD_UNIT_DEPTH ,"DECOD_UNIT_DEPTH" ,Tdepth_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp (revision 101) @@ -70,15 +70,20 @@ DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_DEPTH ,_param->_nb_context,_param->_size_depth); - DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth ); - DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth+1); - DELETE1_SIGNAL( in_DEPTH_PREDICTION_UNIT_CURRENT ,_param->_nb_context,_param->_size_depth ); - DELETE1_SIGNAL( in_DEPTH_PREDICTION_UNIT_MIN ,_param->_nb_context,_param->_size_depth ); - DELETE1_SIGNAL( in_DEPTH_PREDICTION_UNIT_MAX ,_param->_nb_context,_param->_size_depth+1); - DELETE1_SIGNAL(out_DEPTH_CONTEXT_STATE_MIN ,_param->_nb_context,_param->_size_depth ); + DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL(out_DEPTH_FULL ,_param->_nb_context,1); + DELETE1_SIGNAL( in_DEPTH_PREDICTION_UNIT_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL( in_DEPTH_PREDICTION_UNIT_CURRENT ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL( in_DEPTH_PREDICTION_UNIT_MIN ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL( in_DEPTH_PREDICTION_UNIT_MAX ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL( in_DEPTH_PREDICTION_UNIT_FULL ,_param->_nb_context,1); + DELETE1_SIGNAL(out_DEPTH_CONTEXT_STATE_MIN ,_param->_nb_context,_param->_size_depth); -// DELETE2_SIGNAL(out_DEPTH_DECOD_UNIT_CURRENT ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth ); - DELETE2_SIGNAL(out_DEPTH_DECOD_UNIT_MIN ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth ); - DELETE2_SIGNAL(out_DEPTH_DECOD_UNIT_MAX ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth+1); +// DELETE2_SIGNAL(out_DEPTH_DECOD_UNIT_CURRENT ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth); + DELETE2_SIGNAL(out_DEPTH_DECOD_UNIT_MIN ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth); + DELETE2_SIGNAL(out_DEPTH_DECOD_UNIT_MAX ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth); + DELETE2_SIGNAL(out_DEPTH_DECOD_UNIT_FULL ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],1); + DELETE2_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH_VAL ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],1); DELETE2_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_depth.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_depth.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_depth.cpp (revision 101) @@ -26,10 +26,10 @@ if (_param->_have_port_depth) { - Tdepth_t min = PORT_READ(in_DEPTH_PREDICTION_UNIT_MIN [i]); - PORT_WRITE(out_DEPTH_CONTEXT_STATE_MIN [i],min); - PORT_WRITE(out_DEPTH_MIN [i],min); + Tdepth_t min = PORT_READ(in_DEPTH_PREDICTION_UNIT_MIN [i]); + PORT_WRITE(out_DEPTH_CONTEXT_STATE_MIN [i],min); + PORT_WRITE(out_DEPTH_MIN [i],min); + PORT_WRITE(out_DEPTH_MAX [i], PORT_READ(in_DEPTH_PREDICTION_UNIT_MAX [i])); } - - PORT_WRITE(out_DEPTH_MAX [i], PORT_READ(in_DEPTH_PREDICTION_UNIT_MAX [i])); + PORT_WRITE(out_DEPTH_FULL [i], PORT_READ(in_DEPTH_PREDICTION_UNIT_FULL [i])); } @@ -39,10 +39,12 @@ uint32_t num_context = _param->_translate_context_id_from_decod_unit[i][j]; + PORT_WRITE(out_CONTEXT_DECOD_UNIT_DEPTH_VAL [i][j], PORT_READ(in_DEPTH_PREDICTION_UNIT_VAL [num_context])); if (_param->_have_port_depth) { - PORT_WRITE(out_CONTEXT_DECOD_UNIT_DEPTH [i][j], PORT_READ(in_DEPTH_PREDICTION_UNIT_CURRENT [num_context])); - PORT_WRITE(out_DEPTH_DECOD_UNIT_MIN [i][j], PORT_READ(in_DEPTH_PREDICTION_UNIT_MIN [num_context])); + PORT_WRITE(out_CONTEXT_DECOD_UNIT_DEPTH [i][j], PORT_READ(in_DEPTH_PREDICTION_UNIT_CURRENT [num_context])); + PORT_WRITE(out_DEPTH_DECOD_UNIT_MIN [i][j], PORT_READ(in_DEPTH_PREDICTION_UNIT_MIN [num_context])); + PORT_WRITE(out_DEPTH_DECOD_UNIT_MAX [i][j], PORT_READ(in_DEPTH_PREDICTION_UNIT_MAX [num_context])); } - PORT_WRITE(out_DEPTH_DECOD_UNIT_MAX [i][j], PORT_READ(in_DEPTH_PREDICTION_UNIT_MAX [num_context])); + PORT_WRITE(out_DEPTH_DECOD_UNIT_FULL [i][j], PORT_READ(in_DEPTH_PREDICTION_UNIT_FULL [num_context])); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp (revision 101) @@ -67,4 +67,5 @@ ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); +//ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_IS_CURRENT ," in_PREDICT_BRANCH_IS_CURRENT ",Tcontrol_t ); ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); @@ -104,4 +105,5 @@ if (_param->_have_port_inst_ifetch_ptr) INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR ); +//INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_IS_CURRENT ); INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE ); if (_param->_have_port_depth) @@ -129,7 +131,7 @@ srand(seed); - const int32_t percent_transaction_address = 75; - const int32_t percent_transaction_predict = 75; - const int32_t percent_transaction_event = 5; + const int32_t percent_transaction_address = 100; + const int32_t percent_transaction_predict = 100; + const int32_t percent_transaction_event = 0; SC_START(0); @@ -155,22 +157,26 @@ uint32_t nb_packet = 1; + Tcontrol_t a_val = false; Tcontrol_t c_val = false; - Tcontrol_t n_val = false; + Tcontrol_t n_val = true ; Tcontrol_t nn_val = false; + Tgeneral_data_t a_addr = 0x100>>2; Tgeneral_data_t c_addr = 0x100>>2; Tgeneral_data_t n_addr = 0x100>>2; Tgeneral_data_t nn_addr = 0x100>>2; + Tcontrol_t a_enable [_param->_nb_instruction]; Tcontrol_t c_enable [_param->_nb_instruction]; Tcontrol_t n_enable [_param->_nb_instruction]; + Tcontrol_t a_is_ds_take = 0; Tcontrol_t c_is_ds_take = 0; Tcontrol_t n_is_ds_take = 0; Tcontrol_t nn_is_ds_take = 0; - c_enable [0] = 1; + n_enable [0] = 1; for (uint32_t i=1; i<_param->_nb_instruction; i++) - c_enable [i] = 0; + n_enable [i] = 0; LABEL("Send Reset"); @@ -216,4 +222,5 @@ in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take); in_PREDICT_INST_IFETCH_PTR ->write(0); +// in_PREDICT_BRANCH_IS_CURRENT ->write(0); in_PREDICT_BRANCH_STATE ->write(0); in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0); @@ -251,4 +258,6 @@ for (uint32_t i=0; i<_param->_nb_instruction; i++) n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read(); + + LABEL(" * nn_addr : %.8x",nn_addr); } @@ -256,9 +265,9 @@ { LABEL("ADDRESS : Transaction accepted"); - LABEL(" * address wait : %.8x",c_addr); - - TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),c_addr); + LABEL(" * address wait : %.8x",a_addr); + + TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),a_addr); for (uint32_t i=0; i<_param->_nb_instruction; i++) - TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),c_enable[i]); + TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),a_enable[i]); if (_param->_have_port_inst_ifetch_ptr) TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),0); @@ -267,27 +276,70 @@ TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0); - c_val = 0; + a_val = 0; nb_packet ++; } + { + string str_a_enable = ""; + string str_c_enable = ""; + string str_n_enable = ""; + + for (uint32_t i=0; i<_param->_nb_instruction; i++) + { + str_a_enable += " " + toString(a_enable [i]); + str_c_enable += " " + toString(c_enable [i]); + str_n_enable += " " + toString(n_enable [i]); + } + + LABEL("----[ Before ]---------------------"); + LABEL(" * nb_packet : %d",nb_packet); + LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str()); + LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str()); + LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str()); + LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr); + LABEL("-----------------------------------"); + } + + if (not a_val) + { + if (c_val and n_val and nn_val) + { + a_val = 1; + c_val = 0; + a_addr = c_addr; + a_is_ds_take = c_is_ds_take; + + for (uint32_t i=0; i<_param->_nb_instruction; i++) + a_enable [i] = c_enable [i]; + } + } if (not c_val) - { - if (n_val and nn_val) - { - c_val = 1; - c_addr = n_addr; - c_is_ds_take = n_is_ds_take; - - for (uint32_t i=0; i<_param->_nb_instruction; i++) - c_enable [i] = n_enable [i]; - - n_val = 1; - n_addr = nn_addr; - n_is_ds_take = nn_is_ds_take; - - nn_val = 0; - } - } + { + c_val = n_val; + if (n_val) + { + c_addr = n_addr; + c_is_ds_take = n_is_ds_take; + + for (uint32_t i=0; i<_param->_nb_instruction; i++) + c_enable [i] = n_enable [i]; + } + n_val = 0; + } + + if (not n_val) + { + n_val = nn_val; + if (nn_val) + { + n_addr = nn_addr; + n_is_ds_take = nn_is_ds_take; + +// for (uint32_t i=0; i<_param->_nb_instruction; i++) +// n_enable [i] = nn_enable [i]; + } + nn_val = 0; + } if (in_EVENT_VAL->read() and out_EVENT_ACK->read()) @@ -295,4 +347,5 @@ LABEL("EVENT : Transaction accepted"); + a_val = false; c_val = false; n_val = true; @@ -312,4 +365,5 @@ { + string str_a_enable = ""; string str_c_enable = ""; string str_n_enable = ""; @@ -317,20 +371,15 @@ for (uint32_t i=0; i<_param->_nb_instruction; i++) { + str_a_enable += " " + toString(a_enable [i]); str_c_enable += " " + toString(c_enable [i]); str_n_enable += " " + toString(n_enable [i]); } - LABEL("-----------------------------------"); + LABEL("----[ After ]----------------------"); LABEL(" * nb_packet : %d",nb_packet); - LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take , c_addr ,str_c_enable.c_str()); - if (nn_val) - { - LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take , n_addr ,str_n_enable.c_str()); - } - else - { - LABEL(" * pc+4 : %d %d %.8x" ,n_val ,n_is_ds_take , n_addr ); - } - LABEL(" * pc+8 : %d %d %.8x" ,nn_val ,nn_is_ds_take, nn_addr); + LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str()); + LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str()); + LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str()); + LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr); LABEL("-----------------------------------"); } @@ -368,4 +417,5 @@ delete [] in_PREDICT_INSTRUCTION_ENABLE ; delete in_PREDICT_INST_IFETCH_PTR ; +//delete in_PREDICT_BRANCH_IS_CURRENT ; delete in_PREDICT_BRANCH_STATE ; delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h (revision 101) @@ -83,7 +83,8 @@ public : SC_IN (Tcontrol_t ) * in_PREDICT_PC_NEXT_IS_DS_TAKE ; public : SC_IN (Tcontrol_t ) ** in_PREDICT_INSTRUCTION_ENABLE ; //[nb_instruction] - public : SC_IN (Tinst_ifetch_ptr_t ) * in_PREDICT_INST_IFETCH_PTR ; +//public : SC_IN (Tcontrol_t ) * in_PREDICT_BRANCH_IS_CURRENT ; public : SC_IN (Tbranch_state_t ) * in_PREDICT_BRANCH_STATE ; public : SC_IN (Tprediction_ptr_t ) * in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ; + public : SC_IN (Tinst_ifetch_ptr_t ) * in_PREDICT_INST_IFETCH_PTR ; // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -98,4 +99,12 @@ // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : Tcontrol_t reg_PC_ACCESS_VAL ; + private : Tgeneral_address_t reg_PC_ACCESS ; + private : Tcontrol_t reg_PC_ACCESS_IS_DS_TAKE ; + private : Tcontrol_t * reg_PC_ACCESS_INSTRUCTION_ENABLE ; //[nb_instruction] + private : Tinst_ifetch_ptr_t reg_PC_ACCESS_INST_IFETCH_PTR ; + private : Tbranch_state_t reg_PC_ACCESS_BRANCH_STATE ; + private : Tprediction_ptr_t reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID ; + private : Tcontrol_t reg_PC_CURRENT_VAL ; private : Tgeneral_address_t reg_PC_CURRENT ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp (revision 101) @@ -85,7 +85,8 @@ ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address); ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); +// ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_IS_CURRENT ,"branch_is_current" ,Tcontrol_t ,1); ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); + ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); } { @@ -110,6 +111,7 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - reg_PC_CURRENT_INSTRUCTION_ENABLE = new Tcontrol_t [_param->_nb_instruction]; - reg_PC_NEXT_INSTRUCTION_ENABLE = new Tcontrol_t [_param->_nb_instruction]; + ALLOC1(reg_PC_ACCESS_INSTRUCTION_ENABLE ,Tcontrol_t,_param->_nb_instruction); + ALLOC1(reg_PC_CURRENT_INSTRUCTION_ENABLE,Tcontrol_t,_param->_nb_instruction); + ALLOC1(reg_PC_NEXT_INSTRUCTION_ENABLE ,Tcontrol_t,_param->_nb_instruction); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp (revision 101) @@ -47,4 +47,5 @@ if (_param->_have_port_inst_ifetch_ptr) delete in_PREDICT_INST_IFETCH_PTR ; +// delete in_PREDICT_BRANCH_IS_CURRENT ; delete in_PREDICT_BRANCH_STATE ; if (_param->_have_port_depth) @@ -60,4 +61,5 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { + delete reg_PC_ACCESS_INSTRUCTION_ENABLE ; delete reg_PC_CURRENT_INSTRUCTION_ENABLE; delete reg_PC_NEXT_INSTRUCTION_ENABLE ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp (revision 101) @@ -28,16 +28,16 @@ // ========================================= - internal_ADDRESS_VAL = reg_PC_CURRENT_VAL; + internal_ADDRESS_VAL = reg_PC_ACCESS_VAL; PORT_WRITE(out_ADDRESS_VAL ,internal_ADDRESS_VAL ); - PORT_WRITE(out_ADDRESS_INSTRUCTION_ADDRESS ,reg_PC_CURRENT ); + PORT_WRITE(out_ADDRESS_INSTRUCTION_ADDRESS ,reg_PC_ACCESS ); if (_param->_have_port_inst_ifetch_ptr) - PORT_WRITE(out_ADDRESS_INST_IFETCH_PTR ,reg_PC_CURRENT_INST_IFETCH_PTR ); - PORT_WRITE(out_ADDRESS_BRANCH_STATE ,reg_PC_CURRENT_BRANCH_STATE ); + PORT_WRITE(out_ADDRESS_INST_IFETCH_PTR ,reg_PC_ACCESS_INST_IFETCH_PTR ); + PORT_WRITE(out_ADDRESS_BRANCH_STATE ,reg_PC_ACCESS_BRANCH_STATE ); if (_param->_have_port_depth) - PORT_WRITE(out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID); + PORT_WRITE(out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID); for (uint32_t i=0; i<_param->_nb_instruction; i++) - PORT_WRITE(out_ADDRESS_INSTRUCTION_ENABLE [i], reg_PC_CURRENT_INSTRUCTION_ENABLE[i]); + PORT_WRITE(out_ADDRESS_INSTRUCTION_ENABLE [i], reg_PC_ACCESS_INSTRUCTION_ENABLE[i]); // ========================================= Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp (revision 101) @@ -28,8 +28,18 @@ { // nothing is valid + reg_PC_ACCESS_VAL = 0; + reg_PC_CURRENT_VAL = 0; reg_PC_NEXT_VAL = 1; reg_PC_NEXT = 0x100>>2; + reg_PC_NEXT_IS_DS_TAKE = 0; + reg_PC_NEXT_INSTRUCTION_ENABLE [0] = 1; + for (uint32_t i=1; i<_param->_nb_instruction; i++) + reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; + reg_PC_NEXT_INST_IFETCH_PTR = 0; + reg_PC_NEXT_BRANCH_STATE = 0; + reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; + reg_PC_NEXT_NEXT_VAL = 0; @@ -42,11 +52,24 @@ if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL) { + bool branch_is_current = reg_PC_NEXT_IS_DS_TAKE; + if (branch_is_current) + { + if (_param->_have_port_inst_ifetch_ptr) + reg_PC_CURRENT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); + reg_PC_CURRENT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); + if (_param->_have_port_depth) + reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); + } + else + { + if (_param->_have_port_inst_ifetch_ptr) + reg_PC_NEXT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); + reg_PC_NEXT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); + if (_param->_have_port_depth) + reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); + } + for (uint32_t i=0; i<_param->_nb_instruction; i++) reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]); - if (_param->_have_port_inst_ifetch_ptr) - reg_PC_NEXT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); - reg_PC_NEXT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); - if (_param->_have_port_depth) - reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); reg_PC_NEXT_NEXT_VAL = 1; // address is valid @@ -64,50 +87,73 @@ // ========================================= // transaction with icache - if ( (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) or not reg_PC_CURRENT_VAL) - { + if (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) + { + reg_PC_ACCESS_VAL = 0; #ifdef STATISTICS if (usage_is_set(_usage,USE_STATISTICS)) - if (reg_PC_CURRENT_VAL) - { + { (*_stat_nb_transaction_address) ++; for (uint32_t i=0; i<_param->_nb_instruction; i++) - if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true) + if (reg_PC_ACCESS_INSTRUCTION_ENABLE [i] == true) (*_stat_sum_packet_size) ++; } #endif - - - Tcontrol_t pc_next_val = reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL; - - // next pc became current pc - reg_PC_CURRENT_VAL = pc_next_val; - - // if pc_next is not valid : don't erase PC and PC_IS_DS_TAKE : this register is send a the predict (to compute pc_next) - if (pc_next_val) - { - reg_PC_CURRENT = reg_PC_NEXT ; - reg_PC_CURRENT_IS_DS_TAKE = reg_PC_NEXT_IS_DS_TAKE ; - reg_PC_CURRENT_INST_IFETCH_PTR = reg_PC_NEXT_INST_IFETCH_PTR ; - reg_PC_CURRENT_BRANCH_STATE = reg_PC_NEXT_BRANCH_STATE ; - reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID; - - for (uint32_t i=0; i<_param->_nb_instruction; i++) - reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i]; - - reg_PC_NEXT_VAL = reg_PC_NEXT_NEXT_VAL ; - // if pc_next_next is not valid : don't erase PC_NEXT and PC_NEXT_IS_DS_TAKE : this register is send a the predict (to compute pc_next) - if (reg_PC_NEXT_NEXT_VAL) - { - reg_PC_NEXT = reg_PC_NEXT_NEXT ; - reg_PC_NEXT_IS_DS_TAKE = reg_PC_NEXT_NEXT_IS_DS_TAKE; - } - - // invalid next next pc - reg_PC_NEXT_NEXT_VAL = 0; - } - - } - + } + + // Shift register + + if (not reg_PC_ACCESS_VAL and reg_PC_CURRENT_VAL and reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL) + { + reg_PC_ACCESS_VAL = 1; // new request + reg_PC_CURRENT_VAL = 0; // invalid current + + reg_PC_ACCESS = reg_PC_CURRENT ; + reg_PC_ACCESS_IS_DS_TAKE = reg_PC_CURRENT_IS_DS_TAKE ; + reg_PC_ACCESS_INST_IFETCH_PTR = reg_PC_CURRENT_INST_IFETCH_PTR ; + reg_PC_ACCESS_BRANCH_STATE = reg_PC_CURRENT_BRANCH_STATE ; + reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID = reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID; + + for (uint32_t i=0; i<_param->_nb_instruction; i++) + reg_PC_ACCESS_INSTRUCTION_ENABLE [i] = reg_PC_CURRENT_INSTRUCTION_ENABLE [i]; + } + + if (not reg_PC_CURRENT_VAL) + { + bool val = reg_PC_NEXT_VAL; + reg_PC_CURRENT_VAL = val; // new PC_CURRENT if PC_NEXT is valid + reg_PC_NEXT_VAL = 0; // invalid next + + if (val) + { + reg_PC_CURRENT = reg_PC_NEXT ; + reg_PC_CURRENT_IS_DS_TAKE = reg_PC_NEXT_IS_DS_TAKE ; + reg_PC_CURRENT_INST_IFETCH_PTR = reg_PC_NEXT_INST_IFETCH_PTR ; + reg_PC_CURRENT_BRANCH_STATE = reg_PC_NEXT_BRANCH_STATE ; + reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID; + + for (uint32_t i=0; i<_param->_nb_instruction; i++) + reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i]; + } + } + + if (not reg_PC_NEXT_VAL) + { + bool val = reg_PC_NEXT_NEXT_VAL; + reg_PC_NEXT_VAL = val; // new PC_NEXT if PC_NEXT_NEXT is valid + reg_PC_NEXT_NEXT_VAL = 0; // invalid next_next + + if (val) + { + reg_PC_NEXT = reg_PC_NEXT_NEXT ; + reg_PC_NEXT_IS_DS_TAKE = reg_PC_NEXT_NEXT_IS_DS_TAKE ; +// reg_PC_NEXT_INST_IFETCH_PTR = reg_PC_NEXT_NEXT_INST_IFETCH_PTR ; +// reg_PC_NEXT_BRANCH_STATE = reg_PC_NEXT_NEXT_BRANCH_STATE ; +// reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID; + +// for (uint32_t i=0; i<_param->_nb_instruction; i++) +// reg_PC_NEXT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE [i]; + } + } // ========================================= @@ -121,4 +167,6 @@ log_printf(TRACE,Address_management,FUNCTION," * ADDRESS_NEXT : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS_NEXT ),PORT_READ(in_EVENT_ADDRESS_NEXT )<<2); log_printf(TRACE,Address_management,FUNCTION," * ADDRESS_NEXT_VAL : %d" ,PORT_READ(in_EVENT_ADDRESS_NEXT_VAL)); + + reg_PC_ACCESS_VAL = 0; reg_PC_CURRENT_VAL = 0; reg_PC_NEXT_VAL = 1; @@ -157,9 +205,58 @@ } -#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE) +#if defined(DEBUG) and DEBUG_Address_management and (DEBUG >= DEBUG_TRACE) log_printf(TRACE,Address_management,FUNCTION," * Dump PC"); - log_printf(TRACE,Address_management,FUNCTION," * Current : %d %d 0x%.8x (%.8x)",reg_PC_CURRENT_VAL , reg_PC_CURRENT_IS_DS_TAKE , reg_PC_CURRENT , reg_PC_CURRENT <<2); - log_printf(TRACE,Address_management,FUNCTION," * Next : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_VAL , reg_PC_NEXT_IS_DS_TAKE , reg_PC_NEXT , reg_PC_NEXT <<2); - log_printf(TRACE,Address_management,FUNCTION," * Next_Next : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT, reg_PC_NEXT_NEXT<<2); + { + std::string instruction_enable; + for (uint32_t i=0; i<_param->_nb_instruction; ++i) + instruction_enable += toString(reg_PC_ACCESS_INSTRUCTION_ENABLE [i])+ " "; + + log_printf(TRACE,Address_management,FUNCTION," * Access : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", + reg_PC_ACCESS_VAL, + reg_PC_ACCESS_IS_DS_TAKE, + reg_PC_ACCESS, + reg_PC_ACCESS<<2, + reg_PC_ACCESS_BRANCH_STATE, + reg_PC_ACCESS_INST_IFETCH_PTR, + reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID, + instruction_enable.c_str() + ); + } + { + std::string instruction_enable; + for (uint32_t i=0; i<_param->_nb_instruction; ++i) + instruction_enable += toString(reg_PC_CURRENT_INSTRUCTION_ENABLE [i])+ " "; + + log_printf(TRACE,Address_management,FUNCTION," * Current : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", + reg_PC_CURRENT_VAL, + reg_PC_CURRENT_IS_DS_TAKE, + reg_PC_CURRENT, + reg_PC_CURRENT<<2, + reg_PC_CURRENT_BRANCH_STATE, + reg_PC_CURRENT_INST_IFETCH_PTR, + reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID, + instruction_enable.c_str() + ); + } + { + std::string instruction_enable; + for (uint32_t i=0; i<_param->_nb_instruction; ++i) + instruction_enable += toString(reg_PC_NEXT_INSTRUCTION_ENABLE [i])+ " "; + + log_printf(TRACE,Address_management,FUNCTION," * Next : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", + reg_PC_NEXT_VAL, + reg_PC_NEXT_IS_DS_TAKE, + reg_PC_NEXT, + reg_PC_NEXT<<2, + reg_PC_NEXT_BRANCH_STATE, + reg_PC_NEXT_INST_IFETCH_PTR, + reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID, + instruction_enable.c_str()); + } + log_printf(TRACE,Address_management,FUNCTION," * Next_Next : %d %d 0x%.8x (%.8x)", + reg_PC_NEXT_NEXT_VAL, + reg_PC_NEXT_NEXT_IS_DS_TAKE, + reg_PC_NEXT_NEXT, + reg_PC_NEXT_NEXT<<2); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h (revision 101) @@ -22,5 +22,5 @@ { IFETCH_QUEUE_STATE_EMPTY , // slot is empty - //IFETCH_QUEUE_STATE_WAIT_REQ , // slot is allocated - wait request to cache +// IFETCH_QUEUE_STATE_WAIT_REQ , // slot is allocated - wait request to cache IFETCH_QUEUE_STATE_WAIT_RSP , // slot have send a request - wait respons from cache IFETCH_QUEUE_STATE_HAVE_RSP , // slot have a bloc of instruction - wait accept by decod Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp (revision 101) @@ -41,5 +41,5 @@ // New slot in ifetch_queue is allocated - _queue[reg_PTR_WRITE]->_state = IFETCH_QUEUE_STATE_WAIT_RSP; + _queue[reg_PTR_WRITE]->_state = IFETCH_QUEUE_STATE_WAIT_RSP; #ifdef STATISTICS @@ -58,7 +58,7 @@ } - _queue[reg_PTR_WRITE]->_address = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS ); + _queue[reg_PTR_WRITE]->_address = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS); _queue[reg_PTR_WRITE]->_inst_ifetch_ptr = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR ):0; - _queue[reg_PTR_WRITE]->_branch_state = PORT_READ(in_ADDRESS_BRANCH_STATE ); + _queue[reg_PTR_WRITE]->_branch_state = PORT_READ(in_ADDRESS_BRANCH_STATE); _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_depth)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0; @@ -142,8 +142,17 @@ for (uint32_t i=0; i<_param->_size_queue; i++) { - log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] %s %.8x %d - %d %d %d", i, toString(_queue [i]->_state).c_str(), _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception); + log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] 0x%.8x (0x%.8x) %d - %d %d %d - %s", + i, + _queue [i]->_address, + _queue [i]->_address<<2, + _queue [i]->_inst_ifetch_ptr, + _queue [i]->_branch_state, + _queue [i]->_branch_update_prediction_id, + _queue [i]->_exception, + toString(_queue [i]->_state).c_str() + ); for (uint32_t j=0; j<_param->_nb_instruction; j++) - log_printf(TRACE,Ifetch_queue,FUNCTION," * %d %.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]); + log_printf(TRACE,Ifetch_queue,FUNCTION," * %d 0x%.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]); } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp (revision 101) @@ -250,218 +250,218 @@ LABEL("Iteration %d",iteration); - // PREDICT - { - in_PREDICT_ACK ->write((rand()%100)write((rand()%100)read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read(); - - uint32_t begin = addr%_param->_nb_instruction; - uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1); - Tcontrol_t take = (nb_packet_in%jump)==0; +// SC_START(0); + +// Taddress_t addr = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read(); + +// uint32_t begin = addr%_param->_nb_instruction; +// uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1); +// Tcontrol_t take = (nb_packet_in%jump)==0; - if (take) - addr += 0x100; - else - addr += end-begin+1; - - for (uint32_t i=0; i<_param->_nb_instruction; i++) - in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); - in_PREDICT_PC_NEXT ->write(addr); - in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take); - in_PREDICT_INST_IFETCH_PTR ->write(0); - in_PREDICT_BRANCH_STATE ->write(0); - in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0); - } - - // DECOD - { - uint32_t nb_decod = (rand()%_param->_nb_instruction); - - for (uint32_t i=0; i<_param->_nb_instruction; i++) - in_DECOD_ACK [i]->write(i<=nb_decod); - } - - // EVENT - in_EVENT_VAL ->write((rand()%100)write(0x77); - in_EVENT_ADDRESS_NEXT ->write(0x171); - Tcontrol_t is_ds_take = rand(); - in_EVENT_ADDRESS_NEXT_VAL->write(is_ds_take); - in_EVENT_IS_DS_TAKE ->write(is_ds_take); - - // ICACHE_REQ - in_ICACHE_REQ_ACK->write((rand()%100)empty()) - { - slot_t cache_rsp = cache->read(); - - val = (cache_rsp._delay == 0); +// if (take) +// addr += 0x100; +// else +// addr += end-begin+1; + +// for (uint32_t i=0; i<_param->_nb_instruction; i++) +// in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); +// in_PREDICT_PC_NEXT ->write(addr); +// in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take); +// in_PREDICT_INST_IFETCH_PTR ->write(0); +// in_PREDICT_BRANCH_STATE ->write(0); +// in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0); +// } + +// // DECOD +// { +// uint32_t nb_decod = (rand()%_param->_nb_instruction); + +// for (uint32_t i=0; i<_param->_nb_instruction; i++) +// in_DECOD_ACK [i]->write(i<=nb_decod); +// } + +// // EVENT +// in_EVENT_VAL ->write((rand()%100)write(0x77); +// in_EVENT_ADDRESS_NEXT ->write(0x171); +// Tcontrol_t is_ds_take = rand(); +// in_EVENT_ADDRESS_NEXT_VAL->write(is_ds_take); +// in_EVENT_IS_DS_TAKE ->write(is_ds_take); + +// // ICACHE_REQ +// in_ICACHE_REQ_ACK->write((rand()%100)empty()) +// { +// slot_t cache_rsp = cache->read(); + +// val = (cache_rsp._delay == 0); - Tpacket_t packet = cache_rsp._data->packet ; - Taddress_t address = cache_rsp._data->address; +// Tpacket_t packet = cache_rsp._data->packet ; +// Taddress_t address = cache_rsp._data->address; - in_ICACHE_RSP_PACKET_ID ->write(packet); - for (uint32_t i=0; i<_param->_nb_instruction; i++) - in_ICACHE_RSP_INSTRUCTION [i]->write(address+i); - in_ICACHE_RSP_ERROR ->write(0); - } - - in_ICACHE_RSP_VAL->write(val); - } - - //------------------------------------------------- - SC_START(0); - //------------------------------------------------- - - if (out_ICACHE_REQ_VAL->read() and in_ICACHE_REQ_ACK->read()) - { - LABEL("ICACHE_REQ : Transaction accepted"); - - Tpacket_t packet = (_param->_have_port_ifetch_queue_ptr)?out_ICACHE_REQ_PACKET_ID->read():0; - Taddress_t address = out_ICACHE_REQ_ADDRESS->read(); - - TEST(bool ,slot_use[packet], false); - TEST(Taddress_t,address ,c_addr); - - slot_use[packet] = true; - - uint32_t delay; - if ((rand()%100)push(delay,cache_req); - - c_val = 0; - nb_packet_in ++; - } - - { - bool find=false; - - Taddress_t addr=out_DECOD_ADDRESS->read(); - for (uint32_t i=0; i<_param->_nb_instruction; i++) - if (out_DECOD_VAL[i]->read() and in_DECOD_ACK [i]->read()) - { - Tinstruction_t inst = out_DECOD_INSTRUCTION[i]->read(); - LABEL("DECOD [%d] : Transaction accepted",i); - LABEL(" address : 0x%x",addr); - LABEL(" instruction : 0x%x",inst); - - find = true; - TEST(Tinstruction_t,inst,addr+i); - } - - if (find) - { - if (_param->_have_port_inst_ifetch_ptr) - TEST(Tinst_ifetch_ptr_t, out_DECOD_INST_IFETCH_PTR ->read(), 0); - TEST(Tbranch_state_t , out_DECOD_BRANCH_STATE ->read(), 0); - if (_param->_have_port_depth) - TEST(Tprediction_ptr_t , out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(), 0); - TEST(Texception_t , out_DECOD_EXCEPTION ->read(), 0); - } - } +// in_ICACHE_RSP_PACKET_ID ->write(packet); +// for (uint32_t i=0; i<_param->_nb_instruction; i++) +// in_ICACHE_RSP_INSTRUCTION [i]->write(address+i); +// in_ICACHE_RSP_ERROR ->write(0); +// } + +// in_ICACHE_RSP_VAL->write(val); +// } + +// //------------------------------------------------- +// SC_START(0); +// //------------------------------------------------- + +// if (out_ICACHE_REQ_VAL->read() and in_ICACHE_REQ_ACK->read()) +// { +// LABEL("ICACHE_REQ : Transaction accepted"); + +// Tpacket_t packet = (_param->_have_port_ifetch_queue_ptr)?out_ICACHE_REQ_PACKET_ID->read():0; +// Taddress_t address = out_ICACHE_REQ_ADDRESS->read(); + +// TEST(bool ,slot_use[packet], false); +// TEST(Taddress_t,address ,c_addr); + +// slot_use[packet] = true; + +// uint32_t delay; +// if ((rand()%100)push(delay,cache_req); + +// c_val = 0; +// nb_packet_in ++; +// } + +// { +// bool find=false; + +// Taddress_t addr=out_DECOD_ADDRESS->read(); +// for (uint32_t i=0; i<_param->_nb_instruction; i++) +// if (out_DECOD_VAL[i]->read() and in_DECOD_ACK [i]->read()) +// { +// Tinstruction_t inst = out_DECOD_INSTRUCTION[i]->read(); +// LABEL("DECOD [%d] : Transaction accepted",i); +// LABEL(" address : 0x%x",addr); +// LABEL(" instruction : 0x%x",inst); + +// find = true; +// TEST(Tinstruction_t,inst,addr+i); +// } + +// if (find) +// { +// if (_param->_have_port_inst_ifetch_ptr) +// TEST(Tinst_ifetch_ptr_t, out_DECOD_INST_IFETCH_PTR ->read(), 0); +// TEST(Tbranch_state_t , out_DECOD_BRANCH_STATE ->read(), 0); +// if (_param->_have_port_depth) +// TEST(Tprediction_ptr_t , out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(), 0); +// TEST(Texception_t , out_DECOD_EXCEPTION ->read(), 0); +// } +// } - if (in_ICACHE_RSP_VAL->read() and out_ICACHE_RSP_ACK->read()) - { - LABEL("ICACHE_RSP : Transaction accepted"); - - slot_use[cache->read()._data->packet] = false; - - cache->pop(); - } - - if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) - { - LABEL("PREDICT : Transaction accepted"); - - if (c_val) - TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr ); - TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr ); - TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take); - - nn_val = true; - nn_addr = in_PREDICT_PC_NEXT ->read(); - nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read(); +// if (in_ICACHE_RSP_VAL->read() and out_ICACHE_RSP_ACK->read()) +// { +// LABEL("ICACHE_RSP : Transaction accepted"); + +// slot_use[cache->read()._data->packet] = false; + +// cache->pop(); +// } + +// if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) +// { +// LABEL("PREDICT : Transaction accepted"); + +// if (c_val) +// TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr ); +// TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr ); +// TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take); + +// nn_val = true; +// nn_addr = in_PREDICT_PC_NEXT ->read(); +// nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read(); - for (uint32_t i=0; i<_param->_nb_instruction; i++) - n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read(); - } - - if (not c_val) - { - if (n_val and nn_val) - { - c_val = 1; - c_addr = n_addr; - c_is_ds_take = n_is_ds_take; - - for (uint32_t i=0; i<_param->_nb_instruction; i++) - c_enable [i] = n_enable [i]; +// for (uint32_t i=0; i<_param->_nb_instruction; i++) +// n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read(); +// } + +// if (not c_val) +// { +// if (n_val and nn_val) +// { +// c_val = 1; +// c_addr = n_addr; +// c_is_ds_take = n_is_ds_take; + +// for (uint32_t i=0; i<_param->_nb_instruction; i++) +// c_enable [i] = n_enable [i]; - n_val = 1; - n_addr = nn_addr; - n_is_ds_take = nn_is_ds_take; +// n_val = 1; +// n_addr = nn_addr; +// n_is_ds_take = nn_is_ds_take; - nn_val = 0; - } - } - - if (in_EVENT_VAL->read() and out_EVENT_ACK->read()) - { - LABEL("EVENT : Transaction accepted"); - - c_val = false; - n_val = true; - - n_addr = in_EVENT_ADDRESS->read(); - n_is_ds_take = in_EVENT_IS_DS_TAKE->read(); - nn_val = in_EVENT_ADDRESS_NEXT_VAL->read(); - nn_addr = in_EVENT_ADDRESS_NEXT ->read(); - nn_is_ds_take = 0; - - n_enable [0] = 1; - for (uint32_t i=1; i<_param->_nb_instruction; i++) - n_enable [i] = 0; - } +// nn_val = 0; +// } +// } + +// if (in_EVENT_VAL->read() and out_EVENT_ACK->read()) +// { +// LABEL("EVENT : Transaction accepted"); + +// c_val = false; +// n_val = true; + +// n_addr = in_EVENT_ADDRESS->read(); +// n_is_ds_take = in_EVENT_IS_DS_TAKE->read(); +// nn_val = in_EVENT_ADDRESS_NEXT_VAL->read(); +// nn_addr = in_EVENT_ADDRESS_NEXT ->read(); +// nn_is_ds_take = 0; + +// n_enable [0] = 1; +// for (uint32_t i=1; i<_param->_nb_instruction; i++) +// n_enable [i] = 0; +// } - { - string str_c_enable = ""; - string str_n_enable = ""; - - for (uint32_t i=0; i<_param->_nb_instruction; i++) - { - str_c_enable += " " + toString(c_enable [i]); - str_n_enable += " " + toString(n_enable [i]); - } - - LABEL("-----------------------------------"); - LABEL(" * nb_packet_in : %d",nb_packet_in); - LABEL(" * nb_packet_out : %d",nb_packet_out); - LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take , c_addr ,str_c_enable.c_str()); - if (nn_val) - { - LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take , n_addr ,str_n_enable.c_str()); - } - else - { - LABEL(" * pc+4 : %d %d %.8x" ,n_val ,n_is_ds_take , n_addr ); - } - LABEL(" * pc+8 : %d %d %.8x" ,nn_val ,nn_is_ds_take, nn_addr); - LABEL("-----------------------------------"); - } - - SC_START(1); - cache->transition(); +// { +// string str_c_enable = ""; +// string str_n_enable = ""; + +// for (uint32_t i=0; i<_param->_nb_instruction; i++) +// { +// str_c_enable += " " + toString(c_enable [i]); +// str_n_enable += " " + toString(n_enable [i]); +// } + +// LABEL("-----------------------------------"); +// LABEL(" * nb_packet_in : %d",nb_packet_in); +// LABEL(" * nb_packet_out : %d",nb_packet_out); +// LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take , c_addr ,str_c_enable.c_str()); +// if (nn_val) +// { +// LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take , n_addr ,str_n_enable.c_str()); +// } +// else +// { +// LABEL(" * pc+4 : %d %d %.8x" ,n_val ,n_is_ds_take , n_addr ); +// } +// LABEL(" * pc+8 : %d %d %.8x" ,nn_val ,nn_is_ds_take, nn_addr); +// LABEL("-----------------------------------"); +// } + +// SC_START(1); +// cache->transition(); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h (revision 101) @@ -90,7 +90,7 @@ public : SC_IN (Tcontrol_t ) * in_PREDICT_PC_NEXT_IS_DS_TAKE ; public : SC_IN (Tcontrol_t ) ** in_PREDICT_INSTRUCTION_ENABLE ; //[nb_instruction] - public : SC_IN (Tinst_ifetch_ptr_t ) * in_PREDICT_INST_IFETCH_PTR ; public : SC_IN (Tbranch_state_t ) * in_PREDICT_BRANCH_STATE ; public : SC_IN (Tprediction_ptr_t ) * in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ; + public : SC_IN (Tinst_ifetch_ptr_t ) * in_PREDICT_INST_IFETCH_PTR ; // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp (revision 101) @@ -151,5 +151,5 @@ // Branch is the last slot : next paquet is the delay slot - pc_next = address_src+1; // sequencial + pc_next = address_src+1; // sequential pc_next_is_ds_take = 1; address_msb = _param->_nb_instruction [context]; // == (address_src_lsb+1) @@ -341,5 +341,5 @@ // Take the address packet base and add new packet - pc_next = pc_current-address_lsb+_param->_nb_instruction [context]; // sequencial + pc_next = pc_current-address_lsb+_param->_nb_instruction [context]; // sequential pc_next_is_ds_take = 0; // no branch, also no delay slot inst_ifetch_ptr = 0; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp (revision 101) @@ -99,7 +99,9 @@ ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_VAL ,"out_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context); /******************************************************** @@ -170,6 +172,8 @@ INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_CURRENT ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_MIN ,_param->_nb_context); - } INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_MAX ,_param->_nb_context); + } + INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_FULL ,_param->_nb_context); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -372,7 +376,9 @@ DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_DEPTH_VAL ,_param->_nb_context); DELETE1_SC_SIGNAL(out_DEPTH_CURRENT ,_param->_nb_context); DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context); DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_DEPTH_FULL ,_param->_nb_context); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 101) @@ -143,7 +143,9 @@ ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_VAL ,"out_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context); /******************************************************** @@ -239,6 +241,8 @@ INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MAX ,_param->_nb_context); } - INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MAX ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_FULL ,_param->_nb_context); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -373,7 +377,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); - + } SC_START(0); // fct melay @@ -404,6 +409,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -462,6 +469,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -490,6 +499,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } SC_START(0); @@ -516,6 +527,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -539,6 +552,8 @@ // if (_param->_have_port_depth) +// { // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); +// } SC_START(0); @@ -654,7 +669,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); - + } SC_START(0); // fct melay @@ -685,6 +701,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -764,6 +782,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -793,7 +813,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); - + } SC_START(0); @@ -819,6 +840,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -1013,7 +1036,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); - + } SC_START(0); // fct melay @@ -1044,6 +1068,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -1123,6 +1149,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -1152,7 +1180,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); - + } SC_START(0); @@ -1178,6 +1207,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -1450,7 +1481,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); - + } SC_START(0); // fct melay @@ -1481,6 +1513,8 @@ if (_param->_have_port_depth) - TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); + { + TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -1541,6 +1575,8 @@ if (_param->_have_port_depth) - TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); + { + TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -1593,7 +1629,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); - + } SC_START(0); // fct melay @@ -1624,6 +1661,8 @@ if (_param->_have_port_depth) - TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); + { + TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -1677,7 +1716,9 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); - + } + SC_START(0); @@ -1711,6 +1752,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -1738,7 +1781,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); - + } SC_START(0); @@ -1772,6 +1816,8 @@ if (_param->_have_port_depth) + { TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } } } @@ -2176,7 +2222,9 @@ // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete [] out_DEPTH_VAL; delete [] out_DEPTH_CURRENT; delete [] out_DEPTH_MIN; delete [] out_DEPTH_MAX; + delete [] out_DEPTH_FULL; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h (revision 101) @@ -26,5 +26,5 @@ EVENT_STATE_FLUSH_UPT , // in commit stage, detect a miss, context is stop and ufpt is flush, update RAS EVENT_STATE_UPDATE_CONTEXT , // prediction unit is update, send signal to context manager - EVENT_STATE_WAIT_END_EVENT // prediction unit is ok, wait the end of envent (send by Context State) + EVENT_STATE_WAIT_END_EVENT // prediction unit is ok, wait the end of event (send by Context State) } event_state_t; @@ -45,4 +45,5 @@ UPDATE_PREDICTION_STATE_EVENT , // previous branch is a miss prediction UPDATE_PREDICTION_STATE_END_OK , // branch is updated, update pointer + UPDATE_PREDICTION_STATE_END_KO_WAIT_END , // branch is updated, don't update pointer UPDATE_PREDICTION_STATE_END_KO // branch is updated, don't update pointer } upt_state_t; @@ -147,4 +148,5 @@ case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_EVENT : return "event" ; break; case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_OK : return "end_ok" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_KO_WAIT_END: return "end_ko_wait_end" ; break; case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_KO : return "end_ko" ; break; default : return "" ; break; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 101) @@ -148,7 +148,9 @@ // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_DEPTH_VAL ; //[nb_context] public : SC_OUT(Tdepth_t ) ** out_DEPTH_CURRENT ; //[nb_context] public : SC_OUT(Tdepth_t ) ** out_DEPTH_MIN ; //[nb_context] public : SC_OUT(Tdepth_t ) ** out_DEPTH_MAX ; //[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_DEPTH_FULL ; //[nb_context] // If DEPTH_CURRENT : // equal at DEPTH_MIN -> not speculative @@ -172,4 +174,5 @@ private : uint32_t * reg_UPT_TOP_EVENT ; //[nb_context] private : uint32_t * reg_UPT_UPDATE ; //[nb_context] + private : bool * reg_UPT_EMPTY ; //[nb_context] private : bool * reg_IS_ACCURATE ; //[nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 101) @@ -160,7 +160,9 @@ { ALLOC1_INTERFACE("depth",OUT,SOUTH, "depth", _param->_nb_context); - ALLOC1_SIGNAL_OUT(out_DEPTH_CURRENT,"CURRENT",Tdepth_t,_param->_size_depth); - ALLOC1_SIGNAL_OUT(out_DEPTH_MIN ,"MIN" ,Tdepth_t,_param->_size_depth); - ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"MAX" ,Tdepth_t,_param->_size_depth+1); + ALLOC1_SIGNAL_OUT(out_DEPTH_VAL ,"VAL" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_DEPTH_CURRENT,"CURRENT",Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_DEPTH_FULL ,"FULL" ,Tcontrol_t,1); } @@ -201,4 +203,5 @@ ALLOC1(reg_UPT_TOP_EVENT ,uint32_t ,_param->_nb_context); ALLOC1(reg_UPT_UPDATE ,uint32_t ,_param->_nb_context); + ALLOC1(reg_UPT_EMPTY ,bool ,_param->_nb_context); ALLOC1(reg_EVENT_STATE ,event_state_t,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 101) @@ -117,7 +117,9 @@ // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + DELETE1_SIGNAL(out_DEPTH_VAL ,_param->_nb_context,1); DELETE1_SIGNAL(out_DEPTH_CURRENT ,_param->_nb_context,_param->_size_depth); DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth); - DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth+1); + DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL(out_DEPTH_FULL ,_param->_nb_context,1); // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -154,4 +156,5 @@ DELETE1(reg_UPT_TOP_EVENT ,_param->_nb_context); DELETE1(reg_UPT_UPDATE ,_param->_nb_context); + DELETE1(reg_UPT_EMPTY ,_param->_nb_context); DELETE1(reg_EVENT_STATE ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp (revision 101) @@ -34,10 +34,21 @@ for (uint32_t i=0; i<_param->_nb_context; i++) { + // is a valid instruction ? + // If DEPTH_CURRENT : + // equal at DEPTH_MIN -> not speculative + // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss + // include ]DEPTH_MIN:DEPTH_MAX] -> speculative + + PORT_WRITE(out_DEPTH_VAL [i],(reg_UPDATE_PREDICTION_TABLE [i][reg_UPT_TOP [i]]._state == UPDATE_PREDICTION_STATE_EMPTY)); if (_param->_have_port_depth) { PORT_WRITE(out_DEPTH_CURRENT [i], reg_UPT_TOP [i]); PORT_WRITE(out_DEPTH_MIN [i], reg_UPT_BOTTOM [i]); - } PORT_WRITE(out_DEPTH_MAX [i], reg_UPT_TOP [i]); + } + PORT_WRITE(out_DEPTH_FULL [i], not reg_UPT_EMPTY [i] and (reg_UPT_TOP [i] == reg_UPT_BOTTOM [i])); + +// bool empty = reg_UPT_EMPTY [i]; +// PORT_WRITE(out_DEPTH_MAX [i], ((empty)?reg_UPT_BOTTOM [i]:((reg_UPT_TOP [i]==0)?(_param->_size_upt_queue[i]-1):(reg_UPT_TOP [i]-1)))); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 101) @@ -46,4 +46,5 @@ reg_UPT_TOP_EVENT [i] = 0; reg_UPT_UPDATE [i] = 0; + reg_UPT_EMPTY [i] = true; reg_IS_ACCURATE [i] = true; @@ -87,9 +88,13 @@ // UPDATE_PREDICTION_TABLE { - uint32_t bottom = reg_UPT_BOTTOM [i]; - bool end_ok = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK); - bool end_ko = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO); + uint32_t bottom = reg_UPT_BOTTOM [i]; + bool end_ok = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK); + bool end_ko = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO); +// event_state_t event_state = reg_EVENT_STATE [i]; // Test if state is end +// if ((end_ok or end_ko) and +// ((event_state != EVENT_STATE_UPDATE_CONTEXT) and +// (event_state != EVENT_STATE_WAIT_END_EVENT))) if (end_ok or end_ko) { @@ -102,4 +107,8 @@ // Update pointer reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i]; + + if (reg_UPT_BOTTOM [i] == reg_UPT_TOP [i]) + reg_UPT_EMPTY [i] = true; // free a slot + // if (bottom = reg_UPT_UPDATE [i]) // reg_UPT_UPDATE [i] = reg_UPT_BOTTOM [i]; @@ -108,4 +117,7 @@ reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i]; reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i]; + + if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i]) + reg_UPT_EMPTY [i] = false; } } @@ -290,4 +302,5 @@ // Update pointer reg_UPT_TOP [context] = (upt_ptr_write+1)%_param->_size_upt_queue [context]; + reg_UPT_EMPTY [context] = false; // reg_UPT_UPDATE [context] = reg_UPT_TOP [context]; } @@ -338,4 +351,7 @@ reg_UPT_TOP_EVENT [context] = top; + if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context]) + reg_UPT_EMPTY [i] = true; + #ifdef DEBUG_TEST if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) @@ -483,4 +499,9 @@ if (ko) { + // Ko : wait end of all instruction +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO_WAIT_END (update)",context,depth); + +// reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO_WAIT_END; + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",context,depth); @@ -535,5 +556,5 @@ // Free the branch with no accurate ? - if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) + if ( (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko) reg_IS_ACCURATE [context] = true; } @@ -587,5 +608,6 @@ // Tdepth_t depth = PORT_READ(in_EVENT_DEPTH [i]); - // Test if end of miss + // Test if end of miss -> all previous branch is complete + // -> all next branch is finish if (event_type == EVENT_TYPE_MISS_SPECULATION) { @@ -602,4 +624,19 @@ reg_EVENT_STATE [i] = EVENT_STATE_OK; + reg_IS_ACCURATE [i] = true; + +// Tdepth_t depth = reg_UPT_TOP [i]; + +#ifdef DEBUG_TEST +// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO_WAIT_END) +// throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); +// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO) +// throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); +#endif + +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",i,depth); + +// reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END_KO; + } } @@ -699,4 +736,5 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++) log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d %.1d, %.8d %.8x %.4d - %s", Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h (revision 101) @@ -121,7 +121,9 @@ // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_DEPTH_VAL ; //[nb_context] public : SC_OUT(Tdepth_t ) ** out_DEPTH_CURRENT ; //[nb_context] public : SC_OUT(Tdepth_t ) ** out_DEPTH_MIN ; //[nb_context] public : SC_OUT(Tdepth_t ) ** out_DEPTH_MAX ; //[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_DEPTH_FULL ; //[nb_context] // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp (revision 101) @@ -127,7 +127,9 @@ ALLOC1_INTERFACE("depth",OUT,SOUTH,"Interface with depth",_param->_nb_context); - ALLOC1_SIGNAL_OUT(out_DEPTH_CURRENT ,"current" ,Tdepth_t,_param->_size_depth); - ALLOC1_SIGNAL_OUT(out_DEPTH_MIN ,"min" ,Tdepth_t,_param->_size_depth); - ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"max" ,Tdepth_t,_param->_size_depth+1); + ALLOC1_SIGNAL_OUT(out_DEPTH_VAL ,"val" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_DEPTH_CURRENT ,"current" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_DEPTH_FULL ,"full" ,Tcontrol_t,1); } @@ -729,4 +731,8 @@ #endif + PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_VAL", + dest,"out_DEPTH_"+toString(i)+"_VAL"); + PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_FULL", + dest,"out_DEPTH_"+toString(i)+"_FULL"); if (_param->_have_port_depth) { @@ -735,7 +741,7 @@ PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_MIN", dest,"out_DEPTH_"+toString(i)+"_MIN"); - } PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_MAX", dest,"out_DEPTH_"+toString(i)+"_MAX"); + } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp (revision 101) @@ -76,7 +76,9 @@ DELETE1_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth ); + DELETE1_SIGNAL(out_DEPTH_VAL ,_param->_nb_context,1); DELETE1_SIGNAL(out_DEPTH_CURRENT ,_param->_nb_context,_param->_size_depth); DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth); - DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth+1); + DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL(out_DEPTH_FULL ,_param->_nb_context,1); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp (revision 101) @@ -117,4 +117,5 @@ ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context); @@ -206,6 +207,9 @@ INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_MEM ,_param->_nb_context); if (_param->_have_port_depth) + { INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_MIN ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_MAX ,_param->_nb_context); + } + INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_FULL ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_SR_IEE ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_SR_EPH ,_param->_nb_context); @@ -257,4 +261,5 @@ TEST(Tdepth_t ,out_DEPTH_MIN [i]->read(),0); // no branch speculated TEST(Tdepth_t ,out_DEPTH_MAX [i]->read(),0); // no branch speculated + TEST(Tdepth_t ,out_DEPTH_FULL [i]->read(),0); // no branch speculated } for (uint32_t i=0; i<_param->_sum_inst_decod; ++i) @@ -359,4 +364,5 @@ DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context); DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_DEPTH_FULL ,_param->_nb_context); DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context); DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h (revision 101) @@ -155,4 +155,5 @@ public : SC_OUT(Tdepth_t ) ** out_DEPTH_MIN ;//[nb_context] public : SC_OUT(Tdepth_t ) ** out_DEPTH_MAX ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_DEPTH_FULL ;//[nb_context] // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 101) @@ -180,6 +180,7 @@ ALLOC1_INTERFACE("depth",OUT,EAST,_("Interface depth"),_param->_nb_context); - ALLOC1_SIGNAL_OUT (out_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth ); - ALLOC1_SIGNAL_OUT (out_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth+1); + ALLOC1_SIGNAL_OUT (out_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_OUT (out_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_OUT (out_DEPTH_FULL ,"FULL" ,Tcontrol_t ,1); } @@ -611,4 +612,6 @@ #endif + COMPONENT_MAP(_component,src ,"out_DEPTH_"+toString(i)+ "_VAL", + dest, "in_DEPTH_"+toString(i)+"_PREDICTION_UNIT_VAL"); if (_param->_have_port_depth) { @@ -617,7 +620,9 @@ COMPONENT_MAP(_component,src ,"out_DEPTH_"+toString(i)+ "_MIN" , dest, "in_DEPTH_"+toString(i)+"_PREDICTION_UNIT_MIN" ); - } COMPONENT_MAP(_component,src ,"out_DEPTH_"+toString(i)+ "_MAX" , dest, "in_DEPTH_"+toString(i)+"_PREDICTION_UNIT_MAX" ); + } + COMPONENT_MAP(_component,src ,"out_DEPTH_"+toString(i)+ "_FULL" , + dest, "in_DEPTH_"+toString(i)+"_PREDICTION_UNIT_FULL" ); } } @@ -787,8 +792,13 @@ if (_param->_have_port_depth) + { COMPONENT_MAP(_component,src , "in_DEPTH_"+toString(j)+ "_MIN", dest,"out_DEPTH_"+toString(i)+"_"+toString(j)+"_DECOD_UNIT_MIN"); COMPONENT_MAP(_component,src , "in_DEPTH_"+toString(j)+ "_MAX", dest,"out_DEPTH_"+toString(i)+"_"+toString(j)+"_DECOD_UNIT_MAX"); + } + COMPONENT_MAP(_component,src , "in_DEPTH_"+toString(j)+ "_FULL", + dest,"out_DEPTH_"+toString(i)+"_"+toString(j)+"_DECOD_UNIT_FULL"); + } @@ -828,4 +838,6 @@ #endif + COMPONENT_MAP(_component,src , "in_CONTEXT_"+toString(j)+ "_DEPTH_VAL", + dest,"out_CONTEXT_"+toString(i)+"_"+toString(j)+"_DECOD_UNIT_DEPTH_VAL"); if (_param->_have_port_depth) COMPONENT_MAP(_component,src , "in_CONTEXT_"+toString(j)+ "_DEPTH", @@ -1180,18 +1192,26 @@ if (_param->_have_port_depth) + { PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_MIN", dest,"out_DEPTH_"+toString(i)+"_MIN"); PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_MAX", dest,"out_DEPTH_"+toString(i)+"_MAX"); - } - + } + PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_FULL", + dest,"out_DEPTH_"+toString(i)+"_FULL"); + } + + // in_DEPTH_PREDICTION_UNIT_VAL - component_prediction_unit // in_DEPTH_PREDICTION_UNIT_CURRENT - component_prediction_unit // in_DEPTH_PREDICTION_UNIT_MIN - component_prediction_unit // in_DEPTH_PREDICTION_UNIT_MAX - component_prediction_unit + // in_DEPTH_PREDICTION_UNIT_FULL - component_prediction_unit // out_DEPTH_DECOD_UNIT_MIN - component_decod_unit // out_DEPTH_DECOD_UNIT_MAX - component_decod_unit + // out_DEPTH_DECOD_UNIT_FULL - component_decod_unit // out_DEPTH_CONTEXT_STATE_MIN - component_context_state // ~~~~~[ Interface : "context"" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_CONTEXT_DECOD_UNIT_DEPTH_VAL - component_decod_unit // out_CONTEXT_DECOD_UNIT_DEPTH - component_decod_unit } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp (revision 101) @@ -104,4 +104,5 @@ DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth ); DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth+1); + DELETE1_SIGNAL(out_DEPTH_FULL ,_param->_nb_context,_param->_size_depth+1); DELETE1_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context,1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp (revision 101) @@ -164,4 +164,5 @@ ALLOC2_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); ALLOC2_SC_SIGNAL( in_DEPTH_MAX ," in_DEPTH_MAX ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_DEPTH_FULL ," in_DEPTH_FULL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); ALLOC2_SC_SIGNAL( in_SPR_READ_SR_OVE ," in_SPR_READ_SR_OVE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); @@ -308,5 +309,11 @@ INSTANCE2_SC_SIGNAL(_Commit_unit,out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); INSTANCE2_SC_SIGNAL(_Commit_unit,out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); + + if (_param->_have_port_depth) + { + INSTANCE2_SC_SIGNAL(_Commit_unit, in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1]); INSTANCE2_SC_SIGNAL(_Commit_unit, in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1]); + } + INSTANCE2_SC_SIGNAL(_Commit_unit, in_DEPTH_FULL ,_param->_nb_front_end,_param->_nb_context[it1]); INSTANCE2_SC_SIGNAL(_Commit_unit, in_SPR_READ_SR_OVE ,_param->_nb_front_end,_param->_nb_context[it1]); @@ -321,9 +328,4 @@ INSTANCE2_SC_SIGNAL(_Commit_unit,out_SPR_WRITE_SR_OV ,_param->_nb_front_end,_param->_nb_context[it1]); - for (uint32_t i=0; i<_param->_nb_front_end; i++) - for (uint32_t j=0; j<_param->_nb_context[i]; j++) - if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL(_Commit_unit, in_DEPTH_MIN [i][j]); - msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -703,4 +705,5 @@ DELETE2_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1]); DELETE2_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_DEPTH_FULL ,_param->_nb_front_end,_param->_nb_context[it1]); DELETE2_SC_SIGNAL( in_SPR_READ_SR_OVE ,_param->_nb_front_end,_param->_nb_context[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 101) @@ -194,4 +194,5 @@ public : SC_IN (Tdepth_t ) *** in_DEPTH_MIN ;//[nb_front_end][nb_context] public : SC_IN (Tdepth_t ) *** in_DEPTH_MAX ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_DEPTH_FULL ;//[nb_front_end][nb_context] // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 101) @@ -213,6 +213,7 @@ ALLOC2_INTERFACE("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); - _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); - _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth+1,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL ,"full" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 101) @@ -140,6 +140,7 @@ DELETE2_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_commit); - DELETE2_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth ); - DELETE2_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth+1); + DELETE2_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth); + DELETE2_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth); + DELETE2_SIGNAL( in_DEPTH_FULL ,_param->_nb_front_end, _param->_nb_context[it1],1); DELETE2_SIGNAL( in_SPR_READ_SR_OVE ,_param->_nb_front_end, _param->_nb_context[it1],1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 101) @@ -347,4 +347,6 @@ if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0])) { + log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [0]"); + uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0]; @@ -368,4 +370,7 @@ if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i])) { + log_printf(TRACE,Commit_unit,FUNCTION," * BRANCH_COMPLETE [%d]",i); + log_printf(TRACE,Commit_unit,FUNCTION," * miss_prediction : %d",PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])); + uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i]; @@ -378,5 +383,5 @@ #endif - entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_OK_SPECULATIVE:ROB_END_BRANCH_MISS_SPECULATIVE; + entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE; // entry->state = ROB_END_OK_SPECULATIVE; } @@ -410,12 +415,13 @@ Tdepth_t depth = entry->depth; - Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [front_end_id][context_id]):0; - Tdepth_t depth_max = PORT_READ(in_DEPTH_MAX[front_end_id][context_id]); + Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; + Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; + Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); // is a valid instruction ? // If DEPTH_CURRENT : // equal at DEPTH_MIN -> not speculative - // not include ]DEPTH_MIN:DEPTH_MAX[ -> previous branch miss - // include ]DEPTH_MIN:DEPTH_MAX[ -> speculative + // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss + // include ]DEPTH_MIN:DEPTH_MAX] -> speculative // All case @@ -428,8 +434,15 @@ Tcontrol_t is_valid = ((depth == depth_min) or - ((depth_min < depth_max)? - (depth depth_min) or (depth < depth_max)))); - + depth_full or + ((depth_min <= depth_max)? + ((depth >= depth_min) and (depth <=depth_max)): + ((depth >= depth_min) or (depth <=depth_max)))); + + log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d]",i); + log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d",is_valid); + log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth ); + log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min); + log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); + //------------------------------------------------------ // test if instruction is miss speculative @@ -542,5 +555,5 @@ toString((*it)->state).c_str() , (*it)->ptr ); - log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.5d %.6d, %.1d %.5d %.6d, %.1d %.5d %.6d, %.1d %.1d %.6d %.6d, %.1d %.1d %.6d %.6d ", + log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", (*it)->read_ra , (*it)->num_reg_ra_log , @@ -562,6 +575,6 @@ log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x", + (*it)->exception_use , (*it)->exception , - (*it)->exception_use , (*it)->flags , (*it)->no_sequence , Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp (revision 101) @@ -86,5 +86,5 @@ { entry->data = PORT_READ(in_SPR_RDATA [i]); - entry->write_rd = not PORT_READ(in_SPR_INVALID [i]); +// entry->write_rd = not PORT_READ(in_SPR_INVALID [i]); // in all case write value } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp (revision 101) @@ -36,6 +36,8 @@ Tcontrol_t WRITE_RD = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_WRITE_RD [i]); Tgeneral_address_t NUM_REG_RD_LOG = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG [i]); - Tgeneral_address_t NUM_REG_RD_PHY_OLD = (NUM_REG_RD_LOG!=0)?PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD [i]):0; - Tgeneral_address_t NUM_REG_RD_PHY_NEW = (NUM_REG_RD_LOG!=0)?PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW [i]):0; +// Tgeneral_address_t NUM_REG_RD_PHY_OLD = (NUM_REG_RD_LOG!=0)?PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD [i]):0; +// Tgeneral_address_t NUM_REG_RD_PHY_NEW = (NUM_REG_RD_LOG!=0)?PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW [i]):0; + Tgeneral_address_t NUM_REG_RD_PHY_OLD = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD [i]); + Tgeneral_address_t NUM_REG_RD_PHY_NEW = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW [i]); Tcontrol_t WRITE_RE = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_WRITE_RE [i]); Tspecial_address_t NUM_REG_RE_LOG = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG [i]); @@ -43,5 +45,6 @@ Tspecial_address_t NUM_REG_RE_PHY_NEW = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW [i]); - PORT_WRITE(out_INSERT_FREE_LIST_GPR_VAL [i], WRITE_RD and (NUM_REG_RD_LOG!=0)); +// PORT_WRITE(out_INSERT_FREE_LIST_GPR_VAL [i], WRITE_RD and (NUM_REG_RD_LOG!=0)); + PORT_WRITE(out_INSERT_FREE_LIST_GPR_VAL [i], WRITE_RD ); PORT_WRITE(out_INSERT_FREE_LIST_SPR_VAL [i], WRITE_RE ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp (revision 101) @@ -167,4 +167,5 @@ ALLOC2_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); ALLOC2_SC_SIGNAL( in_DEPTH_MAX ," in_DEPTH_MAX ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_DEPTH_FULL ," in_DEPTH_FULL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); ALLOC2_SC_SIGNAL(out_SPR_SR_IEE ,"out_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); @@ -313,10 +314,10 @@ INSTANCE2_SC_SIGNAL(_OOO_Engine,out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); - for (uint32_t i=0; i<_param->_nb_front_end; i++) - for (uint32_t j=0; j<_param->_nb_context[i]; j++) - if (_param->_have_port_depth) - INSTANCE_SC_SIGNAL(_OOO_Engine, in_DEPTH_MIN [i][j]); + if (_param->_have_port_depth) + { + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1]); INSTANCE2_SC_SIGNAL(_OOO_Engine, in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1]); - + } + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_DEPTH_FULL ,_param->_nb_front_end,_param->_nb_context[it1]); INSTANCE2_SC_SIGNAL(_OOO_Engine,out_SPR_SR_IEE ,_param->_nb_front_end,_param->_nb_context[it1]); INSTANCE2_SC_SIGNAL(_OOO_Engine,out_SPR_SR_EPH ,_param->_nb_front_end,_param->_nb_context[it1]); @@ -482,4 +483,5 @@ DELETE2_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1]); DELETE2_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_DEPTH_FULL ,_param->_nb_front_end,_param->_nb_context[it1]); DELETE2_SC_SIGNAL(out_SPR_SR_IEE ,_param->_nb_front_end,_param->_nb_context[it1]); DELETE2_SC_SIGNAL(out_SPR_SR_EPH ,_param->_nb_front_end,_param->_nb_context[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h (revision 101) @@ -478,12 +478,4 @@ //---------------------------------------------------------- - // [0][19] CID - //---------------------------------------------------------- - class CID : public GENERIC - { - public : CID (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; - }; - - //---------------------------------------------------------- // [0][20] FPCSR //---------------------------------------------------------- @@ -548,4 +540,28 @@ fpee = x >> 0; }; + }; + + //---------------------------------------------------------- + // [0][21] CID + //---------------------------------------------------------- + class CID : public GENERIC + { + public : CID (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + + //---------------------------------------------------------- + // [0][22] TID + //---------------------------------------------------------- + class TID : public GENERIC + { + public : TID (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + + //---------------------------------------------------------- + // [0][23] TSR + //---------------------------------------------------------- + class TSR : public GENERIC + { + public : TSR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp (revision 101) @@ -168,6 +168,8 @@ _spr [i][j][k][SPR_SR ] = new SR (i,j,_param); _spr [i][j][k][SPR_PPC ] = new PPC (i,j,_param); + _spr [i][j][k][SPR_FPCSR ] = new FPCSR (i,j,_param); _spr [i][j][k][SPR_CID ] = new CID (i,j,_param); - _spr [i][j][k][SPR_FPCSR ] = new FPCSR (i,j,_param); + _spr [i][j][k][SPR_TID ] = new TID (i,j,_param); + _spr [i][j][k][SPR_TSR ] = new TSR (i,j,_param); _spr [i][j][k][SPR_EPCR ] = new EPCR (i,j,_param); _spr [i][j][k][SPR_EEAR ] = new EEAR (i,j,_param); @@ -197,5 +199,4 @@ case GROUP_TICK_TIMER : case GROUP_FLOATING_POINT : - case GROUP_MAC : case GROUP_RESERVED_1 : Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h (revision 101) @@ -197,4 +197,5 @@ public : SC_IN (Tdepth_t ) *** in_DEPTH_MIN ;//[nb_front_end][nb_context] public : SC_IN (Tdepth_t ) *** in_DEPTH_MAX ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_DEPTH_FULL ;//[nb_front_end][nb_context] // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 101) @@ -225,5 +225,6 @@ _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); - _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth+1 ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_DEPTH_FULL ,"FULL" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); } @@ -990,8 +991,12 @@ if (_param->_have_port_depth) + { PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN", dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN"); PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX", dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX"); + } + PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL", + dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_FULL"); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp (revision 101) @@ -142,5 +142,6 @@ DELETE2_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_nb_inst_commit ); DELETE2_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth ); - DELETE2_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth+1 ); + DELETE2_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth ); + DELETE2_SIGNAL( in_DEPTH_FULL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); DELETE2_SIGNAL(out_SPR_SR_IEE ,_param->_nb_front_end,_param->_nb_context[it1],1 ); DELETE2_SIGNAL(out_SPR_SR_EPH ,_param->_nb_front_end,_param->_nb_context[it1],1 ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp (revision 101) @@ -383,6 +383,7 @@ // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - // out_DEPTH_MIN - ooo_engine. in_DEPTH_MIN - // out_DEPTH_MAX - ooo_engine. in_DEPTH_MAX + // out_DEPTH_MIN - ooo_engine. in_DEPTH_MIN + // out_DEPTH_MAX - ooo_engine. in_DEPTH_MAX + // out_DEPTH_FULL - ooo_engine. in_DEPTH_FULL // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -646,8 +647,12 @@ if (_param->_have_port_depth) + { COMPONENT_MAP(_component,src , "in_DEPTH_"+toString(j)+"_"+toString(k)+"_MIN", dest,"out_DEPTH_" +toString(k)+"_MIN"); COMPONENT_MAP(_component,src , "in_DEPTH_"+toString(j)+"_"+toString(k)+"_MAX", dest,"out_DEPTH_" +toString(k)+"_MAX"); + } + COMPONENT_MAP(_component,src , "in_DEPTH_"+toString(j)+"_"+toString(k)+"_FULL", + dest,"out_DEPTH_" +toString(k)+"_FULL"); } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp (revision 101) @@ -495,5 +495,5 @@ _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_BNF ] |= (instruction_size_data(INSTRUCTION_L_BNF ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_BNF )._type][instruction_information(INSTRUCTION_L_BNF )._operation]._latence > 0); _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CMOV ] |= (instruction_size_data(INSTRUCTION_L_CMOV ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CMOV )._type][instruction_information(INSTRUCTION_L_CMOV )._operation]._latence > 0); - _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CSYNC ] |= (instruction_size_data(INSTRUCTION_L_CSYNC ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CSYNC )._type][instruction_information(INSTRUCTION_L_CSYNC )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CSYNC ] |= (instruction_size_data(INSTRUCTION_L_CSYNC ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CSYNC )._type][instruction_information(INSTRUCTION_L_CSYNC )._operation]._latence > 0); _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST1 ] |= (instruction_size_data(INSTRUCTION_L_CUST1 ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CUST1 )._type][instruction_information(INSTRUCTION_L_CUST1 )._operation]._latence > 0); _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST2 ] |= (instruction_size_data(INSTRUCTION_L_CUST2 ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CUST2 )._type][instruction_information(INSTRUCTION_L_CUST2 )._operation]._latence > 0); @@ -531,5 +531,5 @@ _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MOVHI ] |= (instruction_size_data(INSTRUCTION_L_MOVHI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MOVHI )._type][instruction_information(INSTRUCTION_L_MOVHI )._operation]._latence > 0); _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MSB ] |= (instruction_size_data(INSTRUCTION_L_MSB ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MSB )._type][instruction_information(INSTRUCTION_L_MSB )._operation]._latence > 0); - _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MSYNC ] |= (instruction_size_data(INSTRUCTION_L_MSYNC ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MSYNC )._type][instruction_information(INSTRUCTION_L_MSYNC )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MSYNC ] |= (instruction_size_data(INSTRUCTION_L_MSYNC ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MSYNC )._type][instruction_information(INSTRUCTION_L_MSYNC )._operation]._latence > 0); _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MTSPR ] |= (instruction_size_data(INSTRUCTION_L_MTSPR ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MTSPR )._type][instruction_information(INSTRUCTION_L_MTSPR )._operation]._latence > 0); _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MUL ] |= (instruction_size_data(INSTRUCTION_L_MUL ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MUL )._type][instruction_information(INSTRUCTION_L_MUL )._operation]._latence > 0); @@ -539,5 +539,5 @@ _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_OR ] |= (instruction_size_data(INSTRUCTION_L_OR ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_OR )._type][instruction_information(INSTRUCTION_L_OR )._operation]._latence > 0); _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_ORI ] |= (instruction_size_data(INSTRUCTION_L_ORI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_ORI )._type][instruction_information(INSTRUCTION_L_ORI )._operation]._latence > 0); - _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_PSYNC ] |= (instruction_size_data(INSTRUCTION_L_PSYNC ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_PSYNC )._type][instruction_information(INSTRUCTION_L_PSYNC )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_PSYNC ] |= (instruction_size_data(INSTRUCTION_L_PSYNC ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_PSYNC )._type][instruction_information(INSTRUCTION_L_PSYNC )._operation]._latence > 0); _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_RFE ] |= (instruction_size_data(INSTRUCTION_L_RFE ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_RFE )._type][instruction_information(INSTRUCTION_L_RFE )._operation]._latence > 0); _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_ROR ] |= (instruction_size_data(INSTRUCTION_L_ROR ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_ROR )._type][instruction_information(INSTRUCTION_L_ROR )._operation]._latence > 0); @@ -728,6 +728,49 @@ _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SH ] |= (instruction_size_data(INSTRUCTION_L_SH ) <= size_general_data); _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SW ] |= (instruction_size_data(INSTRUCTION_L_SW ) <= size_general_data); + +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CSYNC ] = true; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MSYNC ] = true; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_PSYNC ] = true; } + // Reedit timing + { + multi_execute_loop::execute_loop::execute_timing_t timing_tmp [_nb_functionnal_unit][_nb_type][_nb_operation]; + + for (uint32_t i=0; i<_nb_functionnal_unit; ++i) + for (uint32_t j=0; j<_nb_type; ++j) + for (uint32_t k=0; k<_nb_operation; ++k) + { + timing_tmp [i][j][k]._latence = _timing [i][j][k]._latence; + timing_tmp [i][j][k]._delay = _timing [i][j][k]._delay ; + + // Reset + _timing [i][j][k]._latence = _timing [i][j][k]._delay = 0; + } + + for (uint32_t i=0; i<_nb_thread; ++i) + { + uint32_t num_front_end = _link_context_with_thread [i].first; + uint32_t num_context = _link_context_with_thread [i].second; + + for (uint32_t j=0; j<_nb_functionnal_unit; ++j) + { + // Test if link + if (not _link_thread_and_functionnal_unit[i][j]) + continue; + + for (uint32_t k=0; k " << argv[0] << " name_instance list_params" << endl << "list_params is :" << endl - << " - size_queue (uint32_t)" << endl - << " - size_data (uint32_t)" << endl - << " - nb_port_slot (uint32_t)" << endl + << " - size_queue (uint32_t)" << endl + << " - size_data (uint32_t)" << endl + << " - nb_port_slot (uint32_t)" << endl + << " - have_port_write (bool )" << endl + << " - have_port_read (bool )" << endl << "" << endl; @@ -37,9 +39,10 @@ uint32_t x = 1; - const string name = argv[x++]; - const uint32_t size_queue = atoi(argv[x++]); - const uint32_t size_data = atoi(argv[x++]); - const uint32_t nb_port_slot = atoi(argv[x++]); - + const string name = argv[x++]; + const uint32_t size_queue = fromString(argv[x++]); + const uint32_t size_data = fromString(argv[x++]); + const uint32_t nb_port_slot = fromString(argv[x++]); + const bool have_port_write = fromString(argv[x++]); + const bool have_port_read = fromString(argv[x++]); try { @@ -47,5 +50,7 @@ (size_queue, size_data , - nb_port_slot + nb_port_slot, + have_port_write, + have_port_read ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/src/test.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/src/test.cpp (revision 101) @@ -58,4 +58,6 @@ ALLOC1_SC_SIGNAL(out_SLOT_VAL ,"out_SLOT_VAL" ,Tcontrol_t,_param->_nb_port_slot); ALLOC1_SC_SIGNAL(out_SLOT_DATA ,"out_SLOT_DATA" ,Tdata_t ,_param->_nb_port_slot); + ALLOC0_SC_SIGNAL(out_PTR_WRITE ,"out_PTR_WRITE" ,Tptr_t ); + ALLOC0_SC_SIGNAL(out_PTR_READ ,"out_PTR_READ" ,Tptr_t ); /******************************************************** @@ -76,4 +78,8 @@ INSTANCE1_SC_SIGNAL(_Queue,out_SLOT_VAL ,_param->_nb_port_slot); INSTANCE1_SC_SIGNAL(_Queue,out_SLOT_DATA ,_param->_nb_port_slot); + if (_param->_have_port_ptr_write) + INSTANCE0_SC_SIGNAL(_Queue,out_PTR_WRITE ); + if (_param->_have_port_ptr_read ) + INSTANCE0_SC_SIGNAL(_Queue,out_PTR_READ ); cout << "<" << name << "> Start Simulation ............" << endl; @@ -168,5 +174,6 @@ DELETE1_SC_SIGNAL(out_SLOT_VAL ,_param->_nb_port_slot); DELETE1_SC_SIGNAL(out_SLOT_DATA ,_param->_nb_port_slot); - + DELETE0_SC_SIGNAL(out_PTR_WRITE ); + DELETE0_SC_SIGNAL(out_PTR_READ ); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Parameters.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Parameters.h (revision 101) @@ -22,12 +22,19 @@ { //-----[ fields ]------------------------------------------------------------ - public : const uint32_t _size_queue ; - public : const uint32_t _size_data ; - public : const uint32_t _nb_port_slot; + public : const uint32_t _size_queue ; + public : const uint32_t _size_data ; + public : const uint32_t _nb_port_slot ; + public : const bool _have_port_ptr_write; + public : const bool _have_port_ptr_read ; + + public : const uint32_t _size_ptr ; + public : const bool _have_port_ptr ; //-----[ methods ]----------------------------------------------------------- - public : Parameters (uint32_t size_queue, - uint32_t size_data , - uint32_t nb_port_slot); + public : Parameters (uint32_t size_queue , + uint32_t size_data , + uint32_t nb_port_slot , + bool have_port_ptr_write, + bool have_port_ptr_read ); // public : Parameters (Parameters & param) ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Queue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Queue.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Queue.h (revision 101) @@ -78,4 +78,8 @@ public : SC_OUT(Tdata_t ) ** out_SLOT_DATA; + // ~~~~~[ Interface "ptr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tptr_t ) * out_PTR_WRITE; + public : SC_OUT(Tptr_t ) * out_PTR_READ ; + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ protected : morpheo::behavioural::generic::queue_control::Queue_Control * _queue_control; @@ -87,5 +91,4 @@ protected : Tcontrol_t internal_INSERT_ACK; protected : Tcontrol_t internal_RETIRE_VAL; - #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters.cpp (revision 101) @@ -7,5 +7,5 @@ #include "Behavioural/Generic/Queue/include/Parameters.h" - +#include "Common/include/Log2.h" namespace morpheo { namespace behavioural { @@ -16,10 +16,16 @@ #undef FUNCTION #define FUNCTION "Queue::Parameters" - Parameters::Parameters (uint32_t size_queue, - uint32_t size_data , - uint32_t nb_port_slot): - _size_queue (size_queue), - _size_data (size_data ), - _nb_port_slot (nb_port_slot) + Parameters::Parameters (uint32_t size_queue , + uint32_t size_data , + uint32_t nb_port_slot , + bool have_port_ptr_write, + bool have_port_ptr_read ): + _size_queue (size_queue), + _size_data (size_data ), + _nb_port_slot (nb_port_slot), + _have_port_ptr_write (have_port_ptr_write and (log2(size_queue)>0)), + _have_port_ptr_read (have_port_ptr_read and (log2(size_queue)>0)), + _size_ptr (log2(size_queue)), + _have_port_ptr (have_port_ptr_write or have_port_ptr_read) { log_printf(FUNC,Queue,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp (revision 101) @@ -72,4 +72,15 @@ ALLOC1_SIGNAL_OUT(out_SLOT_DATA ,"data",Tdata_t,_param->_size_data); } + + // ~~~~~[ Interface "ptr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (_param->_have_port_ptr) + { + ALLOC0_INTERFACE("ptr", OUT, EAST, _("Internal pointer.")); + + if (_param->_have_port_ptr_write) + ALLOC0_SIGNAL_OUT(out_PTR_WRITE ,"write",Tptr_t,_param->_size_ptr); + if (_param->_have_port_ptr_read ) + ALLOC0_SIGNAL_OUT(out_PTR_READ ,"read" ,Tptr_t,_param->_size_ptr); + } if (usage_is_set(_usage,USE_SYSTEMC)) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_deallocation.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_deallocation.cpp (revision 101) @@ -36,4 +36,9 @@ DELETE1_SIGNAL(out_SLOT_VAL ,_param->_nb_port_slot,1); DELETE1_SIGNAL(out_SLOT_DATA ,_param->_nb_port_slot,_param->_size_data); + + if (_param->_have_port_ptr_write) + DELETE0_SIGNAL(out_PTR_WRITE ,_param->_size_ptr); + if (_param->_have_port_ptr_read ) + DELETE0_SIGNAL(out_PTR_READ ,_param->_size_ptr); // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_genMoore.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_genMoore.cpp (revision 101) @@ -20,5 +20,7 @@ log_printf(FUNC,Queue,FUNCTION,"Begin"); + //--------------------------------------------- // Output + //--------------------------------------------- internal_INSERT_ACK = not _queue_control->full(); internal_RETIRE_VAL = not _queue_control->empty(); @@ -28,5 +30,7 @@ PORT_WRITE(out_RETIRE_DATA,_queue_data[(*_queue_control)[0]]); + //--------------------------------------------- // Slot + //--------------------------------------------- // Note : Slot 0 is the same slot as retire interface. uint32_t nb_elt = _queue_control->nb_elt(); @@ -37,4 +41,12 @@ PORT_WRITE(out_SLOT_DATA [i],_queue_data[(*_queue_control)[i]]); } + + //--------------------------------------------- + // Pointer + //--------------------------------------------- + if (_param->_have_port_ptr_write) + PORT_WRITE(out_PTR_WRITE, _queue_control->ptr_push()); + if (_param->_have_port_ptr_read ) + PORT_WRITE(out_PTR_READ , _queue_control->ptr_pop ()); log_printf(FUNC,Queue,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_vhdl_body.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_vhdl_body.cpp (revision 101) @@ -62,4 +62,17 @@ else vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <= reg_DATA(conv_integer(0));"); + } + + if (_param->_have_port_ptr) + { + vhdl->set_body (0,""); + vhdl->set_comment(0,"---------------------------------------------------------------------------"); + vhdl->set_comment(0," Slot"); + vhdl->set_comment(0,"---------------------------------------------------------------------------"); + vhdl->set_body (0,""); + if (_param->_have_port_ptr_write) + vhdl->set_body (0,"out_PTR_WRITE <= signal_PTR_WRITE;"); + if (_param->_have_port_ptr_read) + vhdl->set_body (0,"out_PTR_READ <= signal_PTR_READ;"); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue_Control/include/Queue_Control.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue_Control/include/Queue_Control.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue_Control/include/Queue_Control.h (revision 101) @@ -35,9 +35,13 @@ public : void clear (void); + public : uint32_t ptr_pop (uint32_t index=0); + public : uint32_t ptr_push (void); + + public : uint32_t push (void); public : uint32_t push_ovf (void); - public : void pop (uint32_t); + public : void pop (uint32_t index); public : void pop (void); - public : void pop_ovf (uint32_t); + public : void pop_ovf (uint32_t index); public : void pop_ovf (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Parameters.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Parameters.h (revision 101) @@ -21,17 +21,20 @@ class Parameters : public morpheo::behavioural::Parameters { - public : const uint32_t _nb_port_read ; - public : const uint32_t _nb_port_write; - public : const uint32_t _nb_port_read_write; - public : const uint32_t _nb_word ; - public : const uint32_t _size_word ; - public : const uint32_t _size_address ; - public : const bool _have_port_address; + public : const uint32_t _nb_port_read ; + public : const uint32_t _nb_port_write; + public : const uint32_t _nb_port_read_write; + public : const uint32_t _nb_word ; + public : const uint32_t _size_word ; + public : const uint32_t _size_address ; + public : const bool _have_port_address; + public : const bool _have_init_value; + public : const std::string _init_value; - public : Parameters (uint32_t nb_port_read , - uint32_t nb_port_write, - uint32_t nb_port_read_write, - uint32_t nb_word , - uint32_t size_word ); + public : Parameters (uint32_t nb_port_read , + uint32_t nb_port_write, + uint32_t nb_port_read_write, + uint32_t nb_word , + uint32_t size_word , + std::string init_value=""); // public : Parameters (Parameters & param) ; public : ~Parameters () ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/Parameters.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/Parameters.cpp (revision 101) @@ -14,9 +14,10 @@ namespace registerfile_monolithic { - Parameters::Parameters (uint32_t nb_port_read , - uint32_t nb_port_write, - uint32_t nb_port_read_write , - uint32_t nb_word , - uint32_t size_word + Parameters::Parameters (uint32_t nb_port_read , + uint32_t nb_port_write, + uint32_t nb_port_read_write , + uint32_t nb_word , + uint32_t size_word , + std::string init_value ) : _nb_port_read (nb_port_read ), @@ -26,6 +27,7 @@ _size_word (size_word ), _size_address (static_cast(log2(_nb_word))), - _have_port_address (_size_address != 0) - + _have_port_address (_size_address != 0), + _have_init_value (init_value != ""), + _init_value (init_value) { test(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/Parameters_msg_error.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/Parameters_msg_error.cpp (revision 101) @@ -33,4 +33,6 @@ test.error("you need a write port"); + // Need test init_value + return test; }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp (revision 101) @@ -18,60 +18,59 @@ log_printf(FUNC,RegisterFile,"transition","Begin"); - for (uint32_t i=0; i<_param->_nb_port_write; i++) + if (_param->_have_init_value and (PORT_READ(in_NRESET) == 0)) { - // Have a write? - if ( PORT_READ(in_WRITE_VAL[i]) == true) - { + for (uint32_t i=0; i<_param->_nb_word; ++i) + reg_DATA[i] = fromString(_param->_init_value); + } + else + { + for (uint32_t i=0; i<_param->_nb_port_write; i++) + { + // Have a write? + if ( PORT_READ(in_WRITE_VAL[i]) == true) + { #ifdef STATISTICS - if (usage_is_set(_usage,USE_STATISTICS)) - (*_stat_nb_write) ++; -#endif - - Taddress_t address; - if (_param->_have_port_address) - address = PORT_READ(in_WRITE_ADDRESS[i]); - else - address = 0; - - Tdata_t data = PORT_READ(in_WRITE_DATA [i]); - - log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast(address),static_cast(data)); - - // Write in registerFile - reg_DATA[address] = data; - } - } - for (uint32_t i=0; i<_param->_nb_port_read_write; i++) - { - // Have a read_write? - if (PORT_READ(in_READ_WRITE_VAL[i]) == true) - { - if (PORT_READ(in_READ_WRITE_RW [i]) == RW_WRITE) - { -#ifdef STATISTICS - if (usage_is_set(_usage,USE_STATISTICS)) + if (usage_is_set(_usage,USE_STATISTICS)) (*_stat_nb_write) ++; #endif - - Taddress_t address; - if (_param->_have_port_address) - address = PORT_READ(in_READ_WRITE_ADDRESS[i]); - else - address = 0; - Tdata_t data = PORT_READ(in_READ_WRITE_WDATA [i]); - - log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast(address),static_cast(data)); - - // Write in registerFile - reg_DATA[address] = data; - } + + Taddress_t address = (_param->_have_port_address)?PORT_READ(in_WRITE_ADDRESS[i]):0; + Tdata_t data = PORT_READ(in_WRITE_DATA [i]); + + log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast(address),static_cast(data)); + + // Write in registerFile + reg_DATA[address] = data; + } + } + for (uint32_t i=0; i<_param->_nb_port_read_write; i++) + { + // Have a read_write? + if (PORT_READ(in_READ_WRITE_VAL[i]) == true) + { + if (PORT_READ(in_READ_WRITE_RW [i]) == RW_WRITE) + { #ifdef STATISTICS - else - { - if (usage_is_set(_usage,USE_STATISTICS)) - (*_stat_nb_read) ++; - } + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_write) ++; #endif - } + + Taddress_t address = (_param->_have_port_address)?PORT_READ(in_READ_WRITE_ADDRESS[i]):0; + Tdata_t data = PORT_READ(in_READ_WRITE_WDATA [i]); + + log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast(address),static_cast(data)); + + // Write in registerFile + reg_DATA[address] = data; + } +#ifdef STATISTICS + else + { + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_read) ++; + } +#endif + } + } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp (revision 101) @@ -65,4 +65,16 @@ vhdl->set_body (0,"begin -- process RegisterFile_write"); vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); + + if (_param->_have_init_value) + { + vhdl->set_body (2,"if in_NRESET = '0' then"); + + std::string init_value = ((_param->_size_word>1)?"\"":"'")+_param->_init_value+((_param->_size_word>1)?"\"":"'"); + + for (uint32_t i=0; i<_param->_nb_word; ++i) + vhdl->set_body (3,"reg_DATA("+toString(i)+") <= "+init_value+";"); + + vhdl->set_body (2,"else"); + } for (uint32_t i = 0; i < _param->_nb_port_write; i++) @@ -92,4 +104,8 @@ vhdl->set_body (1,"end if;"); + + if (_param->_have_init_value) + vhdl->set_body (1,"end if;"); + vhdl->set_body (0,"end process RegisterFile_write;"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h (revision 101) @@ -14,5 +14,7 @@ I Use reserved SPR : - [0][19] - SPR_CID + [0][21] - SPR_CID : Context Id + [0][22] - SPR_TID : Thread Id + [0][23] - SPR_TSR : Thread Status Register (Priority) */ @@ -216,7 +218,7 @@ # define OPERATION_SPECIAL_L_MACRC 0x12 // 001_0010 l.macrc # define OPERATION_SPECIAL_L_MSB 0x14 // 001_0100 l.msb -# define OPERATION_SPECIAL_L_MSYNC 0x21 // 010_0001 l.msync -# define OPERATION_SPECIAL_L_PSYNC 0x22 // 010_0010 l.psync -# define OPERATION_SPECIAL_L_CSYNC 0x24 // 010_0100 l.csync +//#define OPERATION_SPECIAL_L_MSYNC 0x21 // 010_0001 l.msync +//#define OPERATION_SPECIAL_L_PSYNC 0x22 // 010_0010 l.psync +//#define OPERATION_SPECIAL_L_CSYNC 0x24 // 010_0100 l.csync # define OPERATION_SPECIAL_L_SYS 0x41 // 100_0001 l.sys # define OPERATION_SPECIAL_L_TRAP 0x42 // 100_0010 l.trap @@ -542,6 +544,8 @@ # define SPR_SR 17 // Supervision register # define SPR_PPC 18 // PC mapped to SPR space (previous PC) -# define SPR_CID 19 // Context Id # define SPR_FPCSR 20 // FP Control Status register +# define SPR_CID 21 // Context Id +# define SPR_TID 22 // Thread Id +# define SPR_TSR 23 // Thread Priority # define SPR_EPCR 32 // Exception PC register # define SPR_EEAR 48 // Exception EA register Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 101) @@ -10,8 +10,8 @@ #define MORPHEO_MAJOR_VERSION 0 #define MORPHEO_MINOR_VERSION 2 -#define MORPHEO_REVISION "100" +#define MORPHEO_REVISION "101" #define MORPHEO_CODENAME "Castor" -#define MORPHEO_DATE_DAY "08" +#define MORPHEO_DATE_DAY "15" #define MORPHEO_DATE_MONTH "01" #define MORPHEO_DATE_YEAR "2009" Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Types.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Types.cpp (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Types.cpp (revision 101) @@ -27,5 +27,6 @@ case INSTRUCTION_L_BNF : return instruction_t (TYPE_BRANCH ,OPERATION_BRANCH_L_TEST_NF ,ORBIS32,1); case INSTRUCTION_L_CMOV : return instruction_t (TYPE_MOVE ,OPERATION_MOVE_L_CMOV ,ORBIS32,2); - case INSTRUCTION_L_CSYNC : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_CSYNC ,ORBIS32,2); +// case INSTRUCTION_L_CSYNC : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_CSYNC ,ORBIS32,2); + case INSTRUCTION_L_CSYNC : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_SYNCHRONIZATION,ORBIS32,2); case INSTRUCTION_L_CUST1 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_L_1 ,ORBIS32,2); case INSTRUCTION_L_CUST2 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_L_2 ,ORBIS32,2); @@ -63,5 +64,6 @@ case INSTRUCTION_L_MOVHI : return instruction_t (TYPE_MOVE ,OPERATION_MOVE_L_MOVHI ,ORBIS32,1); case INSTRUCTION_L_MSB : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_MSB ,ORBIS32,2); - case INSTRUCTION_L_MSYNC : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_MSYNC ,ORBIS32,2); +// case INSTRUCTION_L_MSYNC : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_MSYNC ,ORBIS32,2); + case INSTRUCTION_L_MSYNC : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_SYNCHRONIZATION,ORBIS32,2); case INSTRUCTION_L_MTSPR : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_MTSPR ,ORBIS32,1); case INSTRUCTION_L_MUL : return instruction_t (TYPE_MUL ,OPERATION_MUL_L_MUL ,ORBIS32,1); @@ -71,5 +73,6 @@ case INSTRUCTION_L_OR : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_OR ,ORBIS32,1); case INSTRUCTION_L_ORI : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_OR ,ORBIS32,1); - case INSTRUCTION_L_PSYNC : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_PSYNC ,ORBIS32,2); +// case INSTRUCTION_L_PSYNC : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_PSYNC ,ORBIS32,2); + case INSTRUCTION_L_PSYNC : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_SYNCHRONIZATION,ORBIS32,2); case INSTRUCTION_L_RFE : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_RFE ,ORBIS32,1); case INSTRUCTION_L_ROR : return instruction_t (TYPE_SHIFT ,OPERATION_SHIFT_L_ROR ,ORBIS32,2); Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_1.cfg (revision 100) +++ (revision ) @@ -1,152 +1,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_2.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_2.cfg (revision 100) +++ (revision ) @@ -1,152 +1,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_1.cfg (revision 101) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_1.cfg (revision 101) @@ -0,0 +1,152 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_2.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_2.cfg (revision 101) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_w1_2.cfg (revision 101) @@ -0,0 +1,152 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen (revision 101) @@ -73,6 +73,6 @@ - - + + Index: trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 100) +++ trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 101) @@ -15,5 +15,5 @@ - + @@ -23,7 +23,7 @@ - + - +