Index: trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_access_lock.cpp
===================================================================
--- trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_access_lock.cpp	(revision 102)
+++ trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_access_lock.cpp	(revision 102)
@@ -0,0 +1,16 @@
+#include "../include/Cache_OneLevel.h"
+
+namespace environment {
+namespace cache {
+namespace cache_onelevel {
+
+  type_rsp_cache_t Cache_OneLevel::access_lock (uint32_t num_port, uint32_t address, uint32_t trdid)
+  {
+    std::cerr << "<" << name << ".{Cache_OneLevel}.access_lock> Not implemented" << std::endl;
+    exit (0);
+    return MISS;
+  }
+
+};
+};
+};
Index: trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_access_prefetch.cpp
===================================================================
--- trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_access_prefetch.cpp	(revision 102)
+++ trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_access_prefetch.cpp	(revision 102)
@@ -0,0 +1,14 @@
+#include "../include/Cache_OneLevel.h"
+
+namespace environment {
+namespace cache {
+namespace cache_onelevel {
+
+  type_rsp_cache_t Cache_OneLevel::access_prefetch (uint32_t num_port, uint32_t address, uint32_t trdid)
+  {
+    return access_cached (num_port,address,trdid,READ);
+  }
+
+};
+};
+};
Index: trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_access_synchronization.cpp
===================================================================
--- trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_access_synchronization.cpp	(revision 102)
+++ trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_access_synchronization.cpp	(revision 102)
@@ -0,0 +1,19 @@
+#include "../include/Cache_OneLevel.h"
+
+namespace environment {
+namespace cache {
+namespace cache_onelevel {
+
+  type_rsp_cache_t Cache_OneLevel::access_synchronization (uint32_t num_port, uint32_t address, uint32_t trdid)
+  {
+    access_port[num_port].valid   = false;
+    access_port[num_port].trdid   = trdid;
+    access_port[num_port].hit     = MISS;
+    access_port[num_port].latence = param->miss_penality;
+
+    return MISS;
+  }
+
+};
+};
+};