Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp (revision 104) @@ -441,5 +441,5 @@ transaction_in.push_back(execute_transaction(_param,0,0,0,233,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbeef,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - == - transaction_in.push_back(execute_transaction(_param,0,0,0,234,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbabe,0xdeadbeef,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - > - - transaction_in.push_back(execute_transaction(_param,0,0,0,235,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbabe,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - < - + transaction_in.push_back(execute_transaction(_param,0,0,0,235,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbabe,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - < - transaction_in.push_back(execute_transaction(_param,0,0,0,236,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbeef,0x21524111,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - == + (in unsigned) transaction_in.push_back(execute_transaction(_param,0,0,0,237,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbeef,0x11111111,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - > + (in unsigned) @@ -452,6 +452,6 @@ transaction_in.push_back(execute_transaction(_param,0,0,0,252,OPERATION_TEST_L_SFGTS ,TYPE_TEST,0,0 ,0x21071981,0x25071959,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // + < + transaction_in.push_back(execute_transaction(_param,0,0,0,253,OPERATION_TEST_L_SFGTS ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbeef,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - == - - transaction_in.push_back(execute_transaction(_param,0,0,0,254,OPERATION_TEST_L_SFGTS ,TYPE_TEST,0,0 ,0xdeadbabe,0xdeadbeef,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - > - - transaction_in.push_back(execute_transaction(_param,0,0,0,255,OPERATION_TEST_L_SFGTS ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbabe,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - < - + transaction_in.push_back(execute_transaction(_param,0,0,0,254,OPERATION_TEST_L_SFGTS ,TYPE_TEST,0,0 ,0xdeadbabe,0xdeadbeef,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - > - + transaction_in.push_back(execute_transaction(_param,0,0,0,255,OPERATION_TEST_L_SFGTS ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbabe,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - < - transaction_in.push_back(execute_transaction(_param,0,0,0,256,OPERATION_TEST_L_SFGTS ,TYPE_TEST,0,0 ,0xdeadbeef,0x21524111,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - == + (in unsigned) transaction_in.push_back(execute_transaction(_param,0,0,0,257,OPERATION_TEST_L_SFGTS ,TYPE_TEST,0,0 ,0xdeadbeef,0x11111111,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - > + (in unsigned) @@ -464,6 +464,6 @@ transaction_in.push_back(execute_transaction(_param,0,0,0,272,OPERATION_TEST_L_SFLES ,TYPE_TEST,0,0 ,0x21071981,0x25071959,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // + < + transaction_in.push_back(execute_transaction(_param,0,0,0,273,OPERATION_TEST_L_SFLES ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbeef,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - == - - transaction_in.push_back(execute_transaction(_param,0,0,0,274,OPERATION_TEST_L_SFLES ,TYPE_TEST,0,0 ,0xdeadbabe,0xdeadbeef,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - > - - transaction_in.push_back(execute_transaction(_param,0,0,0,275,OPERATION_TEST_L_SFLES ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbabe,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - < - + transaction_in.push_back(execute_transaction(_param,0,0,0,274,OPERATION_TEST_L_SFLES ,TYPE_TEST,0,0 ,0xdeadbabe,0xdeadbeef,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - > - + transaction_in.push_back(execute_transaction(_param,0,0,0,275,OPERATION_TEST_L_SFLES ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbabe,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - < - transaction_in.push_back(execute_transaction(_param,0,0,0,276,OPERATION_TEST_L_SFLES ,TYPE_TEST,0,0 ,0xdeadbeef,0x21524111,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - == + (in unsigned) transaction_in.push_back(execute_transaction(_param,0,0,0,277,OPERATION_TEST_L_SFLES ,TYPE_TEST,0,0 ,0xdeadbeef,0x11111111,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - > + (in unsigned) @@ -476,6 +476,6 @@ transaction_in.push_back(execute_transaction(_param,0,0,0,292,OPERATION_TEST_L_SFLTS ,TYPE_TEST,0,0 ,0x21071981,0x25071959,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // + < + transaction_in.push_back(execute_transaction(_param,0,0,0,293,OPERATION_TEST_L_SFLTS ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbeef,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - == - - transaction_in.push_back(execute_transaction(_param,0,0,0,294,OPERATION_TEST_L_SFLTS ,TYPE_TEST,0,0 ,0xdeadbabe,0xdeadbeef,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - > - - transaction_in.push_back(execute_transaction(_param,0,0,0,295,OPERATION_TEST_L_SFLTS ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbabe,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - < - + transaction_in.push_back(execute_transaction(_param,0,0,0,294,OPERATION_TEST_L_SFLTS ,TYPE_TEST,0,0 ,0xdeadbabe,0xdeadbeef,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - > - + transaction_in.push_back(execute_transaction(_param,0,0,0,295,OPERATION_TEST_L_SFLTS ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbabe,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - < - transaction_in.push_back(execute_transaction(_param,0,0,0,296,OPERATION_TEST_L_SFLTS ,TYPE_TEST,0,0 ,0xdeadbeef,0x21524111,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - == + (in unsigned) transaction_in.push_back(execute_transaction(_param,0,0,0,297,OPERATION_TEST_L_SFLTS ,TYPE_TEST,0,0 ,0xdeadbeef,0x11111111,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - > + (in unsigned) @@ -572,12 +572,12 @@ transaction_in.push_back(execute_transaction(_param,0,0,0,701,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x00002107,0x00001981,0 ,1,63,0x034a5387,1,15,0 ,EXCEPTION_NONE ,0)); transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x00048698,0x0000dead,0 ,1,63,0xefc6c4b8,1,15,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); - transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x40000000,0x00000002,0 ,1,63,0x80000000,1,15, FLAG_OV,EXCEPTION_ALU_RANGE,0)); - transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x40000000,0x00000004,0 ,1,63,0x00000000,1,15,FLAG_CY ,EXCEPTION_NONE ,0)); - - transaction_in.push_back(execute_transaction(_param,0,0,0,700,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00000001,0x00000001,0 ,1,63,0x00000001,1,15,0 ,EXCEPTION_NONE ,0)); - transaction_in.push_back(execute_transaction(_param,0,0,0,701,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00002107,0x00001981,0 ,1,63,0x034a5387,1,15,0 ,EXCEPTION_NONE ,0)); - transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00048698,0x0000dead,0 ,1,63,0xefc6c4b8,1,15,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); - transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x40000000,0x00000002,0 ,1,63,0x80000000,1,15, FLAG_OV,EXCEPTION_ALU_RANGE,0)); - transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x40000000,0x00000004,0 ,1,63,0x00000000,1,15,FLAG_CY ,EXCEPTION_NONE ,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,703,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x40000000,0x00000002,0 ,1,63,0x80000000,1,15,0 ,EXCEPTION_NONE ,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,704,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x40000000,0x00000004,0 ,1,63,0x00000000,1,15,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); + + transaction_in.push_back(execute_transaction(_param,0,0,0,800,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00000001,0x00000001,0 ,1,63,0x00000001,1,15,0 ,EXCEPTION_NONE ,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,801,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00002107,0x00001981,0 ,1,63,0x034a5387,1,15,0 ,EXCEPTION_NONE ,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,802,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00048698,0x0000dead,0 ,1,63,0xefc6c4b8,1,15,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,803,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x40000000,0x00000002,0 ,1,63,0x80000000,1,15,0 ,EXCEPTION_NONE ,0)); + transaction_in.push_back(execute_transaction(_param,0,0,0,804,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x40000000,0x00000004,0 ,1,63,0x00000000,1,15,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp (revision 104) @@ -613,4 +613,7 @@ else { + LABEL("out_MEMORY_OUT_DATA_RD[0]->read() : 0x%.8x",out_MEMORY_OUT_DATA_RD[0]->read()); + LABEL("data_wait : 0x%.8x",tab_request[packet_id]._data_wait); + TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD[0]->read(), tab_request[packet_id]._data_wait); } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h (revision 104) @@ -65,5 +65,6 @@ public : Tdcache_address_t _mask_address_lsb ; public : Tdcache_address_t _mask_address_msb ; - + public : Tdcache_address_t _mask_check_hit_byte ; + //-----[ methods ]----------------------------------------------------------- public : Parameters (uint32_t size_store_queue , Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h (revision 104) @@ -147,6 +147,4 @@ #define must_check(x) (is_operation_memory_load(x)) -#define MASK_CHECK_BYTE_HIT 0xff // 1111_1111 - typedef enum { Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (revision 104) @@ -74,4 +74,5 @@ log_printf(TRACE,Load_store_unit,FUNCTION," * data (old) : %.8x",data_old); log_printf(TRACE,Load_store_unit,FUNCTION," * data (new) : %.8x",data_new); + log_printf(TRACE,Load_store_unit,FUNCTION," * address : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._address); log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata); log_printf(TRACE,Load_store_unit,FUNCTION," * shift : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift); @@ -86,4 +87,7 @@ memory_out_data_rd = (have_exception)?data_old:data_new; memory_out_exception = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?EXCEPTION_MEMORY_LOAD_SPECULATIVE:exception; + + log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",exception); + log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",memory_out_exception); break; // we have find a entry !!! stop the search @@ -203,7 +207,7 @@ // FIXME : il peut avoir plusieurs store avec le même paquet_id ... pour l'instant pas très grave car pas de retour (enfin seul les bus error sont des retours) dcache_req_packet_id = DCACHE_REQ_IS_STORE(reg_STORE_QUEUE_PTR_READ); - dcache_req_address = _store_queue [reg_STORE_QUEUE_PTR_READ]._address ; + dcache_req_address = _store_queue [reg_STORE_QUEUE_PTR_READ]._address; dcache_req_type = operation_to_dcache_type(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation); - dcache_req_wdata = _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata ; + dcache_req_wdata = _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata; } } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (revision 104) @@ -57,7 +57,9 @@ for (uint32_t i=0, nb_check=0; (nb_check<_param->_nb_port_check) and (i<_param->_size_load_queue); i++) { + // Get an index from load queue uint32_t index_load = (i + reg_LOAD_QUEUE_CHECK_PRIORITY)%_param->_size_load_queue; - - if (((_load_queue[index_load]._state == LOAD_QUEUE_WAIT_CHECK) or + + // Test if this load must ckecked store queue + if (((_load_queue[index_load]._state == LOAD_QUEUE_WAIT_CHECK) or (_load_queue[index_load]._state == LOAD_QUEUE_COMMIT_CHECK) or (_load_queue[index_load]._state == LOAD_QUEUE_CHECK)) and @@ -69,6 +71,6 @@ // find a entry that it need a check - Tlsq_ptr_t index_store = _load_queue[index_load]._store_queue_ptr_write; + // Init variable bool end_check = false; bool change_state = false; @@ -95,4 +97,5 @@ log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store); + // switch on store_queue state switch (_store_queue[index_store]._state) { @@ -107,5 +110,5 @@ bool test_thread_id = true; - // Test thread id. + // Test thread id if (_param->_have_port_context_id) test_thread_id &= (_load_queue[index_load]._context_id == _store_queue[index_store]._context_id); @@ -117,6 +120,7 @@ if (test_thread_id) { + // the load and store are in the same thread. Now, we must test address. + log_printf(TRACE,Load_store_unit,FUNCTION," * load and store is the same thread."); - // the load and store are in the same thread. Now, we must test address. Tdcache_address_t load_addr = _load_queue [index_load ]._address; Tdcache_address_t store_addr = _store_queue[index_store]._address; @@ -126,5 +130,5 @@ log_printf(TRACE,Load_store_unit,FUNCTION," * load_addr & mask_address_msb : %.8x.",load_addr & _param->_mask_address_msb); log_printf(TRACE,Load_store_unit,FUNCTION," * store_addr & mask_address_msb : %.8x.",store_addr & _param->_mask_address_msb); - // Test if the both address target the same word + // Test if the both address target the same "word" if ((load_addr & _param->_mask_address_msb) == (store_addr & _param->_mask_address_msb)) @@ -143,11 +147,17 @@ // the only case is (4) + // Read data Tgeneral_data_t load_data = _load_queue [index_load ]._rdata ; Tgeneral_data_t store_data = _store_queue[index_store]._wdata ; - log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (init) : %.8x",load_data); - log_printf(TRACE,Load_store_unit,FUNCTION," * store_data (init) : %.8x",store_data); + log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (before): 0x%.8x",load_data); + log_printf(TRACE,Load_store_unit,FUNCTION," * store_data (before): 0x%.8x",store_data); + + uint32_t store_nb_byte = (1<_mask_address_lsb); - uint32_t store_num_byte_max = store_num_byte_min+(1<> 0 + // lw 0 : 0 1 2 3 >> 0 -4 + // lw 4 : 4 5 6 7 >> 32 +4 + // lh 0 : 0 1 >> 0 -6 + // lh 2 : 2 3 >> 16 -2 + // lh 4 : 4 5 >> 32 +2 + // lh 6 : 6 7 >> 48 +6 + // lb 0 : 0 >> 0 -7 + // lb 1 : 1 >> 8 -5 + // lb 2 : 2 >> 16 -3 + // lb 3 : 3 >> 24 -1 + // lb 4 : 4 >> 32 +1 + // lb 5 : 5 >> 40 +3 + // lb 6 : 6 >> 48 +5 + // lb 7 : 7 >> 56 +7 + + // diff : (store_nb_byte + load_nb_byte) - 2*nb_load_byte*((num_store_byte+1) + + // store duplicate = all store access can be see as full size_data store + uint32_t load_nb_byte = (1<>3 : %d",(_param->_size_general_data>>3)); +// log_printf(TRACE,Load_store_unit,FUNCTION," * load_nb_byte : %d",load_nb_byte); +// log_printf(TRACE,Load_store_unit,FUNCTION," * x = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*(num_store_byte/load_nb_byte+1)) = %d+%d-%d*%d = %d" +// , (_param->_size_general_data>>3) +// , load_nb_byte +// , 2*load_nb_byte +// ,((num_store_byte/load_nb_byte)+1) +// ,((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1))); + + + num_load_byte =num_store_byte+((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1)); + } + else + { + // sd 0 : 0 1 2 3 4 5 6 7 + // ld 0 : 0 1 2 3 4 5 6 7 >> 0 + // lw 0 : 4 5 6 7 >> 0 + // lw 4 : 0 1 2 3 >> 32 + // lh 0 : 6 7 >> 0 + // lh 2 : 4 5 >> 16 + // lh 4 : 2 3 >> 32 + // lh 6 : 0 1 >> 48 + // lb 0 : 7 >> 0 + // lb 1 : 6 >> 8 + // lb 2 : 5 >> 16 + // lb 3 : 4 >> 24 + // lb 4 : 3 >> 32 + // lb 5 : 2 >> 40 + // lb 6 : 1 >> 48 + // lb 7 : 0 >> 56 + + num_load_byte = num_store_byte; + } + + uint32_t mask = 1<(load_data, store_data, index+8-1, index); +// log_printf(TRACE,Load_store_unit,FUNCTION," * interval store : [%d:%d]",num_store_bit_max,num_store_bit_min); + log_printf(TRACE,Load_store_unit,FUNCTION," * interval store : [..:%d]",num_store_bit_min); + log_printf(TRACE,Load_store_unit,FUNCTION," * interval load : [%d:%d]",num_load_bit_max,num_load_bit_min); + log_printf(TRACE,Load_store_unit,FUNCTION," * rdata_old : 0x%.8x", load_data); + + load_data = ((((store_data>>num_store_bit_min) & 0xff) << num_load_bit_min) | + mask_not(load_data,num_load_bit_max,num_load_bit_min)); + _load_queue[index_load]._check_hit_byte |= mask; _load_queue[index_load]._check_hit = 1; change_state = true; - log_printf(TRACE,Load_store_unit,FUNCTION," * rdata_new : %.8x", load_data); + log_printf(TRACE,Load_store_unit,FUNCTION," * rdata_new : 0x%.8x", load_data); } } _load_queue[index_load]._rdata = load_data; + log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (after) : 0x%.8x",load_data); log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x",_load_queue[index_load]._check_hit); @@ -182,6 +274,7 @@ log_printf(TRACE,Load_store_unit,FUNCTION," * mask_end_check : %x",(-1& _param->_mask_address_lsb)); + log_printf(TRACE,Load_store_unit,FUNCTION," * mask_check_hit_byte: %x",_param->_mask_check_hit_byte); // The check is finish if all bit is set - end_check = (_load_queue[index_load]._check_hit_byte == MASK_CHECK_BYTE_HIT); + end_check = (_load_queue[index_load]._check_hit_byte == _param->_mask_check_hit_byte); } } @@ -387,5 +480,5 @@ // reordering data - _store_queue [index]._wdata = duplicate(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0); + _store_queue [index]._wdata = duplicate(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0); // _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]); } @@ -500,5 +593,5 @@ (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1)) { - log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ[0]"); + log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ [0]"); switch (internal_DCACHE_REQ_SELECT_QUEUE) @@ -542,5 +635,4 @@ bool have_exception = (exception != EXCEPTION_MEMORY_NONE); - if (have_exception) _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT; @@ -570,23 +662,30 @@ Tdcache_address_t address = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address; Tdcache_address_t address_lsb = (address & _param->_mask_address_lsb); - Tdcache_address_t check_hit_byte = gen_mask_not(address_lsb+memory_access(operation)+1,address_lsb); - _load_queue [ptr_write]._context_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id ; - _load_queue [ptr_write]._front_end_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id ; - _load_queue [ptr_write]._ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id ; - _load_queue [ptr_write]._packet_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._packet_id ; - _load_queue [ptr_write]._operation = operation; + Tdcache_address_t check_hit_byte = gen_mask_not(address_lsb+(memory_size(operation)>>3)-1,address_lsb) & _param->_mask_check_hit_byte; + + log_printf(TRACE,Load_store_unit,FUNCTION," * address : 0x%.8x", address); + log_printf(TRACE,Load_store_unit,FUNCTION," * address_lsb : 0x%.8x", address_lsb); + log_printf(TRACE,Load_store_unit,FUNCTION," * operation : %d", operation); + log_printf(TRACE,Load_store_unit,FUNCTION," * memory_size : %d", memory_size(operation)); + log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : 0x%x", check_hit_byte); + + _load_queue [ptr_write]._context_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id; + _load_queue [ptr_write]._front_end_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id; + _load_queue [ptr_write]._ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id; + _load_queue [ptr_write]._packet_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._packet_id; + _load_queue [ptr_write]._operation = operation; _load_queue [ptr_write]._store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write; - _load_queue [ptr_write]._address = address; - _load_queue [ptr_write]._check_hit_byte = check_hit_byte; - _load_queue [ptr_write]._check_hit = 0; - _load_queue [ptr_write]._shift = address<<3; - _load_queue [ptr_write]._is_load_signed = is_operation_memory_load_signed(operation); - _load_queue [ptr_write]._access_size = memory_size(operation); + _load_queue [ptr_write]._address = address; + _load_queue [ptr_write]._check_hit_byte = check_hit_byte; + _load_queue [ptr_write]._check_hit = 0; + _load_queue [ptr_write]._shift = address_lsb<<3;// *8 + _load_queue [ptr_write]._is_load_signed = is_operation_memory_load_signed(operation); + _load_queue [ptr_write]._access_size = memory_size(operation); // NOTE : if have an exception, must write in register, because a depend instruction wait the load data. - _load_queue [ptr_write]._write_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._write_rd ; + _load_queue [ptr_write]._write_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._write_rd ; - _load_queue [ptr_write]._num_reg_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._num_reg_rd ; - _load_queue [ptr_write]._exception = exception; - _load_queue [ptr_write]._rdata = address; // to the exception + _load_queue [ptr_write]._num_reg_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._num_reg_rd ; + _load_queue [ptr_write]._exception = exception; + _load_queue [ptr_write]._rdata = address; // to the exception log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); @@ -628,5 +727,20 @@ #endif - _load_queue [packet_id]._rdata = rdata; + Tdcache_data_t data = _load_queue [packet_id]._rdata; + + log_printf(TRACE,Load_store_unit,FUNCTION," * data construction"); + log_printf(TRACE,Load_store_unit,FUNCTION," * data from cache : 0x%.8x",rdata); + log_printf(TRACE,Load_store_unit,FUNCTION," * data (before) : 0x%.8x", data); + log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : 0x%x" ,_load_queue [packet_id]._check_hit_byte); + for (uint32_t i=0;i<(_param->_size_general_data>>3)/*8*/; ++i) + // Test if this byte has been checked + if ((_load_queue [packet_id]._check_hit_byte & (1<(data,rdata,((i+1)<<3)-1,i<<3); + } + log_printf(TRACE,Load_store_unit,FUNCTION," * data (after) : 0x%.8x", data); + + _load_queue [packet_id]._rdata = data; if (error != DCACHE_ERROR_NONE) Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp (revision 104) @@ -64,4 +64,8 @@ _mask_address_lsb = gen_mask(log2(size_general_data/8)); _mask_address_msb = gen_mask(size_general_data) << log2(size_general_data/8); + _mask_check_hit_byte = 0; + + for (uint32_t i=0; i<(size_general_data>>3) /*8*/; ++i) + _mask_check_hit_byte |= (1<_nb_rename_unit,_param->_nb_inst_retire[it1]); //ALLOC2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_ID ,"out_RETIRE_RENAME_UNIT_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); - ALLOC2_SC_SIGNAL(out_RETIRE_EVENT_STATE ,"out_RETIRE_EVENT_STATE ",Tevent_state_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); ALLOC2_SC_SIGNAL(out_RETIRE_USE_STORE_QUEUE ,"out_RETIRE_USE_STORE_QUEUE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); ALLOC2_SC_SIGNAL(out_RETIRE_USE_LOAD_QUEUE ,"out_RETIRE_USE_LOAD_QUEUE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); @@ -114,4 +113,9 @@ ALLOC2_SC_SIGNAL(out_RETIRE_NUM_REG_RE_PHY_OLD ,"out_RETIRE_NUM_REG_RE_PHY_OLD ",Tspecial_address_t,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); ALLOC2_SC_SIGNAL(out_RETIRE_NUM_REG_RE_PHY_NEW ,"out_RETIRE_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + + ALLOC2_SC_SIGNAL(out_RETIRE_EVENT_VAL ,"out_RETIRE_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_ACK ," in_RETIRE_EVENT_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_EVENT_STATE ,"out_RETIRE_EVENT_STATE ",Tevent_state_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC1_SC_SIGNAL( in_COMMIT_VAL ," in_COMMIT_VAL ",Tcontrol_t ,_param->_nb_inst_commit); ALLOC1_SC_SIGNAL(out_COMMIT_ACK ,"out_COMMIT_ACK ",Tcontrol_t ,_param->_nb_inst_commit); @@ -231,5 +235,4 @@ INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); //INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); - INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_EVENT_STATE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_USE_STORE_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_USE_LOAD_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); @@ -251,16 +254,19 @@ INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); - INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_VAL ,_param->_nb_inst_commit); - INSTANCE1_SC_SIGNAL(_Commit_unit,out_COMMIT_ACK ,_param->_nb_inst_commit); - INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_WEN ,_param->_nb_inst_commit); - if (_param->_have_port_rob_ptr ) - INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_PACKET_ID ,_param->_nb_inst_commit); -//INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_OPERATION ,_param->_nb_inst_commit); -//INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_TYPE ,_param->_nb_inst_commit); - INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_FLAGS ,_param->_nb_inst_commit); - INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_EXCEPTION ,_param->_nb_inst_commit); - INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_NO_SEQUENCE ,_param->_nb_inst_commit); - INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_ADDRESS ,_param->_nb_inst_commit); - INSTANCE1_SC_SIGNAL(_Commit_unit,out_COMMIT_NUM_REG_RD ,_param->_nb_inst_commit); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_RETIRE_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_VAL ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit,out_COMMIT_ACK ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_WEN ,_param->_nb_inst_commit); + if (_param->_have_port_rob_ptr ) + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_PACKET_ID ,_param->_nb_inst_commit); +//INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_OPERATION ,_param->_nb_inst_commit); +//INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_TYPE ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_FLAGS ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_EXCEPTION ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_NO_SEQUENCE ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_ADDRESS ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit,out_COMMIT_NUM_REG_RD ,_param->_nb_inst_commit); INSTANCE1_SC_SIGNAL(_Commit_unit,out_REEXECUTE_VAL ,_param->_nb_inst_reexecute); INSTANCE1_SC_SIGNAL(_Commit_unit, in_REEXECUTE_ACK ,_param->_nb_inst_reexecute); @@ -636,5 +642,4 @@ DELETE2_SC_SIGNAL(out_RETIRE_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); //DELETE2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); - DELETE2_SC_SIGNAL(out_RETIRE_EVENT_STATE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); DELETE2_SC_SIGNAL(out_RETIRE_USE_STORE_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); DELETE2_SC_SIGNAL(out_RETIRE_USE_LOAD_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); @@ -655,4 +660,7 @@ DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_RETIRE_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context[it1]); DELETE1_SC_SIGNAL( in_COMMIT_VAL ,_param->_nb_inst_commit); DELETE1_SC_SIGNAL(out_COMMIT_ACK ,_param->_nb_inst_commit); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 104) @@ -112,5 +112,4 @@ public : SC_OUT(Tcontext_t ) *** out_RETIRE_CONTEXT_ID ;//[nb_rename_unit][nb_inst_retire] //public : SC_OUT(Tcontext_t ) *** out_RETIRE_RENAME_UNIT_ID ;//[nb_rename_unit][nb_inst_retire] - public : SC_OUT(Tevent_state_t ) *** out_RETIRE_EVENT_STATE ;//[nb_rename_unit][nb_inst_retire] public : SC_OUT(Tcontrol_t ) *** out_RETIRE_USE_STORE_QUEUE ;//[nb_rename_unit][nb_inst_retire] public : SC_OUT(Tcontrol_t ) *** out_RETIRE_USE_LOAD_QUEUE ;//[nb_rename_unit][nb_inst_retire] @@ -131,4 +130,9 @@ public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RE_PHY_OLD ;//[nb_rename_unit][nb_inst_retire] public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RE_PHY_NEW ;//[nb_rename_unit][nb_inst_retire] + + // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_VAL ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_RETIRE_EVENT_ACK ;//[nb_front_end][nb_context] + public : SC_OUT(Tevent_state_t ) *** out_RETIRE_EVENT_STATE ;//[nb_front_end][nb_context] // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -223,4 +227,11 @@ private : Tevent_state_t ** reg_EVENT_STATE ;//[nb_front_end][nb_context] + private : bool ** reg_EVENT_FLUSH ;//[nb_front_end][nb_context] + + private : Taddress_t ** reg_PC_PREVIOUS ;//[nb_front_end][nb_context] + private : Taddress_t ** reg_PC_CURRENT ;//[nb_front_end][nb_context] + private : Taddress_t ** reg_PC_CURRENT_IS_DS ;//[nb_front_end][nb_context] + private : Taddress_t ** reg_PC_CURRENT_IS_DS_TAKE ;//[nb_front_end][nb_context] + private : Taddress_t ** reg_PC_NEXT ;//[nb_front_end][nb_context] // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -250,4 +261,6 @@ private : Tcontrol_t ** internal_EVENT_ACK ;//[nb_front_end][nb_context] + + private : Tcontrol_t ** internal_RETIRE_EVENT_VAL ;//[nb_front_end][nb_context] #endif Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp (revision 104) @@ -81,4 +81,7 @@ internal_EVENT_ACK [i][j] = 1; PORT_WRITE(out_EVENT_ACK [i][j], internal_EVENT_ACK [i][j]); + + internal_RETIRE_EVENT_VAL [i][j] = 1; + PORT_WRITE(out_RETIRE_EVENT_VAL [i][j], internal_RETIRE_EVENT_VAL [i][j]); } @@ -152,5 +155,4 @@ (*(out_RETIRE_CONTEXT_ID [i][j])) (*(in_RETIRE_ACK [x][y])); // (*(out_RETIRE_RENAME_UNIT_ID [i][j])) (*(in_RETIRE_ACK [x][y])); - (*(out_RETIRE_EVENT_STATE [i][j])) (*(in_RETIRE_ACK [x][y])); (*(out_RETIRE_USE_STORE_QUEUE [i][j])) (*(in_RETIRE_ACK [x][y])); (*(out_RETIRE_USE_LOAD_QUEUE [i][j])) (*(in_RETIRE_ACK [x][y])); @@ -183,5 +185,4 @@ (*(out_RETIRE_CONTEXT_ID [i][j])) (*(in_SPR_WRITE_ACK [x][y])); // (*(out_RETIRE_RENAME_UNIT_ID [i][j])) (*(in_SPR_WRITE_ACK [x][y])); - (*(out_RETIRE_EVENT_STATE [i][j])) (*(in_SPR_WRITE_ACK [x][y])); (*(out_RETIRE_USE_STORE_QUEUE [i][j])) (*(in_SPR_WRITE_ACK [x][y])); (*(out_RETIRE_USE_LOAD_QUEUE [i][j])) (*(in_SPR_WRITE_ACK [x][y])); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 104) @@ -104,5 +104,4 @@ _ALLOC2_SIGNAL_OUT(out_RETIRE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); // _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_ID ,"rename_unit_id" ,Tcontext_t ,_param->_size_rename_unit_id ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); - _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STATE ,"event_state" ,Tevent_state_t ,_param->_size_event_state ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); _ALLOC2_SIGNAL_OUT(out_RETIRE_USE_STORE_QUEUE ,"use_store_queue" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); _ALLOC2_SIGNAL_OUT(out_RETIRE_USE_LOAD_QUEUE ,"use_load_queue" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); @@ -125,4 +124,13 @@ } + // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("retire_event",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_front_end,_param->_nb_context[it1]); + + _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_VAL ,VAL,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_ACK ,ACK,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state ,_param->_nb_front_end,_param->_nb_context[it1]); + } + // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { @@ -243,42 +251,42 @@ { // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - internal_BANK_INSERT_VAL = new Tcontrol_t [_param->_nb_bank]; - internal_BANK_INSERT_NUM_RENAME_UNIT = new uint32_t [_param->_nb_bank]; - internal_BANK_INSERT_NUM_INST = new uint32_t [_param->_nb_bank]; - - internal_BANK_COMMIT_VAL = new Tcontrol_t * [_param->_nb_bank]; - internal_BANK_COMMIT_NUM_INST = new uint32_t * [_param->_nb_bank]; - internal_BANK_COMMIT_ENTRY = new entry_t ** [_param->_nb_bank]; + ALLOC1(internal_BANK_INSERT_VAL ,Tcontrol_t,_param->_nb_bank); + ALLOC1(internal_BANK_INSERT_NUM_RENAME_UNIT ,uint32_t ,_param->_nb_bank); + ALLOC1(internal_BANK_INSERT_NUM_INST ,uint32_t ,_param->_nb_bank); + + ALLOC2(internal_BANK_COMMIT_VAL ,Tcontrol_t,_param->_nb_bank,_param->_nb_bank_access_commit); + ALLOC2(internal_BANK_COMMIT_NUM_INST ,uint32_t ,_param->_nb_bank,_param->_nb_bank_access_commit); + ALLOC2(internal_BANK_COMMIT_ENTRY ,entry_t * ,_param->_nb_bank,_param->_nb_bank_access_commit); + + ALLOC1(internal_BANK_RETIRE_VAL ,Tcontrol_t,_param->_nb_bank); + ALLOC1(internal_BANK_RETIRE_NUM_RENAME_UNIT ,uint32_t ,_param->_nb_bank); + ALLOC1(internal_BANK_RETIRE_NUM_INST ,uint32_t ,_param->_nb_bank); + + ALLOC1(internal_REEXECUTE_VAL ,Tcontrol_t,_param->_nb_inst_reexecute); + ALLOC1(internal_REEXECUTE_NUM_BANK ,uint32_t ,_param->_nb_inst_reexecute); + + ALLOC1(internal_BRANCH_COMPLETE_VAL ,Tcontrol_t,_param->_nb_inst_branch_complete); + ALLOC1(internal_BRANCH_COMPLETE_NUM_BANK ,uint32_t ,_param->_nb_inst_branch_complete); + + ALLOC2(internal_EVENT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context [it1]); + + ALLOC2(internal_RETIRE_EVENT_VAL ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ALLOC1(_rob ,std::list,_param->_nb_bank); - for (uint32_t i=0; i<_param->_nb_bank; i++) - { - internal_BANK_COMMIT_VAL [i] = new Tcontrol_t [_param->_nb_bank_access_commit]; - internal_BANK_COMMIT_NUM_INST [i] = new uint32_t [_param->_nb_bank_access_commit]; - internal_BANK_COMMIT_ENTRY [i] = new entry_t * [_param->_nb_bank_access_commit]; - } - - internal_BANK_RETIRE_VAL = new Tcontrol_t [_param->_nb_bank]; - internal_BANK_RETIRE_NUM_RENAME_UNIT = new uint32_t [_param->_nb_bank]; - internal_BANK_RETIRE_NUM_INST = new uint32_t [_param->_nb_bank]; - - internal_REEXECUTE_VAL = new Tcontrol_t [_param->_nb_inst_reexecute]; - internal_REEXECUTE_NUM_BANK = new uint32_t [_param->_nb_inst_reexecute]; - - internal_BRANCH_COMPLETE_VAL = new Tcontrol_t [_param->_nb_inst_branch_complete]; - internal_BRANCH_COMPLETE_NUM_BANK = new uint32_t [_param->_nb_inst_branch_complete]; - - internal_EVENT_ACK = new Tcontrol_t * [_param->_nb_front_end]; - for (uint32_t i=0; i<_param->_nb_front_end; i++) - internal_EVENT_ACK [i] = new Tcontrol_t [_param->_nb_context [i]]; - - // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - ALLOC1(_rob ,std::list,_param->_nb_bank); + ALLOC1(reg_BANK_PTR ,uint32_t ,_param->_nb_bank); + + ALLOC2(reg_NB_INST_COMMIT_ALL ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]); + ALLOC2(reg_NB_INST_COMMIT_MEM ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]); - ALLOC1(reg_BANK_PTR ,uint32_t ,_param->_nb_bank); - - ALLOC2(reg_NB_INST_COMMIT_ALL ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]); - ALLOC2(reg_NB_INST_COMMIT_MEM ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]); - - ALLOC2(reg_EVENT_STATE ,Tevent_state_t,_param->_nb_front_end,_param->_nb_context [it1]); + ALLOC2(reg_EVENT_STATE ,Tevent_state_t,_param->_nb_front_end,_param->_nb_context [it1]); + ALLOC2(reg_EVENT_FLUSH ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); + + ALLOC2(reg_PC_PREVIOUS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); + ALLOC2(reg_PC_CURRENT ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); + ALLOC2(reg_PC_CURRENT_IS_DS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); + ALLOC2(reg_PC_CURRENT_IS_DS_TAKE,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); + ALLOC2(reg_PC_NEXT ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 104) @@ -67,5 +67,4 @@ DELETE2_SIGNAL(out_RETIRE_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_context_id ); // DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_rename_unit_id ); - DELETE2_SIGNAL(out_RETIRE_EVENT_STATE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_event_state ); DELETE2_SIGNAL(out_RETIRE_USE_STORE_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); DELETE2_SIGNAL(out_RETIRE_USE_LOAD_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); @@ -87,4 +86,8 @@ DELETE2_SIGNAL(out_RETIRE_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register ); + DELETE2_SIGNAL(out_RETIRE_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1],1); + DELETE2_SIGNAL( in_RETIRE_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1],1); + DELETE2_SIGNAL(out_RETIRE_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_event_state); + DELETE1_SIGNAL( in_COMMIT_VAL ,_param->_nb_inst_commit,1 ); DELETE1_SIGNAL(out_COMMIT_ACK ,_param->_nb_inst_commit,1 ); @@ -156,32 +159,38 @@ // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] internal_BANK_INSERT_VAL ; - delete [] internal_BANK_INSERT_NUM_RENAME_UNIT; - delete [] internal_BANK_INSERT_NUM_INST ; - - delete [] internal_BANK_COMMIT_VAL ; - delete [] internal_BANK_COMMIT_NUM_INST ; - delete [] internal_BANK_COMMIT_ENTRY ; - - delete [] internal_BANK_RETIRE_VAL ; - delete [] internal_BANK_RETIRE_NUM_RENAME_UNIT; - delete [] internal_BANK_RETIRE_NUM_INST ; - - delete [] internal_REEXECUTE_VAL ; - delete [] internal_REEXECUTE_NUM_BANK ; - - delete [] internal_BRANCH_COMPLETE_VAL ; - delete [] internal_BRANCH_COMPLETE_NUM_BANK ; - - for (uint32_t i=0; i<_param->_nb_front_end; i++) - delete [] internal_EVENT_ACK [i]; - delete [] internal_EVENT_ACK; + DELETE1(internal_BANK_INSERT_VAL ,_param->_nb_bank); + DELETE1(internal_BANK_INSERT_NUM_RENAME_UNIT ,_param->_nb_bank); + DELETE1(internal_BANK_INSERT_NUM_INST ,_param->_nb_bank); + + DELETE2(internal_BANK_COMMIT_VAL ,_param->_nb_bank,_param->_nb_bank_access_commit); + DELETE2(internal_BANK_COMMIT_NUM_INST ,_param->_nb_bank,_param->_nb_bank_access_commit); + DELETE2(internal_BANK_COMMIT_ENTRY ,_param->_nb_bank,_param->_nb_bank_access_commit); + + DELETE1(internal_BANK_RETIRE_VAL ,_param->_nb_bank); + DELETE1(internal_BANK_RETIRE_NUM_RENAME_UNIT ,_param->_nb_bank); + DELETE1(internal_BANK_RETIRE_NUM_INST ,_param->_nb_bank); + + DELETE1(internal_REEXECUTE_VAL ,_param->_nb_inst_reexecute); + DELETE1(internal_REEXECUTE_NUM_BANK ,_param->_nb_inst_reexecute); + + DELETE1(internal_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); + DELETE1(internal_BRANCH_COMPLETE_NUM_BANK ,_param->_nb_inst_branch_complete); + + DELETE2(internal_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context [it1]); + + DELETE2(internal_RETIRE_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - DELETE1(_rob ,_param->_nb_bank); - DELETE1(reg_BANK_PTR ,_param->_nb_bank); - DELETE2(reg_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context [it1]); - DELETE2(reg_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context [it1]); - DELETE2(reg_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context [it1]); + DELETE1(_rob ,_param->_nb_bank); + DELETE1(reg_BANK_PTR ,_param->_nb_bank); + DELETE2(reg_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context [it1]); + DELETE2(reg_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context [it1]); + DELETE2(reg_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context [it1]); + DELETE2(reg_EVENT_FLUSH ,_param->_nb_front_end,_param->_nb_context [it1]); + DELETE2(reg_PC_PREVIOUS ,_param->_nb_front_end,_param->_nb_context [it1]); + DELETE2(reg_PC_CURRENT ,_param->_nb_front_end,_param->_nb_context [it1]); + DELETE2(reg_PC_CURRENT_IS_DS ,_param->_nb_front_end,_param->_nb_context [it1]); + DELETE2(reg_PC_CURRENT_IS_DS_TAKE,_param->_nb_front_end,_param->_nb_context [it1]); + DELETE2(reg_PC_NEXT ,_param->_nb_front_end,_param->_nb_context [it1]); } @@ -199,5 +208,4 @@ }; // end namespace multi_ooo_engine }; // end namespace core - }; // end namespace behavioural }; // end namespace morpheo Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp (revision 104) @@ -35,5 +35,4 @@ Tcontrol_t spr_write_sr_ov_val [_param->_nb_front_end][_param->_max_nb_context]; Tcontrol_t spr_write_sr_ov [_param->_nb_front_end][_param->_max_nb_context]; - // Initialisation @@ -148,5 +147,4 @@ PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id ); // PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id ); - PORT_WRITE(out_RETIRE_EVENT_STATE [x][y], reg_EVENT_STATE[front_end_id][context_id]); PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue ); PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue ); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp (revision 104) @@ -143,4 +143,10 @@ } + // =================================================================== + // =====[ RETIRE_EVENT ]============================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context [i]; j++) + PORT_WRITE(out_RETIRE_EVENT_STATE [i][j], reg_EVENT_STATE[i][j]); log_end(Commit_unit,FUNCTION); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 104) @@ -41,8 +41,15 @@ for (uint32_t j=0; j<_param->_nb_context [i]; j++) { - reg_NB_INST_COMMIT_ALL [i][j] = 0; - reg_NB_INST_COMMIT_MEM [i][j] = 0; - - reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; + reg_NB_INST_COMMIT_ALL [i][j] = 0; + reg_NB_INST_COMMIT_MEM [i][j] = 0; + + reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; + reg_EVENT_FLUSH [i][j] = false; + +// reg_PC_PREVIOUS [i][j] = (0x100-4)>>2; + reg_PC_CURRENT [i][j] = (0x100 )>>2; + reg_PC_CURRENT_IS_DS [i][j] = 0; + reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0; +// reg_PC_NEXT [i][j] = (0x100+4)>>2; } @@ -62,8 +69,25 @@ switch (reg_EVENT_STATE [i][j]) { - case EVENT_STATE_EVENT : reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; break; - case EVENT_STATE_END : reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; break; + case EVENT_STATE_EVENT : + { + if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j]) + reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; + break; + } + case EVENT_STATE_WAITEND : + { + if (reg_NB_INST_COMMIT_ALL [i][j] == 0) + { + reg_EVENT_STATE [i][j] = EVENT_STATE_END; + reg_EVENT_FLUSH [i][j] = false; + } + break; + } + case EVENT_STATE_END : + { + reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; + break; + } // case EVENT_STATE_NO_EVENT : -// case EVENT_STATE_WAITEND : default : break; } @@ -324,6 +348,7 @@ { reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; - - // !!!!!!!!!!! Compute address + reg_EVENT_FLUSH [front_end_id][context_id] = true; + + // TODO Compute address !!!!!!!!!!! } @@ -332,7 +357,4 @@ if (type == TYPE_MEMORY) reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; - - if (reg_NB_INST_COMMIT_ALL [front_end_id][context_id] == 0) - reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_END; reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank; @@ -416,6 +438,6 @@ Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; - Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; - Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); +// Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; +// Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); // is a valid instruction ? @@ -433,9 +455,12 @@ // ....... max ...X... min ....... KO - Tcontrol_t is_valid = ((depth == depth_min) or - depth_full or - ((depth_min <= depth_max)? - ((depth >= depth_min) and (depth <=depth_max)): - ((depth >= depth_min) or (depth <=depth_max)))); +// Tcontrol_t is_valid = ((depth == depth_min) or +// depth_full or +// ((depth_min <= depth_max)? +// ((depth >= depth_min) and (depth <=depth_max)): +// ((depth >= depth_min) or (depth <=depth_max)))); + + bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; + Tcontrol_t is_valid = ((depth == depth_min) and not flush); log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d]",i); @@ -443,5 +468,6 @@ log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth ); log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min); - log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); +// log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); + log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); //------------------------------------------------------ @@ -522,9 +548,12 @@ for (uint32_t i=0; i<_param->_nb_front_end; i++) for (uint32_t j=0; j<_param->_nb_context [i]; j++) - log_printf(TRACE,Commit_unit,FUNCTION," * num_inst[%d][%d] all : %d, mem : %d",i,j,reg_NB_INST_COMMIT_ALL[i][j],reg_NB_INST_COMMIT_MEM[i][j]); + { + log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] num_inst_all : %d, num_inst_mem : %d",i,j,reg_NB_INST_COMMIT_ALL[i][j],reg_NB_INST_COMMIT_MEM[i][j]); + log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] state : %s",i,j,toString(reg_EVENT_STATE [i][j]).c_str()); + } for (uint32_t i=0; i<_param->_nb_bank; i++) { - log_printf(TRACE,Commit_unit,FUNCTION," * Bank[%d] size : %d, ptr : %d",i,(int)_rob[i].size(), reg_BANK_PTR [i]); + log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",i,(int)_rob[i].size(), reg_BANK_PTR [i]); #ifdef STATISTICS Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp (revision 104) @@ -81,5 +81,4 @@ ALLOC1_SC_SIGNAL( in_RETIRE_FRONT_END_ID ," in_RETIRE_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_CONTEXT_ID ," in_RETIRE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_retire); - ALLOC1_SC_SIGNAL( in_RETIRE_EVENT_STATE ," in_RETIRE_EVENT_STATE ",Tevent_state_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_WRITE_RD ," in_RETIRE_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_WRITE_RE ," in_RETIRE_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_retire); @@ -90,4 +89,8 @@ ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE_RD_PHY_OLD,"out_RETIRE_RESTORE_RD_PHY_OLD",Tcontrol_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE_RE_PHY_OLD,"out_RETIRE_RESTORE_RE_PHY_OLD",Tcontrol_t ,_param->_nb_inst_retire); + + ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_VAL ," in_RETIRE_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_EVENT_ACK ,"out_RETIRE_EVENT_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_STATE ," in_RETIRE_EVENT_STATE ",Tevent_state_t ,_param->_nb_front_end,_param->_nb_context[it1]); /******************************************************** @@ -136,5 +139,4 @@ if (_param->_have_port_context_id) INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_CONTEXT_ID ,_param->_nb_inst_retire); - INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_EVENT_STATE ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_WRITE_RD ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_WRITE_RE ,_param->_nb_inst_retire); @@ -145,4 +147,8 @@ INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire); + + INSTANCE2_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1]); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -192,4 +198,8 @@ SC_START(0); LABEL("Initialisation"); + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + in_RETIRE_EVENT_VAL [i][j]->write(1); LABEL("Reset"); @@ -251,9 +261,9 @@ Tcontext_t front_end_id = rand() % _param->_nb_front_end; + Tcontext_t context_id = rand() % (_param->_nb_context[front_end_id]); in_RETIRE_VAL [i]->write(val); in_RETIRE_FRONT_END_ID [i]->write(front_end_id); - in_RETIRE_CONTEXT_ID [i]->write(rand() % (_param->_nb_context[front_end_id])); - in_RETIRE_EVENT_STATE [i]->write(EVENT_STATE_NO_EVENT); + in_RETIRE_CONTEXT_ID [i]->write(context_id); in_RETIRE_WRITE_RD [i]->write(rand() % 2); in_RETIRE_WRITE_RE [i]->write(rand() % 2); @@ -262,4 +272,6 @@ in_RETIRE_NUM_REG_RD_PHY_OLD [i]->write(rand() % _param->_nb_general_register); in_RETIRE_NUM_REG_RE_PHY_OLD [i]->write(rand() % _param->_nb_special_register); + + in_RETIRE_EVENT_STATE [front_end_id][context_id]->write(EVENT_STATE_NO_EVENT); } @@ -332,8 +344,9 @@ in_RETIRE_FRONT_END_ID [i]->write(retire_front_end_id [i]); in_RETIRE_CONTEXT_ID [i]->write(retire_context_id [i]); - in_RETIRE_EVENT_STATE [i]->write(EVENT_STATE_EVENT); in_RETIRE_WRITE_RD [i]->write(0); in_RETIRE_WRITE_RE [i]->write(0); + in_RETIRE_EVENT_STATE [retire_front_end_id [i]][retire_context_id [i]]->write(EVENT_STATE_EVENT); + do { @@ -389,5 +402,4 @@ in_RETIRE_FRONT_END_ID [i]->write(retire_front_end_id [i]); in_RETIRE_CONTEXT_ID [i]->write(retire_context_id [i]); - in_RETIRE_EVENT_STATE [i]->write(EVENT_STATE_WAITEND); in_RETIRE_WRITE_RD [i]->write(rand() % 2); in_RETIRE_WRITE_RE [i]->write(rand() % 2); @@ -396,4 +408,6 @@ in_RETIRE_NUM_REG_RD_PHY_OLD [i]->write(rand() % _param->_nb_general_register); in_RETIRE_NUM_REG_RE_PHY_OLD [i]->write(rand() % _param->_nb_special_register); + + in_RETIRE_EVENT_STATE [retire_front_end_id [i]][retire_context_id [i]]->write(EVENT_STATE_WAITEND); } @@ -517,5 +531,4 @@ if (_param->_have_port_context_id) delete [] in_RETIRE_CONTEXT_ID ; - delete [] in_RETIRE_EVENT_STATE ; delete [] in_RETIRE_WRITE_RD ; delete [] in_RETIRE_WRITE_RE ; @@ -527,4 +540,7 @@ delete [] out_RETIRE_RESTORE_RE_PHY_OLD; + DELETE2_SC_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1]); #endif Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h (revision 104) @@ -96,5 +96,4 @@ public : SC_IN (Tcontext_t ) ** in_RETIRE_FRONT_END_ID ;//[nb_inst_retire] public : SC_IN (Tcontext_t ) ** in_RETIRE_CONTEXT_ID ;//[nb_inst_retire] - public : SC_IN (Tevent_state_t ) ** in_RETIRE_EVENT_STATE ;//[nb_inst_retire] public : SC_IN (Tcontrol_t ) ** in_RETIRE_WRITE_RD ;//[nb_inst_retire] public : SC_IN (Tcontrol_t ) ** in_RETIRE_WRITE_RE ;//[nb_inst_retire] @@ -105,4 +104,9 @@ public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RESTORE_RD_PHY_OLD;//[nb_inst_retire] public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RESTORE_RE_PHY_OLD;//[nb_inst_retire] + + // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_RETIRE_EVENT_VAL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_ACK ;//[nb_front_end][nb_context] + public : SC_IN (Tevent_state_t ) *** in_RETIRE_EVENT_STATE ;//[nb_front_end][nb_context] // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -118,4 +122,5 @@ private : Tcontrol_t * internal_INSERT_ACK; //[nb_inst_insert] private : Tcontrol_t * internal_RETIRE_ACK; //[nb_inst_retire] + public : Tcontrol_t ** internal_RETIRE_EVENT_ACK ;//[nb_front_end][nb_context] private : bool *** internal_rat_gpr_update_table; //[nb_front_end][nb_context][nb_general_register_logic] Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp (revision 104) @@ -84,4 +84,5 @@ PORT_WRITE(out_INSERT_ACK[i],internal_INSERT_ACK [i]); } + for (uint32_t i=0; i<_param->_nb_inst_retire; i++) { @@ -90,4 +91,12 @@ PORT_WRITE(out_RETIRE_ACK[i],internal_RETIRE_ACK [i]); } + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + { + internal_RETIRE_EVENT_ACK [i][j] = 1; + + PORT_WRITE(out_RETIRE_EVENT_ACK[i][j],internal_RETIRE_EVENT_ACK [i][j]); + } log_printf(INFO,Register_Address_Translation_unit,FUNCTION,"Method - transition"); @@ -119,6 +128,5 @@ << (*(in_RENAME_NUM_REG_RD_LOG [i])) << (*(in_RENAME_NUM_REG_RE_LOG [i])); - } - + } # ifdef SYSTEMCASS_SPECIFIC @@ -138,10 +146,13 @@ sensitive << (*(in_RETIRE_CONTEXT_ID [i])); - sensitive << (*(in_RETIRE_EVENT_STATE [i])) - << (*(in_RETIRE_WRITE_RD [i])) + sensitive << (*(in_RETIRE_WRITE_RD [i])) << (*(in_RETIRE_WRITE_RE [i])) << (*(in_RETIRE_NUM_REG_RD_LOG [i])) << (*(in_RETIRE_NUM_REG_RE_LOG [i])); } + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + sensitive << (*(in_RETIRE_EVENT_STATE [i][j])); # ifdef SYSTEMCASS_SPECIFIC Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp (revision 104) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h" +#include "Behavioural/include/Allocation.h" #include "Behavioural/include/Allocation.h" @@ -100,5 +101,4 @@ ALLOC1_SIGNAL_IN ( in_RETIRE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); ALLOC1_SIGNAL_IN ( in_RETIRE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC1_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"event_state" ,Tevent_state_t ,_param->_size_event_state ); ALLOC1_SIGNAL_IN ( in_RETIRE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_RETIRE_WRITE_RE ,"write_re" ,Tcontrol_t ,1); @@ -111,9 +111,19 @@ } + // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]); + } + if (usage_is_set(_usage,USE_SYSTEMC)) { - internal_RENAME_ACK = new Tcontrol_t [_param->_nb_inst_insert]; - internal_INSERT_ACK = new Tcontrol_t [_param->_nb_inst_insert]; - internal_RETIRE_ACK = new Tcontrol_t [_param->_nb_inst_retire]; + ALLOC1(internal_RENAME_ACK ,Tcontrol_t,_param->_nb_inst_insert); + ALLOC1(internal_INSERT_ACK ,Tcontrol_t,_param->_nb_inst_insert); + ALLOC1(internal_RETIRE_ACK ,Tcontrol_t,_param->_nb_inst_retire); + ALLOC2(internal_RETIRE_EVENT_ACK ,Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); rat_gpr = new Tgeneral_address_t ** [_param->_nb_front_end]; Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp (revision 104) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -65,5 +66,4 @@ if (_param->_have_port_context_id) delete [] in_RETIRE_CONTEXT_ID ; - delete [] in_RETIRE_EVENT_STATE ; delete [] in_RETIRE_WRITE_RD ; delete [] in_RETIRE_WRITE_RE ; @@ -75,7 +75,12 @@ delete [] out_RETIRE_RESTORE_RE_PHY_OLD; - delete [] internal_RENAME_ACK; - delete [] internal_INSERT_ACK; - delete [] internal_RETIRE_ACK; + DELETE1(internal_RENAME_ACK ,_param->_nb_inst_insert); + DELETE1(internal_INSERT_ACK ,_param->_nb_inst_insert); + DELETE1(internal_RETIRE_ACK ,_param->_nb_inst_retire); + DELETE2(internal_RETIRE_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); + + DELETE2_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL(out_RETIRE_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state); delete [] rat_gpr ; Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp (revision 104) @@ -43,28 +43,17 @@ // init -> need't restore old value - Tcontrol_t retire_restore_rd_phy_old = false; - Tcontrol_t retire_restore_re_phy_old = false; - Tevent_state_t event_state = PORT_READ(in_RETIRE_EVENT_STATE [i]); + Tcontrol_t retire_restore_rd_phy_old = false; + Tcontrol_t retire_restore_re_phy_old = false; + + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; + Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; // Test if event -> need restore ? - if (event_state != EVENT_STATE_NO_EVENT) + if (PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]) != EVENT_STATE_NO_EVENT) { - Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; - Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Have event"); log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id ); - // Test if event have just occure -> reset update_table - if (event_state == EVENT_STATE_EVENT) - { - // Reset update_table - for (uint32_t j=0; j<_param->_nb_general_register_logic; j++) - internal_rat_gpr_update_table[front_end_id][context_id][j] = 0; - for (uint32_t j=0; j<_param->_nb_special_register_logic; j++) - internal_rat_spr_update_table[front_end_id][context_id][j] = 0; - } - // Test and update update table if (PORT_READ(in_RETIRE_WRITE_RD [i])) Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp (revision 104) @@ -60,4 +60,6 @@ if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i]) { + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * INSERT [%d]",i); + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; @@ -71,4 +73,22 @@ // ===================================================== + // ====[ RETIRE_EVENT ]================================= + // ===================================================== + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j]) + // Test if event have just occure + if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT) + { + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Reset Update Table"); + + // Reset update_table + for (uint32_t k=0; k<_param->_nb_general_register_logic; k++) + rat_gpr_update_table [i][j][k] = 0; + for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) + rat_spr_update_table [i][j][k] = 0; + } + + // ===================================================== // ====[ RETIRE ]======================================= // ===================================================== @@ -78,22 +98,20 @@ if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) { + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i); + // if no event : no effect, because the RAT content the most recently register // but if they have a event (exception or miss speculation), the rat must restore the oldest value // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register // the retire interface became of the Re Order Buffer, also is in program sequence ! - if (PORT_READ(in_RETIRE_EVENT_STATE [i]) != EVENT_STATE_NO_EVENT) + + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; + Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; + Tevent_state_t event_state = PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]); + + if (event_state != EVENT_STATE_NO_EVENT) { - Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; - Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; - - // Test if event have just occure - if (PORT_READ(in_RETIRE_EVENT_STATE [i]) == EVENT_STATE_EVENT) - { - // Reset update_table - for (uint32_t j=0; j<_param->_nb_general_register_logic; j++) - rat_gpr_update_table[front_end_id][context_id][j] = 0; - for (uint32_t j=0; j<_param->_nb_special_register_logic; j++) - rat_spr_update_table[front_end_id][context_id][j] = 0; - } + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * event_state : %d",event_state); // Test if write and have not a previous update @@ -102,14 +120,12 @@ Tgeneral_address_t rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * retire[%d]",i); - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id ); - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * rd_log : %d",rd_log ); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * retire RD"); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * rd_log : %d",rd_log); // if (RETIRE_RESTORE_RD_PHY_OLD [i]) - if (rat_gpr_update_table[front_end_id][context_id][rd_log] == 0) - { - rat_gpr [front_end_id][context_id][rd_log] = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); - rat_gpr_update_table[front_end_id][context_id][rd_log] = 1; + if (rat_gpr_update_table [front_end_id][context_id][rd_log] == 0) + { + rat_gpr [front_end_id][context_id][rd_log] = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); + rat_gpr_update_table [front_end_id][context_id][rd_log] = 1; } } @@ -119,9 +135,12 @@ Tspecial_address_t re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * retire RE"); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * re_log : %d",re_log); + // if (RETIRE_RESTORE_RE_PHY_OLD [i]) - if (rat_spr_update_table[front_end_id][context_id][re_log] == 0) - { - rat_spr [front_end_id][context_id][re_log] = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); - rat_spr_update_table[front_end_id][context_id][re_log] = 1; + if (rat_spr_update_table [front_end_id][context_id][re_log] == 0) + { + rat_spr [front_end_id][context_id][re_log] = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); + rat_spr_update_table [front_end_id][context_id][re_log] = 1; } } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/src/test.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/src/test.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/src/test.cpp (revision 104) @@ -91,5 +91,4 @@ ALLOC1_SC_SIGNAL( in_RETIRE_FRONT_END_ID ," in_RETIRE_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_CONTEXT_ID ," in_RETIRE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_retire); - ALLOC1_SC_SIGNAL( in_RETIRE_EVENT_STATE ," in_RETIRE_EVENT_STATE ",Tevent_state_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_READ_RA ," in_RETIRE_READ_RA ",Tcontrol_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ," in_RETIRE_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_retire); @@ -106,4 +105,8 @@ ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD," in_RETIRE_NUM_REG_RE_PHY_OLD",Tspecial_address_t,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW," in_RETIRE_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_nb_inst_retire); + + ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_VAL ," in_RETIRE_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_EVENT_ACK ,"out_RETIRE_EVENT_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_STATE ," in_RETIRE_EVENT_STATE ",Tevent_state_t ,_param->_nb_front_end,_param->_nb_context[it1]); /******************************************************** @@ -163,5 +166,4 @@ if (_param->_have_port_context_id) INSTANCE1_SC_SIGNAL(_Register_translation_unit, in_RETIRE_CONTEXT_ID ,_param->_nb_inst_retire); - INSTANCE1_SC_SIGNAL(_Register_translation_unit, in_RETIRE_EVENT_STATE ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Register_translation_unit, in_RETIRE_READ_RA ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Register_translation_unit, in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire); @@ -178,4 +180,8 @@ INSTANCE1_SC_SIGNAL(_Register_translation_unit, in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Register_translation_unit, in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire); + + INSTANCE2_SC_SIGNAL(_Register_translation_unit, in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Register_translation_unit,out_RETIRE_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Register_translation_unit, in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1]); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -264,5 +270,4 @@ delete [] in_RETIRE_FRONT_END_ID ; delete [] in_RETIRE_CONTEXT_ID ; - delete [] in_RETIRE_EVENT_STATE ; delete [] in_RETIRE_READ_RA ; delete [] in_RETIRE_NUM_REG_RA_PHY ; @@ -279,4 +284,8 @@ delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; delete [] in_RETIRE_NUM_REG_RE_PHY_NEW; + + DELETE2_SC_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1]); #endif Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Register_translation_unit.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Register_translation_unit.h (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Register_translation_unit.h (revision 104) @@ -111,5 +111,4 @@ public : SC_IN (Tcontext_t ) ** in_RETIRE_FRONT_END_ID ;//[nb_inst_retire] public : SC_IN (Tcontext_t ) ** in_RETIRE_CONTEXT_ID ;//[nb_inst_retire] - public : SC_IN (Tevent_state_t ) ** in_RETIRE_EVENT_STATE ;//[nb_inst_retire] public : SC_IN (Tcontrol_t ) ** in_RETIRE_READ_RA ;//[nb_inst_retire] public : SC_IN (Tgeneral_address_t) ** in_RETIRE_NUM_REG_RA_PHY ;//[nb_inst_retire] @@ -127,4 +126,9 @@ public : SC_IN (Tspecial_address_t) ** in_RETIRE_NUM_REG_RE_PHY_NEW;//[nb_inst_retire] + // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_RETIRE_EVENT_VAL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_ACK ;//[nb_front_end][nb_context] + public : SC_IN (Tevent_state_t ) *** in_RETIRE_EVENT_STATE ;//[nb_front_end][nb_context] + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::dependency_checking_unit::Dependency_checking_unit * _component_dependency_checking_unit; Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp (revision 104) @@ -110,5 +110,4 @@ ALLOC1_SIGNAL_IN ( in_RETIRE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); ALLOC1_SIGNAL_IN ( in_RETIRE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC1_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"event_state" ,Tevent_state_t ,_param->_size_event_state ); ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register ); @@ -126,4 +125,14 @@ ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register ); } + + // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]); + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ std::string name; @@ -329,6 +338,4 @@ PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_CONTEXT_ID" , dest, "in_RETIRE_"+toString(i)+"_CONTEXT_ID" ); - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_EVENT_STATE" , - dest, "in_RETIRE_"+toString(i)+"_EVENT_STATE" ); PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_WRITE_RD" , dest, "in_RETIRE_"+toString(i)+"_WRITE_RD" ); @@ -356,4 +363,21 @@ dest, "in_RETIRE_"+toString(i)+"_RESTORE_RE_PHY_OLD"); } + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + dest = _name; + +#ifdef POSITION + _component->interface_map (src ,"retire_event_"+toString(i)+"_"+toString(j), + dest,"retire_event_"+toString(i)+"_"+toString(j)); +#endif + PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_VAL" , + dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_VAL" ); + PORT_MAP(_component,src ,"out_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_ACK" , + dest,"out_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_ACK" ); + PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE", + dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE"); + } } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp (revision 104) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Register_translation_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -75,5 +76,4 @@ if (_param->_have_port_context_id) delete [] in_RETIRE_CONTEXT_ID ; - delete [] in_RETIRE_EVENT_STATE ; delete [] in_RETIRE_READ_RA ; delete [] in_RETIRE_NUM_REG_RA_PHY ; @@ -90,5 +90,10 @@ delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; delete [] in_RETIRE_NUM_REG_RE_PHY_NEW; + + DELETE2_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL(out_RETIRE_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state); } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp (revision 104) @@ -115,5 +115,4 @@ ALLOC1_SC_SIGNAL( in_RETIRE_STORE_QUEUE_PTR_WRITE," in_RETIRE_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_LOAD_QUEUE_PTR_WRITE ," in_RETIRE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_retire); - ALLOC1_SC_SIGNAL( in_RETIRE_EVENT_STATE ," in_RETIRE_EVENT_STATE ",Tevent_state_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_READ_RA ," in_RETIRE_READ_RA ",Tcontrol_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ," in_RETIRE_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_retire); @@ -130,4 +129,7 @@ ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD ," in_RETIRE_NUM_REG_RE_PHY_OLD ",Tspecial_address_t,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW ," in_RETIRE_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_inst_retire); + ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_VAL ," in_RETIRE_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_EVENT_ACK ,"out_RETIRE_EVENT_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_STATE ," in_RETIRE_EVENT_STATE ",Tevent_state_t ,_param->_nb_front_end,_param->_nb_context[it1]); ALLOC2_SC_SIGNAL( in_SPR_READ_SR ," in_SPR_READ_SR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]); @@ -220,5 +222,4 @@ if (_param->_have_port_load_queue_ptr) INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire); - INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_EVENT_STATE ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_READ_RA ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire); @@ -235,4 +236,8 @@ INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_retire); + + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit,out_RETIRE_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1]); INSTANCE2_SC_SIGNAL(_Rename_unit,in_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1]); @@ -352,5 +357,4 @@ DELETE1_SC_SIGNAL( in_RETIRE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire); DELETE1_SC_SIGNAL( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire); - DELETE1_SC_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_inst_retire); DELETE1_SC_SIGNAL( in_RETIRE_READ_RA ,_param->_nb_inst_retire); DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire); @@ -368,4 +372,8 @@ DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_retire); + DELETE2_SC_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL(in_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1]); } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h (revision 104) @@ -140,5 +140,4 @@ public : SC_IN (Tlsq_ptr_t ) ** in_RETIRE_STORE_QUEUE_PTR_WRITE;//[nb_inst_retire] public : SC_IN (Tlsq_ptr_t ) ** in_RETIRE_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_retire] - public : SC_IN (Tevent_state_t ) ** in_RETIRE_EVENT_STATE ;//[nb_inst_retire] public : SC_IN (Tcontrol_t ) ** in_RETIRE_READ_RA ;//[nb_inst_retire] public : SC_IN (Tgeneral_address_t) ** in_RETIRE_NUM_REG_RA_PHY ;//[nb_inst_retire] @@ -156,4 +155,9 @@ public : SC_IN (Tspecial_address_t) ** in_RETIRE_NUM_REG_RE_PHY_NEW ;//[nb_inst_retire] + // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_RETIRE_EVENT_VAL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_ACK ;//[nb_front_end][nb_context] + public : SC_IN (Tevent_state_t ) *** in_RETIRE_EVENT_STATE ;//[nb_front_end][nb_context] + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ public : SC_IN (Tspr_t ) *** in_SPR_READ_SR ;//[nb_front_end][nb_context] Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp (revision 104) @@ -139,5 +139,4 @@ ALLOC1_SIGNAL_IN ( in_RETIRE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); ALLOC1_SIGNAL_IN ( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); - ALLOC1_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"event_state" ,Tevent_state_t ,_param->_size_event_state ); ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register ); @@ -154,4 +153,13 @@ ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ); ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ); + } + + // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_VALACK_OUT(out_RETIRE_EVENT_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]); } @@ -537,6 +545,4 @@ PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_CONTEXT_ID" , dest, "in_RETIRE_"+toString(i)+"_CONTEXT_ID" ); - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_EVENT_STATE" , - dest, "in_RETIRE_"+toString(i)+"_EVENT_STATE" ); PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_READ_RA" , dest, "in_RETIRE_"+toString(i)+"_READ_RA" ); @@ -578,4 +584,21 @@ COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_ACK",dest, "in_RETIRE_"+toString(i)+"_REGISTER_TRANSLATION_ACK"); } + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + dest = _name; + +#ifdef POSITION + _component->interface_map (src ,"retire_event_"+toString(i)+"_"+toString(j), + dest,"retire_event_"+toString(i)+"_"+toString(j)); +#endif + PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_VAL" , + dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_VAL" ); + PORT_MAP(_component,src ,"out_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_ACK" , + dest,"out_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_ACK" ); + PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE", + dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE"); + } } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp (revision 104) @@ -97,5 +97,4 @@ DELETE1_SIGNAL( in_RETIRE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire,_param->_size_store_queue_ptr ); DELETE1_SIGNAL( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire,_param->_size_load_queue_ptr ); - DELETE1_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_inst_retire,_param->_size_event_state ); DELETE1_SIGNAL( in_RETIRE_READ_RA ,_param->_nb_inst_retire,1 ); DELETE1_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire,_param->_size_general_register ); @@ -112,4 +111,8 @@ DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_retire,_param->_size_special_register ); DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_retire,_param->_size_special_register ); + + DELETE2_SIGNAL( in_RETIRE_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL(out_RETIRE_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state); DELETE2_SIGNAL(in_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h (revision 104) @@ -81,5 +81,4 @@ // SPR public : bool *** _implement_group ;//[nb_front_end][nb_context][NB_GROUP] - public : std::vector*_link_front_end_with_rename_unit ;//[nb_rename_unit] Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 104) @@ -378,8 +378,8 @@ // ~~~~~[ Interface : "rename_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - std::vector::iterator it = _param->_link_front_end_with_rename_unit[i].begin(); - uint32_t x = 0; - for (uint32_t j=0; j<_param->_nb_front_end; j++) - { + { + std::vector::iterator it = _param->_link_front_end_with_rename_unit[i].begin(); + uint32_t x = 0; + for (uint32_t j=0; j<_param->_nb_front_end; j++) if (i == *it) { @@ -459,6 +459,6 @@ it++; } - } - + } + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) @@ -551,4 +551,5 @@ } + // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) { @@ -581,7 +582,4 @@ COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RE_PHY_NEW", dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RE_PHY_NEW"); - COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_EVENT_STATE" , - dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_EVENT_STATE" ); - if (_param->_have_port_context_id) COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_CONTEXT_ID" , @@ -616,50 +614,57 @@ COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RE_LOG" , dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RE_LOG" ); - -// dest = _name+"_glue"; - -// #ifdef POSITION -// _component->interface_map (src ,"retire_"+toString(j), -// dest,"retire_"+toString(i)+"_"+toString(j)); -// #endif - -// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_VAL" , -// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_VAL" ); -// COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(j)+ "_ACK" , -// dest, "in_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_ACK" ); -// if (_param->_have_port_front_end_id) -// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_FRONT_END_ID" , -// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_FRONT_END_ID" ); -// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_WRITE_RD" , -// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_WRITE_RD" ); -// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RD_PHY_OLD", -// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RD_PHY_OLD"); -// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RD_PHY_NEW", -// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RD_PHY_NEW"); -// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_WRITE_RE" , -// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_WRITE_RE" ); -// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RE_PHY_OLD", -// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RE_PHY_OLD"); -// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RE_PHY_NEW", -// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RE_PHY_NEW"); -// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_EVENT_STATE" , -// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_EVENT_STATE" ); } // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - for (uint32_t i=0; i<_param->_nb_front_end; i++) - for (uint32_t j=0; j<_param->_nb_context[i]; j++) - { - dest = _name+"_glue"; - -#ifdef POSITION - _component->interface_map (src ,"spr_read_"+toString(i)+"_"+toString(j), - dest,"spr_" +toString(i)+"_"+toString(j)); -#endif - - COMPONENT_MAP(_component,src , "in_SPR_READ_"+toString(i)+"_"+toString(j)+ "_SR", - dest,"out_SPR_" +toString(i)+"_"+toString(j)+"_RENAME_UNIT_SR"); - } - } + { + std::vector::iterator it = _param->_link_front_end_with_rename_unit[i].begin(); + uint32_t x = 0; + for (uint32_t j=0; j<_param->_nb_front_end; j++) + if (i == (*it)) + { + for (uint32_t k=0; k<_param->_nb_context[i]; k++) + { + dest = _name+"_commit_unit"; + +#ifdef POSITION + _component->interface_map (src ,"retire_event_"+toString(x)+"_"+toString(k), + dest,"retire_event_"+toString(j)+"_"+toString(k)); +#endif + COMPONENT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(x)+"_"+toString(k)+"_VAL", + dest,"out_RETIRE_EVENT_"+toString(j)+"_"+toString(k)+"_VAL"); + COMPONENT_MAP(_component,src ,"out_RETIRE_EVENT_"+toString(x)+"_"+toString(k)+"_ACK", + dest, "in_RETIRE_EVENT_"+toString(j)+"_"+toString(k)+"_ACK"); + COMPONENT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(x)+"_"+toString(k)+"_STATE", + dest,"out_RETIRE_EVENT_"+toString(j)+"_"+toString(k)+"_STATE"); + x++; + ++it; + } + } + } + + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + std::vector::iterator it = _param->_link_front_end_with_rename_unit[i].begin(); + uint32_t x = 0; + for (uint32_t j=0; j<_param->_nb_front_end; j++) + if (i == *it) + { + for (uint32_t k=0; k<_param->_nb_context[j]; k++) + { + dest = _name+"_glue"; + +#ifdef POSITION + _component->interface_map (src ,"spr_read_"+toString(x)+"_"+toString(k), + dest,"spr_" +toString(j)+"_"+toString(k)); +#endif + + COMPONENT_MAP(_component,src , "in_SPR_READ_"+toString(x)+"_"+toString(k)+ "_SR", + dest,"out_SPR_" +toString(j)+"_"+toString(k)+"_RENAME_UNIT_SR"); + } + x++; + ++it; + } + } + } // =================================================================== @@ -821,4 +826,10 @@ } + // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_RETIRE_VAL - rename_unit.out_RETIRE_VAL + // in_RETIRE_ACK - rename_unit. in_RETIRE_ACK + // out_RETIRE_EVENT_STATE - rename_unit.out_RETIRE_EVENT_STATE + + // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ for (uint32_t i=0; i<_param->_nb_inst_commit; i++) @@ -1043,5 +1054,4 @@ dest, "in_SPR_COMMIT_"+toString(i)+"_"+toString(j)+"_SR_OV" ); } - } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h (revision 104) @@ -571,6 +571,4 @@ # define SPR_MACHI 2 // MAC High - - // SR RENAME # define NB_SPR_LOGIC 2 @@ -596,7 +594,7 @@ # define EVENT_STATE_WAITEND 2 // Wait end of manage event (restaure a good context) # define EVENT_STATE_END 3 // CPU can continue - -# define SIZE_EVENT_TYPE 3 - + +# define SIZE_EVENT_TYPE 3 + # define EVENT_TYPE_NONE 0 // no event # define EVENT_TYPE_MISS_SPECULATION 1 // miss of speculation (load or branch miss speculation) @@ -1071,4 +1069,32 @@ }; +// template<> inline std::string toString(const morpheo::behavioural::event_state_t& x) +// { +// switch (x) +// { +// case morpheo::behavioural::EVENT_STATE_NO_EVENT : return "EVENT_STATE_NO_EVENT"; +// case morpheo::behavioural::EVENT_STATE_EVENT : return "EVENT_STATE_EVENT" ; +// case morpheo::behavioural::EVENT_STATE_WAITEND : return "EVENT_STATE_WAITEND" ; +// case morpheo::behavioural::EVENT_STATE_END : return "EVENT_STATE_END" ; +// default : return ""; +// } +// }; + +// template<> inline std::string toString(const morpheo::behavioural::event_type_t& x) +// { +// switch (x) +// { +// case morpheo::behavioural::EVENT_TYPE_NONE : return "EVENT_TYPE_NONE" ; +// case morpheo::behavioural::EVENT_TYPE_MISS_SPECULATION : return "EVENT_TYPE_MISS_SPECULATION" ; +// case morpheo::behavioural::EVENT_TYPE_EXCEPTION : return "EVENT_TYPE_EXCEPTION" ; +// case morpheo::behavioural::EVENT_TYPE_BRANCH_NO_ACCURATE : return "EVENT_TYPE_BRANCH_NO_ACCURATE"; +// case morpheo::behavioural::EVENT_TYPE_SPR_ACCESS : return "EVENT_TYPE_SPR_ACCESS" ; +// case morpheo::behavioural::EVENT_TYPE_MSYNC : return "EVENT_TYPE_MSYNC" ; +// case morpheo::behavioural::EVENT_TYPE_PSYNC : return "EVENT_TYPE_PSYNC" ; +// case morpheo::behavioural::EVENT_TYPE_CSYNC : return "EVENT_TYPE_CSYNC" ; +// default : return ""; +// } +// }; + }; // end namespace morpheo Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 104) @@ -10,8 +10,8 @@ #define MORPHEO_MAJOR_VERSION 0 #define MORPHEO_MINOR_VERSION 2 -#define MORPHEO_REVISION "103" +#define MORPHEO_REVISION "104" #define MORPHEO_CODENAME "Castor" -#define MORPHEO_DATE_DAY "16" +#define MORPHEO_DATE_DAY "21" #define MORPHEO_DATE_MONTH "01" #define MORPHEO_DATE_YEAR "2009" Index: /trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg (revision 104) @@ -1,11 +1,11 @@ - + - - + + - + @@ -16,5 +16,5 @@ - + @@ -33,16 +33,16 @@ - + - - + + - - + + @@ -74,5 +74,5 @@ - + @@ -115,13 +115,13 @@ - + - + - + @@ -132,5 +132,5 @@ - + Index: /trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 103) +++ /trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 104) @@ -8,7 +8,7 @@ - + - + @@ -25,5 +25,5 @@ - +