Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 101)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 105)
@@ -65,5 +65,5 @@
                   break;
                 }
-              case CONTEXT_STATE_KO_MISS_WAITEND :
+              case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND :
                 {
                   // Wait end of all instruction
@@ -71,5 +71,13 @@
                     
 //                  state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
-                    state = CONTEXT_STATE_KO_MISS_ADDR;
+                    state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_LOAD_WAITEND :
+                {
+                  // Wait end of all instruction
+                  if (inst_all == 0)
+                    state = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
+
                   break;
                 }
@@ -79,5 +87,10 @@
                   break;
                 }
-              case CONTEXT_STATE_KO_MISS_ADDR    :
+              case CONTEXT_STATE_KO_MISS_BRANCH_ADDR    :
+                {
+                  // nothing, wait the update of internal register (pc)
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_LOAD_ADDR    :
                 {
                   // nothing, wait the update of internal register (pc)
@@ -198,5 +211,5 @@
 
               // priority : miss > excep > spr/sync
-              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
+              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
               uint8_t    priority1  = 2; // miss
 
@@ -212,6 +225,6 @@
                 {
                   Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
-//                reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_ADDR;
-                  reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
+//                reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
+                  reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; //@@@ TODO : make MISS fast (miss decod)
                   reg_EVENT_ADDRESS          [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC  [i])+1; // address delay slot
                   reg_EVENT_ADDRESS_EPCR     [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]);   // address_next
@@ -249,5 +262,5 @@
               
               // miss > excep > spr/sync
-              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
               uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?1:0;
 
@@ -258,5 +271,5 @@
               bool       is_valid   = ((state == CONTEXT_STATE_OK) or
                                        (depth1< depth0) or
-                                       ((depth1==depth0) and (priority1>priority0)));
+                                       ((depth1==depth0) and (priority1>=priority0)));
 
               if (is_valid)
@@ -325,6 +338,7 @@
                       }               
                     case EVENT_TYPE_NONE               :
-                    case EVENT_TYPE_MISS_SPECULATION   :
-                    case EVENT_TYPE_BRANCH_NO_ACCURATE :
+                    case EVENT_TYPE_BRANCH_MISS_SPECULATION   :
+                    case EVENT_TYPE_LOAD_MISS_SPECULATION   :
+//                     case EVENT_TYPE_BRANCH_NO_ACCURATE :
                     default :
                       {
@@ -359,6 +373,6 @@
             Tdepth_t   depth_max  = _param->_array_size_depth [context];
             
-//             Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
-//             Tdepth_t   depth1     = (depth    >=depth_min)?(depth    -depth_min):((depth    +depth_max-depth_min));
+//          Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
+//          Tdepth_t   depth1     = (depth    >=depth_min)?(depth    -depth_min):((depth    +depth_max-depth_min));
             Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
             Tdepth_t   depth1     = (depth    >=depth_min)?(depth    ):((depth    +depth_max));
@@ -368,6 +382,6 @@
             
             // miss > excep > spr/sync
-            uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
-            uint8_t    priority1  = 1; // exception
+            uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+            uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION)
 
             // is_valid = can modify local information
@@ -377,5 +391,5 @@
             bool       is_valid   = ((state == CONTEXT_STATE_OK) or
                                      (depth1< depth0) or
-                                     ((depth1==depth0) and (priority1>priority0)));
+                                     ((depth1==depth0) and (priority1>=priority0)));
 
             if (is_valid)
@@ -386,12 +400,13 @@
                 switch (type)
                   {
-                  case EVENT_TYPE_EXCEPTION          : {state_next = CONTEXT_STATE_KO_EXCEP; break;}
-                  case EVENT_TYPE_SPR_ACCESS         :
-                  case EVENT_TYPE_MSYNC              :
-                  case EVENT_TYPE_PSYNC              :
-                  case EVENT_TYPE_CSYNC              :
-                  case EVENT_TYPE_NONE               :
-                  case EVENT_TYPE_MISS_SPECULATION   :
-                  case EVENT_TYPE_BRANCH_NO_ACCURATE :
+                  case EVENT_TYPE_EXCEPTION               : {state_next = CONTEXT_STATE_KO_EXCEP;             break;}
+                  case EVENT_TYPE_LOAD_MISS_SPECULATION   : {state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; break;}
+                  case EVENT_TYPE_BRANCH_MISS_SPECULATION :
+                  case EVENT_TYPE_SPR_ACCESS              :
+                  case EVENT_TYPE_MSYNC                   :
+                  case EVENT_TYPE_PSYNC                   :
+                  case EVENT_TYPE_CSYNC                   :
+                  case EVENT_TYPE_NONE                    :
+//                case EVENT_TYPE_BRANCH_NO_ACCURATE      :
                   default :
                     {
@@ -402,9 +417,9 @@
                 reg_EVENT_ADDRESS          [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS          );
                 reg_EVENT_ADDRESS_EPCR     [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR     ); 
-                reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
+                reg_EVENT_ADDRESS_EPCR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR_VAL );
                 reg_EVENT_ADDRESS_EEAR     [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR     ); 
                 reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
                 reg_EVENT_IS_DELAY_SLOT    [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT    );
-              //reg_EVENT_IS_DS_TAKE       [context] = 0;
+                reg_EVENT_IS_DS_TAKE       [context] = 0;
                 reg_EVENT_DEPTH            [context] = depth;
               }
@@ -435,5 +450,5 @@
                   
 //                   // miss > excep > spr/sync
-//                   uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+//                   uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
 //                   uint8_t    priority1  = 2; // miss
                   
@@ -444,5 +459,5 @@
 //                   bool       is_valid   = ((state == CONTEXT_STATE_OK) or
 //                                            (depth1< depth0) or
-//                                            ((depth1==depth0) and (priority1>priority0)));
+//                                            ((depth1==depth0) and (priority1>=priority0)));
                   
 //                   if (is_valid)
@@ -480,9 +495,10 @@
                     break;
                   }
-                case CONTEXT_STATE_KO_MISS_ADDR  :
+                case CONTEXT_STATE_KO_MISS_BRANCH_ADDR:
 //                   {
 //                     reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
 //                     break;
 //                   }
+                case CONTEXT_STATE_KO_MISS_LOAD_ADDR  :
                 case CONTEXT_STATE_KO_PSYNC_ADDR :
                 case CONTEXT_STATE_KO_CSYNC_ADDR :
