Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp	(revision 102)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp	(revision 105)
@@ -73,4 +73,5 @@
   ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT     ," in_COMMIT_EVENT_IS_DELAY_SLOT     ",Tcontrol_t   );
   ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS           ," in_COMMIT_EVENT_ADDRESS           ",Taddress_t   );
+  ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL  ," in_COMMIT_EVENT_ADDRESS_EPCR_VAL  ",Tcontrol_t   );
   ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR      ," in_COMMIT_EVENT_ADDRESS_EPCR      ",Taddress_t   );
   ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL  ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL  ",Tcontrol_t   );
@@ -155,4 +156,5 @@
   INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT     );
   INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS           );
+  INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR_VAL  );
   INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR      );
   INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL  );
@@ -214,5 +216,5 @@
 
   const bool test1  = true;
-  const bool test2  = true;
+  const bool test2  = false;
   const bool test3  = true;
   const bool test4  = true;
@@ -925,4 +927,5 @@
 	  in_COMMIT_EVENT_ADDRESS          ->write(0xa00);
 	  in_COMMIT_EVENT_ADDRESS_EPCR     ->write(0xb00);
+	  in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(0);
 	  in_COMMIT_EVENT_ADDRESS_EEAR     ->write(0xc00);
 	  in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
@@ -1019,4 +1022,5 @@
 	  in_COMMIT_EVENT_ADDRESS          ->write(0xd00);
 	  in_COMMIT_EVENT_ADDRESS_EPCR     ->write(0xe00);
+	  in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(0);
 	  in_COMMIT_EVENT_ADDRESS_EEAR     ->write(0xf00);
 	  in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
@@ -1113,4 +1117,5 @@
 	  in_COMMIT_EVENT_ADDRESS          ->write(0xa00);
 	  in_COMMIT_EVENT_ADDRESS_EPCR     ->write(0xb00);
+	  in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(1);
 	  in_COMMIT_EVENT_ADDRESS_EEAR     ->write(0xc00);
 	  in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
@@ -1207,4 +1212,5 @@
 	  in_COMMIT_EVENT_ADDRESS          ->write(0xd00);
 	  in_COMMIT_EVENT_ADDRESS_EPCR     ->write(0xe00);
+	  in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(1);
 	  in_COMMIT_EVENT_ADDRESS_EEAR     ->write(0xf00);
 	  in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
@@ -1325,4 +1331,5 @@
   DELETE_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT     );
   DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS           );
+  DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL  );
   DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR      );
   DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL  );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h	(revision 102)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h	(revision 105)
@@ -91,4 +91,5 @@
   public    : SC_IN (Tcontrol_t         )   *  in_COMMIT_EVENT_IS_DELAY_SLOT         ;
   public    : SC_IN (Taddress_t         )   *  in_COMMIT_EVENT_ADDRESS               ;
+  public    : SC_IN (Tcontrol_t         )   *  in_COMMIT_EVENT_ADDRESS_EPCR_VAL      ;
   public    : SC_IN (Taddress_t         )   *  in_COMMIT_EVENT_ADDRESS_EPCR          ;
   public    : SC_IN (Tcontrol_t         )   *  in_COMMIT_EVENT_ADDRESS_EEAR_VAL      ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h	(revision 102)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h	(revision 105)
@@ -25,22 +25,24 @@
   typedef enum
     {
-      CONTEXT_STATE_OK              , // none event
-      CONTEXT_STATE_KO_EXCEP        , // wait end of event (exception)
-      CONTEXT_STATE_KO_EXCEP_ADDR   , // update address manager
-      CONTEXT_STATE_KO_EXCEP_SPR    , // update spr (epc, esr, sr[DSX])
-      CONTEXT_STATE_KO_MISS_ADDR    , // update address manager
-      CONTEXT_STATE_KO_MISS_WAITEND , // wait end of event (miss (branch, load))
-//    CONTEXT_STATE_KO_MSYNC        , // wait completion of all memory operation
-//    CONTEXT_STATE_KO_MSYNC_ISSUE  , // issue msync operation
-      CONTEXT_STATE_KO_MSYNC_EXEC   , // wait completion of     msync  operation
-//    CONTEXT_STATE_KO_PSYNC        , // wait completion of all        operation and after flush pipeline
-      CONTEXT_STATE_KO_PSYNC_FLUSH  , // wait completion of all 
-      CONTEXT_STATE_KO_PSYNC_ADDR   , // wait completion of all 
-//    CONTEXT_STATE_KO_CSYNC        , // wait completion of all        operation and after flush pipeline and flush ALL units (MMU, cache ...)
-      CONTEXT_STATE_KO_CSYNC_FLUSH  ,
-      CONTEXT_STATE_KO_CSYNC_ADDR   ,
-//    CONTEXT_STATE_KO_SPR          , // wait completion of all        operation
-//    CONTEXT_STATE_KO_SPR_ISSUE    , // issue spr's access
-      CONTEXT_STATE_KO_SPR_EXEC       // wait completion of all        operation (spr access)
+      CONTEXT_STATE_OK                    , // none event
+      CONTEXT_STATE_KO_EXCEP              , // wait end of event (exception)
+      CONTEXT_STATE_KO_EXCEP_ADDR         , // update address manager
+      CONTEXT_STATE_KO_EXCEP_SPR          , // update spr (epc, esr, sr[DSX])
+      CONTEXT_STATE_KO_MISS_BRANCH_ADDR   , // update address manager
+      CONTEXT_STATE_KO_MISS_BRANCH_WAITEND, // wait end of event (miss branch)
+      CONTEXT_STATE_KO_MISS_LOAD_ADDR     , // update address manager
+      CONTEXT_STATE_KO_MISS_LOAD_WAITEND  , // wait end of event (miss load))
+//    CONTEXT_STATE_KO_MSYNC              , // wait completion of all memory operation
+//    CONTEXT_STATE_KO_MSYNC_ISSUE        , // issue msync operation
+      CONTEXT_STATE_KO_MSYNC_EXEC         , // wait completion of     msync  operation
+//    CONTEXT_STATE_KO_PSYNC              , // wait completion of all        operation and after flush pipeline
+      CONTEXT_STATE_KO_PSYNC_FLUSH        , // wait completion of all 
+      CONTEXT_STATE_KO_PSYNC_ADDR         , // wait completion of all 
+//    CONTEXT_STATE_KO_CSYNC              , // wait completion of all        operation and after flush pipeline and flush ALL units (MMU, cache ...)
+      CONTEXT_STATE_KO_CSYNC_FLUSH        ,
+      CONTEXT_STATE_KO_CSYNC_ADDR         ,
+//    CONTEXT_STATE_KO_SPR                , // wait completion of all        operation
+//    CONTEXT_STATE_KO_SPR_ISSUE          , // issue spr's access
+      CONTEXT_STATE_KO_SPR_EXEC             // wait completion of all        operation (spr access)
     } context_state_t;
 
@@ -56,22 +58,24 @@
     switch (x)
       {
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_OK              : return "context_state_ok"             ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP        : return "context_state_ko_excep"       ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_ADDR   : return "context_state_ko_excep_addr"  ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_SPR    : return "context_state_ko_excep_spr"   ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_ADDR    : return "context_state_ko_miss_addr"   ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_WAITEND : return "context_state_ko_miss_waitend"; break;
-//       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC        : return "context_state_ko_msync"       ; break;
-//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE  : return "context_state_ko_msync_issue" ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_EXEC   : return "context_state_ko_msync_exec"  ; break;
-//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC        : return "context_state_ko_psync"       ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_FLUSH  : return "context_state_ko_psync_flush" ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_ADDR   : return "context_state_ko_psync_addr"  ; break;
-//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC        : return "context_state_ko_csync"       ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_FLUSH  : return "context_state_ko_csync_flush" ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_ADDR   : return "context_state_ko_csync_addr"  ; break;
-//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR          : return "context_state_ko_spr"         ; break;
-//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_ISSUE    : return "context_state_ko_spr_issue"   ; break;
-      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_EXEC     : return "context_state_ko_spr_exec"    ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_OK                     : return "context_state_ok"                    ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP               : return "context_state_ko_excep"              ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_ADDR          : return "context_state_ko_excep_addr"         ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_SPR           : return "context_state_ko_excep_spr"          ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_ADDR    : return "context_state_ko_miss_branch_addr"   ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : return "context_state_ko_miss_branch_waitend"; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_ADDR      : return "context_state_ko_miss_load_addr"     ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_WAITEND   : return "context_state_ko_miss_load_waitend"  ; break;
+//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC               : return "context_state_ko_msync"              ; break;
+//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE         : return "context_state_ko_msync_issue"        ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_EXEC          : return "context_state_ko_msync_exec"         ; break;
+//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC               : return "context_state_ko_psync"              ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_FLUSH         : return "context_state_ko_psync_flush"        ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_ADDR          : return "context_state_ko_psync_addr"         ; break;
+//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC               : return "context_state_ko_csync"              ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_FLUSH         : return "context_state_ko_csync_flush"        ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_ADDR          : return "context_state_ko_csync_addr"         ; break;
+//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR                 : return "context_state_ko_spr"                ; break;
+//    case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_ISSUE           : return "context_state_ko_spr_issue"          ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_EXEC            : return "context_state_ko_spr_exec"           ; break;
       default    : return ""      ; break;
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp	(revision 102)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp	(revision 105)
@@ -95,4 +95,5 @@
       ALLOC_SIGNAL_IN  ( in_COMMIT_EVENT_IS_DELAY_SLOT         ,"is_delay_slot"   ,Tcontrol_t         ,1);
       ALLOC_SIGNAL_IN  ( in_COMMIT_EVENT_ADDRESS               ,"address"         ,Taddress_t         ,_param->_size_instruction_address);
+      ALLOC_SIGNAL_IN  ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL      ,"address_epcr_val",Tcontrol_t         ,1);
       ALLOC_SIGNAL_IN  ( in_COMMIT_EVENT_ADDRESS_EPCR          ,"address_epcr"    ,Taddress_t         ,_param->_size_instruction_address);
       ALLOC_SIGNAL_IN  ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL      ,"address_eear_val",Tcontrol_t         ,1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp	(revision 102)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp	(revision 105)
@@ -53,4 +53,5 @@
         DELETE_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT         ,1);
         DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS               ,_param->_size_instruction_address);
+	DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL      ,_param->_size_instruction_address);
         DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR          ,_param->_size_instruction_address);
 	DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL      ,_param->_size_instruction_address);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp	(revision 102)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp	(revision 105)
@@ -31,7 +31,8 @@
 	context_state_t state = reg_STATE [i];
 
-        Tcontrol_t val              = ((state == CONTEXT_STATE_KO_EXCEP_ADDR) or
-                                       (state == CONTEXT_STATE_KO_MISS_ADDR ) or
-                                       (state == CONTEXT_STATE_KO_PSYNC_ADDR) or 
+        Tcontrol_t val              = ((state == CONTEXT_STATE_KO_EXCEP_ADDR      ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR  ) or
+                                       (state == CONTEXT_STATE_KO_PSYNC_ADDR      ) or 
                                        (state == CONTEXT_STATE_KO_CSYNC_ADDR));
         
@@ -40,6 +41,6 @@
         Taddress_t    address          = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0);
         Taddress_t    address_next     = reg_EVENT_ADDRESS_EPCR [i];
-        Tcontrol_t    address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);
-        Tcontrol_t    is_ds_take       = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]);
+        Tcontrol_t    address_next_val = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);
+        Tcontrol_t    is_ds_take       = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]);
 	// excep : address exception
 	// miss  : address delay_slot, and address dest
@@ -51,9 +52,10 @@
         switch (state)
           {
-          case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION         ); break;
-          case CONTEXT_STATE_KO_MISS_ADDR  : (type = EVENT_TYPE_MISS_SPECULATION  ); break;
-          case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC             ); break; 
-          case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC             ); break;
-          default                          : (type = EVENT_TYPE_NONE              ); break;
+          case CONTEXT_STATE_KO_EXCEP_ADDR      : (type = EVENT_TYPE_EXCEPTION              ); break;
+          case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: (type = EVENT_TYPE_BRANCH_MISS_SPECULATION); break;
+          case CONTEXT_STATE_KO_MISS_LOAD_ADDR  : (type = EVENT_TYPE_LOAD_MISS_SPECULATION  ); break;
+          case CONTEXT_STATE_KO_PSYNC_ADDR      : (type = EVENT_TYPE_PSYNC                  ); break; 
+          case CONTEXT_STATE_KO_CSYNC_ADDR      : (type = EVENT_TYPE_CSYNC                  ); break;
+          default                               : (type = EVENT_TYPE_NONE                   ); break;
           }
 //      (type = EVENT_TYPE_SPR_ACCESS        );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 102)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 105)
@@ -65,5 +65,5 @@
                   break;
                 }
-              case CONTEXT_STATE_KO_MISS_WAITEND :
+              case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND :
                 {
                   // Wait end of all instruction
@@ -71,5 +71,13 @@
                     
 //                  state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
-                    state = CONTEXT_STATE_KO_MISS_ADDR;
+                    state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_LOAD_WAITEND :
+                {
+                  // Wait end of all instruction
+                  if (inst_all == 0)
+                    state = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
+
                   break;
                 }
@@ -79,5 +87,10 @@
                   break;
                 }
-              case CONTEXT_STATE_KO_MISS_ADDR    :
+              case CONTEXT_STATE_KO_MISS_BRANCH_ADDR    :
+                {
+                  // nothing, wait the update of internal register (pc)
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_LOAD_ADDR    :
                 {
                   // nothing, wait the update of internal register (pc)
@@ -198,5 +211,5 @@
 
               // priority : miss > excep > spr/sync
-              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
+              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
               uint8_t    priority1  = 2; // miss
 
@@ -212,6 +225,6 @@
                 {
                   Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
-//                reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_ADDR;
-                  reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
+//                reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
+                  reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; //@@@ TODO : make MISS fast (miss decod)
                   reg_EVENT_ADDRESS          [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC  [i])+1; // address delay slot
                   reg_EVENT_ADDRESS_EPCR     [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]);   // address_next
@@ -249,5 +262,5 @@
               
               // miss > excep > spr/sync
-              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
               uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?1:0;
 
@@ -258,5 +271,5 @@
               bool       is_valid   = ((state == CONTEXT_STATE_OK) or
                                        (depth1< depth0) or
-                                       ((depth1==depth0) and (priority1>priority0)));
+                                       ((depth1==depth0) and (priority1>=priority0)));
 
               if (is_valid)
@@ -325,6 +338,7 @@
                       }               
                     case EVENT_TYPE_NONE               :
-                    case EVENT_TYPE_MISS_SPECULATION   :
-                    case EVENT_TYPE_BRANCH_NO_ACCURATE :
+                    case EVENT_TYPE_BRANCH_MISS_SPECULATION   :
+                    case EVENT_TYPE_LOAD_MISS_SPECULATION   :
+//                     case EVENT_TYPE_BRANCH_NO_ACCURATE :
                     default :
                       {
@@ -359,6 +373,6 @@
             Tdepth_t   depth_max  = _param->_array_size_depth [context];
             
-//             Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
-//             Tdepth_t   depth1     = (depth    >=depth_min)?(depth    -depth_min):((depth    +depth_max-depth_min));
+//          Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
+//          Tdepth_t   depth1     = (depth    >=depth_min)?(depth    -depth_min):((depth    +depth_max-depth_min));
             Tdepth_t   depth0     = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
             Tdepth_t   depth1     = (depth    >=depth_min)?(depth    ):((depth    +depth_max));
@@ -368,6 +382,6 @@
             
             // miss > excep > spr/sync
-            uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
-            uint8_t    priority1  = 1; // exception
+            uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+            uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION)
 
             // is_valid = can modify local information
@@ -377,5 +391,5 @@
             bool       is_valid   = ((state == CONTEXT_STATE_OK) or
                                      (depth1< depth0) or
-                                     ((depth1==depth0) and (priority1>priority0)));
+                                     ((depth1==depth0) and (priority1>=priority0)));
 
             if (is_valid)
@@ -386,12 +400,13 @@
                 switch (type)
                   {
-                  case EVENT_TYPE_EXCEPTION          : {state_next = CONTEXT_STATE_KO_EXCEP; break;}
-                  case EVENT_TYPE_SPR_ACCESS         :
-                  case EVENT_TYPE_MSYNC              :
-                  case EVENT_TYPE_PSYNC              :
-                  case EVENT_TYPE_CSYNC              :
-                  case EVENT_TYPE_NONE               :
-                  case EVENT_TYPE_MISS_SPECULATION   :
-                  case EVENT_TYPE_BRANCH_NO_ACCURATE :
+                  case EVENT_TYPE_EXCEPTION               : {state_next = CONTEXT_STATE_KO_EXCEP;             break;}
+                  case EVENT_TYPE_LOAD_MISS_SPECULATION   : {state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; break;}
+                  case EVENT_TYPE_BRANCH_MISS_SPECULATION :
+                  case EVENT_TYPE_SPR_ACCESS              :
+                  case EVENT_TYPE_MSYNC                   :
+                  case EVENT_TYPE_PSYNC                   :
+                  case EVENT_TYPE_CSYNC                   :
+                  case EVENT_TYPE_NONE                    :
+//                case EVENT_TYPE_BRANCH_NO_ACCURATE      :
                   default :
                     {
@@ -402,9 +417,9 @@
                 reg_EVENT_ADDRESS          [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS          );
                 reg_EVENT_ADDRESS_EPCR     [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR     ); 
-                reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
+                reg_EVENT_ADDRESS_EPCR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR_VAL );
                 reg_EVENT_ADDRESS_EEAR     [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR     ); 
                 reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
                 reg_EVENT_IS_DELAY_SLOT    [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT    );
-              //reg_EVENT_IS_DS_TAKE       [context] = 0;
+                reg_EVENT_IS_DS_TAKE       [context] = 0;
                 reg_EVENT_DEPTH            [context] = depth;
               }
@@ -435,5 +450,5 @@
                   
 //                   // miss > excep > spr/sync
-//                   uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+//                   uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
 //                   uint8_t    priority1  = 2; // miss
                   
@@ -444,5 +459,5 @@
 //                   bool       is_valid   = ((state == CONTEXT_STATE_OK) or
 //                                            (depth1< depth0) or
-//                                            ((depth1==depth0) and (priority1>priority0)));
+//                                            ((depth1==depth0) and (priority1>=priority0)));
                   
 //                   if (is_valid)
@@ -480,9 +495,10 @@
                     break;
                   }
-                case CONTEXT_STATE_KO_MISS_ADDR  :
+                case CONTEXT_STATE_KO_MISS_BRANCH_ADDR:
 //                   {
 //                     reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
 //                     break;
 //                   }
+                case CONTEXT_STATE_KO_MISS_LOAD_ADDR  :
                 case CONTEXT_STATE_KO_PSYNC_ADDR :
                 case CONTEXT_STATE_KO_CSYNC_ADDR :
