Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 104)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 105)
@@ -51,5 +51,5 @@
               reg_PC_CURRENT_IS_DS      [i][j] = 0;
               reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0;
-//            reg_PC_NEXT               [i][j] = (0x100+4)>>2;
+              reg_PC_NEXT               [i][j] = (0x100+4)>>2;
 	    }
 
@@ -138,5 +138,5 @@
 		  entry->operation               = operation;
 		  entry->is_delay_slot           = PORT_READ(in_INSERT_IS_DELAY_SLOT         [x][y]);
-		  entry->address                 = PORT_READ(in_INSERT_ADDRESS               [x][y]);
+// 		  entry->address                 = PORT_READ(in_INSERT_ADDRESS               [x][y]);
 		  entry->exception               = exception;
 		  entry->exception_use           = PORT_READ(in_INSERT_EXCEPTION_USE         [x][y]);
@@ -162,4 +162,6 @@
 		  entry->num_reg_re_phy_old      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD    [x][y]);
 		  entry->num_reg_re_phy_new      = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW    [x][y]);
+                  entry->no_sequence             = type == TYPE_BRANCH;
+		  entry->address_next            = PORT_READ(in_INSERT_ADDRESS_NEXT          [x][y]);
 
                   // Test if exception :
@@ -295,5 +297,5 @@
                       case ROB_MISS_WAIT_END   : {state = ROB_END_KO_SPECULATIVE; break;}
                         // Store OK, Load and other instruction
-                      case ROB_OTHER_WAIT_END  : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_MISS:ROB_END_OK_SPECULATIVE); break;}
+                      case ROB_OTHER_WAIT_END  : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_LOAD_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE); break;}
                       default :
                         {
@@ -304,9 +306,13 @@
 
 		    // update Re Order Buffer
-		    entry->state       = state;
-		    entry->exception   = exception;
-		    entry->flags       = PORT_READ(in_COMMIT_FLAGS       [x]);
-		    entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);
-		    entry->data_commit = PORT_READ(in_COMMIT_ADDRESS     [x]);
+		    entry->state        = state;
+		    entry->exception    = exception;
+		    entry->flags        = PORT_READ(in_COMMIT_FLAGS       [x]);
+		    entry->no_sequence  = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);
+                    // jalr, jr : address_dest is in register
+                    if ((entry->type      == TYPE_BRANCH) and
+                        (entry->operation == OPERATION_BRANCH_L_JALR) and
+                        (entry->read_rb))
+		    entry->address_next = PORT_READ(in_COMMIT_ADDRESS     [x]);
 		  }
 	      }
@@ -345,10 +351,24 @@
 	      Ttype_t    type         = entry->type        ;
 
-              if (state == ROB_END_BRANCH_MISS)
+              if ((state == ROB_END_OK         ) or // LOAD_MISS
+// 		  (state == ROB_END_KO         ) or 
+		  (state == ROB_END_BRANCH_MISS)//  or 
+// 		  (state == ROB_END_LOAD_MISS  ) or 
+// 		  (state == ROB_END_MISS       ) or 
+// 		  (state == ROB_END_EXCEPTION  )
+		  )
+                {
+//                reg_PC_PREVIOUS           [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id];
+                  reg_PC_CURRENT            [front_end_id][context_id] = reg_PC_NEXT    [front_end_id][context_id];
+                  reg_PC_CURRENT_IS_DS      [front_end_id][context_id] = entry->type == TYPE_BRANCH;
+                  reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence;
+                  reg_PC_NEXT               [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1);
+                }
+
+              if ((state == ROB_END_BRANCH_MISS) or
+                  (state == ROB_END_LOAD_MISS))
                 {
                   reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT;
                   reg_EVENT_FLUSH [front_end_id][context_id] = true;
-
-                  // TODO Compute address !!!!!!!!!!!
                 }
 	      
@@ -412,7 +432,33 @@
 	// =====[ UPDATE ]====================================================
 	// ===================================================================
-        {
-          // Not yet implemented
-        }
+        if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK))
+          {
+            log_printf(TRACE,Commit_unit,FUNCTION,"  * UPDATE");
+
+            entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front();
+
+            switch (entry->state)
+              {
+//               case ROB_END_EXCEPTION_UPDATE :
+//                 {
+//                   entry->state = ROB_END_KO;
+//                   throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n"));
+//                   break;
+//                 }
+              case ROB_END_LOAD_MISS_UPDATE :
+                {
+                  log_printf(TRACE,Commit_unit,FUNCTION,"    * ROB_END_LOAD_MISS_UPDATE");
+
+                  entry->state = ROB_END_LOAD_MISS;
+                  break;
+                }
+              default :
+                {
+                  throw ERRORMORPHEO(FUNCTION,_("Update : invalid state.\n"));
+                  break;
+                }
+              }
+
+          }
 
 	// ===================================================================
@@ -438,6 +484,6 @@
 
               Tdepth_t     depth_min    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0;
-//               Tdepth_t     depth_max    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;
-//               Tcontrol_t   depth_full   = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);
+              Tdepth_t     depth_max    = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;
+              Tcontrol_t   depth_full   = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);
               
               // is a valid instruction ?
@@ -455,18 +501,21 @@
               // ....... max ...X... min ....... KO
               
-//               Tcontrol_t   is_valid      = ((depth == depth_min) or 
-//                                             depth_full or
-//                                             ((depth_min <= depth_max)?
-//                                              ((depth >= depth_min) and (depth <=depth_max)):
-//                                              ((depth >= depth_min) or  (depth <=depth_max))));
-
               bool         flush         = reg_EVENT_FLUSH [front_end_id][context_id];
-              Tcontrol_t   is_valid      = ((depth == depth_min) and not flush);
+
+              Tcontrol_t   is_valid      = (((depth == depth_min) or 
+                                             depth_full or
+                                             ((depth_min <= depth_max)?
+                                              ((depth >= depth_min) and (depth <=depth_max)):
+                                              ((depth >= depth_min) or  (depth <=depth_max))))
+                                             and not flush);
+
+//            Tcontrol_t   is_valid      = ((depth == depth_min) and not flush);
 
               log_printf(TRACE,Commit_unit,FUNCTION,"  * HEAD              [%d]",i);
-              log_printf(TRACE,Commit_unit,FUNCTION,"    * is_valid        : %d",is_valid);
+              log_printf(TRACE,Commit_unit,FUNCTION,"    * is_valid        : %d ((depth == depth_min) and not flush)",is_valid);
               log_printf(TRACE,Commit_unit,FUNCTION,"    * depth           : %d",depth    );
               log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_min       : %d",depth_min);
-//               log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_max       : %d",depth_max);
+              log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_max       : %d",depth_max);
+              log_printf(TRACE,Commit_unit,FUNCTION,"    * depth_full      : %d",depth_full);
               log_printf(TRACE,Commit_unit,FUNCTION,"    * flush           : %d",flush);
 
@@ -481,4 +530,5 @@
 		    case ROB_BRANCH_COMPLETE             : {state = ROB_END_MISS     ; break;}
                     case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS     ; break;}
+                    case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_MISS     ; break;}
 		    case ROB_STORE_WAIT_HEAD_OK          : {state = ROB_STORE_HEAD_KO; break;}
 		  //case ROB_STORE_WAIT_HEAD_KO          : {state = ; break;}
@@ -498,4 +548,7 @@
 		    case ROB_END_KO                      :
                     case ROB_END_BRANCH_MISS             :
+                    case ROB_END_LOAD_MISS_UPDATE        :
+                    case ROB_END_LOAD_MISS               :
+		    case ROB_END_EXCEPTION_UPDATE        :
 		    case ROB_END_EXCEPTION               :
 		    default                              : 
@@ -517,4 +570,5 @@
 		    case ROB_END_KO_SPECULATIVE          : {state = ROB_END_KO                 ; break;}
 		    case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS        ; break;}
+		    case ROB_END_LOAD_MISS_SPECULATIVE   : {state = ROB_END_LOAD_MISS_UPDATE   ; break;}
 		    default : {break;}
 		  }
@@ -528,6 +582,6 @@
 		  switch (state)
 		    {
-		    case ROB_STORE_WAIT_HEAD_OK      : {state = ROB_STORE_HEAD_OK; break;}
-		    case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION; break;}
+		    case ROB_STORE_WAIT_HEAD_OK      : {state = ROB_STORE_HEAD_OK;        break;}
+		    case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;}
 		    default : {break;}
 		    }
@@ -549,6 +603,9 @@
       for (uint32_t j=0; j<_param->_nb_context [i]; j++)
         {
-          log_printf(TRACE,Commit_unit,FUNCTION,"    * [%d][%d] num_inst_all : %d, num_inst_mem : %d",i,j,reg_NB_INST_COMMIT_ALL[i][j],reg_NB_INST_COMMIT_MEM[i][j]);
           log_printf(TRACE,Commit_unit,FUNCTION,"    * [%d][%d] state        : %s",i,j,toString(reg_EVENT_STATE [i][j]).c_str());
+          log_printf(TRACE,Commit_unit,FUNCTION,"    * num_inst_all : %d",reg_NB_INST_COMMIT_ALL[i][j]);
+          log_printf(TRACE,Commit_unit,FUNCTION,"    * num_inst_mem : %d",reg_NB_INST_COMMIT_MEM[i][j]);
+          log_printf(TRACE,Commit_unit,FUNCTION,"    * PC_CURRENT   : %.8x - %d %d",reg_PC_CURRENT [i][j], reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]);
+          log_printf(TRACE,Commit_unit,FUNCTION,"    * PC_NEXT      : %.8x",reg_PC_NEXT [i][j]);
         }
 	
@@ -567,5 +624,5 @@
 	     it++)
 	  {
-            log_printf(TRACE,Commit_unit,FUNCTION,"      [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x (%.8x) %.1d, %.1d %.4d, %.1d %.4d, %s - %d",
+            log_printf(TRACE,Commit_unit,FUNCTION,"      [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s - %d",
                        x,
                        (*it)->front_end_id            ,
@@ -575,6 +632,6 @@
                        (*it)->type                    ,
                        (*it)->operation               ,
-                       (*it)->address                 ,
-                       (*it)->address << 2            ,
+//                     (*it)->address                 ,
+//                     (*it)->address << 2            ,
                        (*it)->is_delay_slot           ,
                        (*it)->use_store_queue         ,
@@ -603,10 +660,11 @@
                        (*it)->num_reg_re_phy_new      );
             
-            log_printf(TRACE,Commit_unit,FUNCTION,"             %.2d %.2d %.1d %.1d %.8x",
+            log_printf(TRACE,Commit_unit,FUNCTION,"             %.2d %.2d %.1d %.1d %.8x (%.8x)",
                        (*it)->exception_use ,
                        (*it)->exception     ,
                        (*it)->flags         ,
                        (*it)->no_sequence   ,
-                       (*it)->data_commit   
+                       (*it)->address_next  ,
+                       (*it)->address_next<<2
                        );
 
