Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (revision 106) @@ -18,4 +18,211 @@ namespace load_store_unit { +template +T swapBytes (T data, uint32_t size_data, uint32_t size_access) +{ + uint64_t x = static_cast(data); + +// switch (size_data) +// { +// case 2 : // 16 bits +// { +// switch (size_access) +// { +// case 2 : +// { +// x = ((((x>> 8)&0xff) << 0) | +// (((x>> 0)&0xff) << 8) ); +// break; +// } +// default : +// { +// break; +// } +// } +// break; +// } +// case 4 : // 32 bits +// { +// switch (size_access) +// { +// case 2 : +// { +// x = ((((x>> 8)&0xff) << 0) | +// (((x>> 0)&0xff) << 8) | +// (((x>>24)&0xff) << 16) | +// (((x>>16)&0xff) << 24) ); +// break; +// } +// case 4 : +// { +// x = ((((x>>24)&0xff) << 0) | +// (((x>>16)&0xff) << 8) | +// (((x>> 8)&0xff) << 16) | +// (((x>> 0)&0xff) << 24) ); +// break; +// } +// default : +// { +// break; +// } +// } +// break; +// } +// case 8 : // 64 bits +// { +// switch (size_access) +// { +// case 2 : +// { +// x = ((((x>> 8)&0xff) << 0) | +// (((x>> 0)&0xff) << 8) | +// (((x>>24)&0xff) << 16) | +// (((x>>16)&0xff) << 24) | +// (((x>>40)&0xff) << 32) | +// (((x>>32)&0xff) << 40) | +// (((x>>56)&0xff) << 48) | +// (((x>>48)&0xff) << 56) ); +// break; +// } +// case 4 : +// { +// x = ((((x>>24)&0xff) << 0) | +// (((x>>16)&0xff) << 8) | +// (((x>> 8)&0xff) << 16) | +// (((x>> 0)&0xff) << 24) | +// (((x>>56)&0xff) << 32) | +// (((x>>48)&0xff) << 40) | +// (((x>>40)&0xff) << 48) | +// (((x>>32)&0xff) << 56) ); +// break; +// } +// case 8 : +// { +// x = ((((x>>56)&0xff) << 0) | +// (((x>>48)&0xff) << 8) | +// (((x>>40)&0xff) << 16) | +// (((x>>32)&0xff) << 24) | +// (((x>>24)&0xff) << 32) | +// (((x>>16)&0xff) << 40) | +// (((x>> 8)&0xff) << 48) | +// (((x>> 0)&0xff) << 56) ); +// break; +// } +// default : +// { +// break; +// } +// } +// break; +// } +// default : +// { +// break; +// } +// } + + + uint64_t y=0; + + for (uint32_t i=0; i>( 8+offset))&0xff) << ( 0+offset)) | + (((x>>( 0+offset))&0xff) << ( 8+offset)) ); + break; + } + case 4 : + { + y |= ((((x>>(24+offset))&0xff) << ( 0+offset)) | + (((x>>(16+offset))&0xff) << ( 8+offset)) | + (((x>>( 8+offset))&0xff) << (16+offset)) | + (((x>>( 0+offset))&0xff) << (24+offset)) ); + break; + } + case 8 : + { + y |= ((((x>>(56+offset))&0xff) << ( 0+offset)) | + (((x>>(48+offset))&0xff) << ( 8+offset)) | + (((x>>(40+offset))&0xff) << (16+offset)) | + (((x>>(32+offset))&0xff) << (24+offset)) | + (((x>>(24+offset))&0xff) << (32+offset)) | + (((x>>(16+offset))&0xff) << (40+offset)) | + (((x>>( 8+offset))&0xff) << (48+offset)) | + (((x>>( 0+offset))&0xff) << (56+offset)) ); + break; + } + default : + { + break; + } + } + } + + return static_cast(y); +} + +template +T swapBits (T data, uint32_t size_data, uint32_t size_access) +{ + uint8_t x = static_cast(data); + + uint8_t y=0; + + for (uint32_t i=0; i>( 1+offset))&0x1) << ( 0+offset)) | + (((x>>( 0+offset))&0x1) << ( 1+offset)) ); + break; + } + case 4 : + { + y |= ((((x>>( 3+offset))&0x1) << ( 0+offset)) | + (((x>>( 2+offset))&0x1) << ( 1+offset)) | + (((x>>( 1+offset))&0x1) << ( 2+offset)) | + (((x>>( 0+offset))&0x1) << ( 3+offset)) ); + break; + } + case 8 : + { + y |= ((((x>>( 7+offset))&0x1) << ( 0+offset)) | + (((x>>( 6+offset))&0x1) << ( 1+offset)) | + (((x>>( 5+offset))&0x1) << ( 2+offset)) | + (((x>>( 4+offset))&0x1) << ( 3+offset)) | + (((x>>( 3+offset))&0x1) << ( 4+offset)) | + (((x>>( 2+offset))&0x1) << ( 5+offset)) | + (((x>>( 1+offset))&0x1) << ( 6+offset)) | + (((x>>( 0+offset))&0x1) << ( 7+offset)) ); + break; + } + default : + { + break; + } + } + } + + return static_cast(y); +} #undef FUNCTION @@ -83,4 +290,6 @@ log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store); + log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read : %d",reg_STORE_QUEUE_PTR_READ); + if (index_store == reg_STORE_QUEUE_PTR_READ) { @@ -148,9 +357,34 @@ // Read data - Tgeneral_data_t load_data = _load_queue [index_load ]._rdata ; - Tgeneral_data_t store_data = _store_queue[index_store]._wdata ; - - log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (before): 0x%.8x",load_data); - log_printf(TRACE,Load_store_unit,FUNCTION," * store_data (before): 0x%.8x",store_data); + bool is_big_endian = true; + + Tgeneral_data_t load_data = _load_queue [index_load ]._rdata ; + Tgeneral_data_t store_data = _store_queue[index_store]._wdata ; + Tdcache_address_t check_hit_byte = _load_queue [index_load ]._check_hit_byte; + Tcontrol_t check_hit = _load_queue [index_load ]._check_hit; + uint32_t load_size_access = memory_size(_load_queue [index_load ]._operation)>>3; + uint32_t store_size_access = memory_size(_store_queue[index_store]._operation)>>3; + + log_printf(TRACE,Load_store_unit,FUNCTION," * is_big_endian : %d",is_big_endian); + log_printf(TRACE,Load_store_unit,FUNCTION," * load_data : 0x%.8x",load_data); + log_printf(TRACE,Load_store_unit,FUNCTION," * store_data : 0x%.8x",store_data); + log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",check_hit_byte); + log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %d",check_hit); + + log_printf(TRACE,Load_store_unit,FUNCTION," * load_size_access : %d",load_size_access ); + log_printf(TRACE,Load_store_unit,FUNCTION," * store_size_access : %d",store_size_access); + + if (is_big_endian) + { + // swap in little endian + load_data = swapBytes(load_data , _param->_size_general_data>>3,load_size_access); + store_data = swapBytes(store_data , _param->_size_general_data>>3,store_size_access); + check_hit_byte = swapBits (check_hit_byte, _param->_size_general_data>>3,load_size_access); + + + log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (swap 1) : 0x%.8x",load_data); + log_printf(TRACE,Load_store_unit,FUNCTION," * store_data (swap 1) : 0x%.8x",store_data); + log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte (swap 1) : %x",check_hit_byte); + } uint32_t store_nb_byte = (1<_mask_address_lsb); +// uint32_t load_num_byte_max = load_num_byte_min+load_nb_byte; + +// log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_min : %d",load_num_byte_min); +// log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_max : %d",load_num_byte_max); + +// for (uint32_t num_load_byte=load_num_byte_min; num_load_byte> 0 - // lw 0 : 0 1 2 3 >> 0 -4 - // lw 4 : 4 5 6 7 >> 32 +4 - // lh 0 : 0 1 >> 0 -6 - // lh 2 : 2 3 >> 16 -2 - // lh 4 : 4 5 >> 32 +2 - // lh 6 : 6 7 >> 48 +6 - // lb 0 : 0 >> 0 -7 - // lb 1 : 1 >> 8 -5 - // lb 2 : 2 >> 16 -3 - // lb 3 : 3 >> 24 -1 - // lb 4 : 4 >> 32 +1 - // lb 5 : 5 >> 40 +3 - // lb 6 : 6 >> 48 +5 - // lb 7 : 7 >> 56 +7 - - // diff : (store_nb_byte + load_nb_byte) - 2*nb_load_byte*((num_store_byte+1) - - // store duplicate = all store access can be see as full size_data store - uint32_t load_nb_byte = (1<>3 : %d",(_param->_size_general_data>>3)); -// log_printf(TRACE,Load_store_unit,FUNCTION," * load_nb_byte : %d",load_nb_byte); -// log_printf(TRACE,Load_store_unit,FUNCTION," * x = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*(num_store_byte/load_nb_byte+1)) = %d+%d-%d*%d = %d" -// , (_param->_size_general_data>>3) -// , load_nb_byte -// , 2*load_nb_byte -// ,((num_store_byte/load_nb_byte)+1) -// ,((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1))); + uint32_t num_load_byte = num_store_byte; + +// if (is_big_endian) +// { +// // sd 0 : 0 1 2 3 4 5 6 7 +// // ld 0 : 0 1 2 3 4 5 6 7 >> 0 +// // lw 0 : 0 1 2 3 >> 0 -4 +// // lw 4 : 4 5 6 7 >> 32 +4 +// // lh 0 : 0 1 >> 0 -6 +// // lh 2 : 2 3 >> 16 -2 +// // lh 4 : 4 5 >> 32 +2 +// // lh 6 : 6 7 >> 48 +6 +// // lb 0 : 0 >> 0 -7 +// // lb 1 : 1 >> 8 -5 +// // lb 2 : 2 >> 16 -3 +// // lb 3 : 3 >> 24 -1 +// // lb 4 : 4 >> 32 +1 +// // lb 5 : 5 >> 40 +3 +// // lb 6 : 6 >> 48 +5 +// // lb 7 : 7 >> 56 +7 + +// // diff : (store_nb_byte + load_nb_byte) - 2*nb_load_byte*((num_store_byte+1) + +// // store duplicate = all store access can be see as full size_data store +// // uint32_t load_nb_byte = (1<_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1)); + +// // num_load_byte =num_store_byte+diff; + +// // log_printf(TRACE,Load_store_unit,FUNCTION," * load_nb_byte : %d",load_nb_byte); +// // log_printf(TRACE,Load_store_unit,FUNCTION," * diff : %d",diff); + + +// num_load_byte = num_store_byte; +// } +// else +// { +// // sd 0 : 0 1 2 3 4 5 6 7 +// // ld 0 : 0 1 2 3 4 5 6 7 >> 0 +// // lw 0 : 4 5 6 7 >> 0 +// // lw 4 : 0 1 2 3 >> 32 +// // lh 0 : 6 7 >> 0 +// // lh 2 : 4 5 >> 16 +// // lh 4 : 2 3 >> 32 +// // lh 6 : 0 1 >> 48 +// // lb 0 : 7 >> 0 +// // lb 1 : 6 >> 8 +// // lb 2 : 5 >> 16 +// // lb 3 : 4 >> 24 +// // lb 4 : 3 >> 32 +// // lb 5 : 2 >> 40 +// // lb 6 : 1 >> 48 +// // lb 7 : 0 >> 56 - - num_load_byte =num_store_byte+((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1)); - } - else - { - // sd 0 : 0 1 2 3 4 5 6 7 - // ld 0 : 0 1 2 3 4 5 6 7 >> 0 - // lw 0 : 4 5 6 7 >> 0 - // lw 4 : 0 1 2 3 >> 32 - // lh 0 : 6 7 >> 0 - // lh 2 : 4 5 >> 16 - // lh 4 : 2 3 >> 32 - // lh 6 : 0 1 >> 48 - // lb 0 : 7 >> 0 - // lb 1 : 6 >> 8 - // lb 2 : 5 >> 16 - // lb 3 : 4 >> 24 - // lb 4 : 3 >> 32 - // lb 5 : 2 >> 40 - // lb 6 : 1 >> 48 - // lb 7 : 0 >> 56 - - num_load_byte = num_store_byte; - } - +// num_load_byte = num_store_byte; +// } + uint32_t mask = 1<(load_data,num_load_bit_max,num_load_bit_min)); - _load_queue[index_load]._check_hit_byte |= mask; - _load_queue[index_load]._check_hit = 1; + check_hit_byte |= mask; + check_hit = 1; change_state = true; @@ -267,9 +510,23 @@ } - _load_queue[index_load]._rdata = load_data; + if (is_big_endian) + { + // swap in little endian + load_data = swapBytes(load_data , _param->_size_general_data>>3,load_size_access); + check_hit_byte = swapBits (check_hit_byte, _param->_size_general_data>>3,load_size_access); + + + log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (swap 2) : 0x%.8x",load_data); + log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte (swap 2) : %x",check_hit_byte); + } + + _load_queue[index_load]._rdata = load_data; + _load_queue[index_load]._check_hit_byte = check_hit_byte; + _load_queue[index_load]._check_hit = check_hit; + log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (after) : 0x%.8x",load_data); - log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x",_load_queue[index_load]._check_hit); - log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",_load_queue[index_load]._check_hit_byte); + log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x",check_hit); + log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",check_hit_byte); log_printf(TRACE,Load_store_unit,FUNCTION," * mask_end_check : %x",(-1& _param->_mask_address_lsb)); @@ -295,4 +552,5 @@ { log_printf(TRACE,Load_store_unit,FUNCTION," * next"); + log_printf(TRACE,Load_store_unit,FUNCTION," * new store_queue_ptr_write : %d",index_store); // if (_load_queue[index_load]._store_queue_ptr_write == 0) // _load_queue[index_load]._store_queue_ptr_write = _param->_size_store_queue-1; @@ -312,8 +570,16 @@ { log_printf(TRACE,Load_store_unit,FUNCTION," * change_state"); + log_printf(TRACE,Load_store_unit,FUNCTION," * end_check : %d",end_check); + + log_printf(TRACE,Load_store_unit,FUNCTION," * state old : %s",toString(_load_queue[index_load]._state).c_str()); switch (_load_queue[index_load]._state) { - case LOAD_QUEUE_WAIT_CHECK : _load_queue[index_load]._state = LOAD_QUEUE_WAIT ; break; + case LOAD_QUEUE_WAIT_CHECK : + { + if (end_check) + _load_queue[index_load]._state = LOAD_QUEUE_WAIT ; + break; + } case LOAD_QUEUE_COMMIT_CHECK : { @@ -321,5 +587,5 @@ _load_queue[index_load]._state = LOAD_QUEUE_COMMIT; else - _load_queue[index_load]._state = LOAD_QUEUE_CHECK; + _load_queue[index_load]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end break; } @@ -328,6 +594,9 @@ if (end_check) _load_queue[index_load]._state = LOAD_QUEUE_COMMIT; + // check find a bypass. A speculative load have been committed : report a speculation miss. - if (_load_queue[index_load]._check_hit != 0) + if ((_load_queue[index_load]._check_hit != 0)// and +// (_load_queue[index_load]._write_rd == 0) + ) { _load_queue[index_load]._exception = EXCEPTION_MEMORY_MISS_SPECULATION; @@ -339,5 +608,5 @@ default : break; } - log_printf(TRACE,Load_store_unit,FUNCTION," * new state : %d",_load_queue[index_load]._state); + log_printf(TRACE,Load_store_unit,FUNCTION," * state new : %s",toString(_load_queue[index_load]._state).c_str()); log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",_load_queue[index_load]._exception); } @@ -712,4 +981,5 @@ log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d" , packet_id); + log_printf(TRACE,Load_store_unit,FUNCTION," * packet_id : %d" , packet_id>>1); log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x", rdata); log_printf(TRACE,Load_store_unit,FUNCTION," * error : %d" , error); @@ -719,7 +989,6 @@ packet_id >>= 1; - log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD : %d", packet_id); + log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD"); - #ifdef DEBUG_TEST if (not have_dcache_rsp(_load_queue [packet_id]._operation)) @@ -754,5 +1023,5 @@ { log_printf(TRACE,Load_store_unit,FUNCTION," * have no bus error."); - log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %d.",_load_queue [packet_id]._state); + log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %s",toString(_load_queue [packet_id]._state).c_str()); // FIXME : convention : if bus error, the cache return the fautive address ! Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_write_status.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_write_status.cpp (revision 105) +++ (revision ) @@ -1,2 +1,0 @@ - - Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_min.cfg (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_min.cfg (revision 106) @@ -3,5 +3,5 @@ 1 1 +1 # nb_decod_unit 1 1 +1 # nb_inst_branch_complete -0 0 +1 # size_depth [0] [nb_context] +1 1 +1 # nb_inst_branch_speculated [0] [nb_context] 32 32 +1 # size_general_data 1 1 +1 # size_inst_decod [0] [nb_decod_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_mono_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_mono_context.cfg (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_mono_context.cfg (revision 106) @@ -3,5 +3,5 @@ 1 1 *4 # nb_decod_unit 1 4 *4 # nb_inst_branch_complete -0 2 +1 # size_depth [0] [nb_context] +1 4 *2 # nb_inst_branch_speculated [0] [nb_context] 32 32 +1 # size_general_data 1 4 *4 # size_inst_decod [0] [nb_decod_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_multi_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_multi_context.cfg (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_multi_context.cfg (revision 106) @@ -3,12 +3,12 @@ 4 4 *4 # nb_decod_unit 2 2 *4 # nb_inst_branch_complete -4 4 +1 # size_depth [0] [nb_context] -2 2 +1 # size_depth [1] [nb_context] -1 1 +1 # size_depth [2] [nb_context] -0 0 +1 # size_depth [3] [nb_context] -4 4 +1 # size_depth [4] [nb_context] -2 2 +1 # size_depth [5] [nb_context] -1 1 +1 # size_depth [6] [nb_context] -0 0 +1 # size_depth [7] [nb_context] +6 6 +1 # nb_inst_branch_speculated [0] [nb_context] +3 3 +1 # nb_inst_branch_speculated [1] [nb_context] +2 2 +1 # nb_inst_branch_speculated [2] [nb_context] +1 1 +1 # nb_inst_branch_speculated [3] [nb_context] +8 8 +1 # nb_inst_branch_speculated [4] [nb_context] +4 4 +1 # nb_inst_branch_speculated [5] [nb_context] +2 2 +1 # nb_inst_branch_speculated [6] [nb_context] +1 1 +1 # nb_inst_branch_speculated [7] [nb_context] 32 32 +1 # size_general_data 4 4 *4 # size_inst_decod [0] [nb_decod_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/main.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/main.cpp (revision 106) @@ -17,5 +17,5 @@ err (_(" * nb_decod_unit (uint32_t)\n")); err (_(" * nb_inst_branch_complete (uint32_t)\n")); - err (_(" * size_depth [nb_context] (uint32_t)\n")); + err (_(" * nb_inst_branch_speculated [nb_context] (uint32_t)\n")); err (_(" * size_general_data (uint32_t)\n")); err (_(" * size_inst_decod [nb_decod_unit] (uint32_t)\n")); @@ -48,7 +48,7 @@ usage (argc, argv); - uint32_t * _size_depth = new uint32_t [_nb_context]; + uint32_t * _nb_inst_branch_speculated = new uint32_t [_nb_context]; for (uint32_t i=0; i<_nb_context; i++) - _size_depth [i] = fromString(argv[x++]); + _nb_inst_branch_speculated [i] = fromString(argv[x++]); uint32_t _size_general_data = fromString(argv[x++]); @@ -69,5 +69,5 @@ _nb_decod_unit , _nb_inst_branch_complete , - _size_depth , + _nb_inst_branch_speculated , _size_general_data , _size_inst_decod , @@ -87,5 +87,5 @@ } - delete [] _size_depth; + delete [] _nb_inst_branch_speculated; delete [] _size_inst_decod; delete [] _link_context_to_decod_unit; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 106) @@ -275,5 +275,5 @@ for (uint32_t i=0; i<_param->_nb_context; i++) if (_param->_have_port_depth) - in_DEPTH_MIN [i]->write((_param->_array_size_depth[i]==0)?0:(i%_param->_array_size_depth[i])); + in_DEPTH_MIN [i]->write((log2(_param->_nb_inst_branch_speculated[i])==0)?0:(i%log2(_param->_nb_inst_branch_speculated[i]))); uint32_t context = rand()%_param->_nb_context; @@ -295,5 +295,5 @@ in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef); if (_param->_have_port_depth) - in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); + in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_MSYNC); @@ -350,5 +350,5 @@ in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe); if (_param->_have_port_depth) - in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); + in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC); @@ -428,5 +428,5 @@ in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdead0300); if (_param->_have_port_depth) - in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); + in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC); @@ -507,5 +507,5 @@ in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdead0400); if (_param->_have_port_depth) - in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); + in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_SPR_ACCESS); @@ -559,5 +559,5 @@ // in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); // if (_param->_have_port_depth) -// in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); +// in_BRANCH_COMPLETE_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); // in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400); // in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500); @@ -580,5 +580,5 @@ if (_param->_have_port_depth) - in_BRANCH_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); + in_BRANCH_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x400); in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x500); @@ -649,5 +649,5 @@ // in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); // if (_param->_have_port_depth) -// in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); +// in_BRANCH_COMPLETE_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); // in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600); // in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700); @@ -669,5 +669,5 @@ uint32_t port = context; - in_BRANCH_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); + in_BRANCH_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x600); in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x700); @@ -736,5 +736,5 @@ in_DECOD_EVENT_CONTEXT_ID [port]->write(context); if (_param->_have_port_depth) - in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); + in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context]))); in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0); @@ -830,5 +830,5 @@ in_DECOD_EVENT_CONTEXT_ID [port]->write(context); if (_param->_have_port_depth) - in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); + in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context]))); in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(1); @@ -922,5 +922,5 @@ in_COMMIT_EVENT_CONTEXT_ID ->write(context); if (_param->_have_port_depth) - in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); + in_COMMIT_EVENT_DEPTH ->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context]))); in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0); @@ -1017,5 +1017,5 @@ in_COMMIT_EVENT_CONTEXT_ID ->write(context); if (_param->_have_port_depth) - in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); + in_COMMIT_EVENT_DEPTH ->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context]))); in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1); @@ -1112,5 +1112,5 @@ in_COMMIT_EVENT_CONTEXT_ID ->write(context); if (_param->_have_port_depth) - in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); + in_COMMIT_EVENT_DEPTH ->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context]))); in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0); @@ -1207,5 +1207,5 @@ in_COMMIT_EVENT_CONTEXT_ID ->write(context); if (_param->_have_port_depth) - in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); + in_COMMIT_EVENT_DEPTH ->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context]))); in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Parameters.h (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Parameters.h (revision 106) @@ -27,5 +27,5 @@ public : uint32_t _nb_decod_unit ; public : uint32_t _nb_inst_branch_complete ; - public : uint32_t * _array_size_depth ; //[nb_context] + public : uint32_t * _nb_inst_branch_speculated ; //[nb_context] //public : uint32_t * _size_depth ; //[nb_context] //public : uint32_t _size_general_data ; @@ -38,5 +38,5 @@ uint32_t nb_decod_unit, uint32_t nb_inst_branch_complete, - uint32_t * size_depth, + uint32_t * nb_inst_branch_speculated, uint32_t size_general_data, uint32_t * size_nb_inst_decod, Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (revision 106) @@ -196,6 +196,4 @@ log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); -// throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n")); - context_state_t state = reg_STATE [i]; @@ -203,13 +201,16 @@ Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; - Tdepth_t depth_max = _param->_array_size_depth [i]; + Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i]; -// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); -// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); - Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); - Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); + Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); + Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); +// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); +// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); // priority : miss > excep > spr/sync - uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); + uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or + (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); uint8_t priority1 = 2; // miss @@ -217,8 +218,17 @@ // if context_state_ok : yes // if context_state_ko : test the depth, and the priority of event - bool is_valid = ((state == CONTEXT_STATE_OK) or (depth1< depth0) or ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth + + log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); + log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); + log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); + log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); + log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); + log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); + log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); + log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); + log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); if (is_valid) @@ -251,10 +261,10 @@ Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; - Tdepth_t depth_max = _param->_array_size_depth [context]; + Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; -// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); -// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); - Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); - Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); + Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); + Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); +// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); +// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); context_state_t state = reg_STATE [context]; @@ -262,5 +272,8 @@ // miss > excep > spr/sync - uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); + uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or + (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; @@ -272,4 +285,14 @@ (depth1< depth0) or ((depth1==depth0) and (priority1>=priority0))); + + log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); + log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); + log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); + log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); + log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); + log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); + log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); + log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); + log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); if (is_valid) @@ -371,10 +394,10 @@ Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; - Tdepth_t depth_max = _param->_array_size_depth [context]; + Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; -// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); -// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); - Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); - Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); + Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); + Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); +// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); +// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); context_state_t state = reg_STATE [context]; @@ -382,5 +405,8 @@ // miss > excep > spr/sync - uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); + uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or + (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or + (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) @@ -392,4 +418,14 @@ (depth1< depth0) or ((depth1==depth0) and (priority1>=priority0))); + + log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); + log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); + log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); + log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); + log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); + log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); + log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); + log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); + log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); if (is_valid) @@ -427,56 +463,4 @@ // ------------------------------------------------------------------- - // -----[ BRANCH_COMPLETE ]------------------------------------------- - // ------------------------------------------------------------------- - -// for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) -// if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) -// { -// log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i); -// if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) -// { -// Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; -// Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; -// Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; -// Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; -// Tdepth_t depth_max = _param->_array_size_depth [context]; - -// // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); -// // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); -// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); -// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); - -// context_state_t state = reg_STATE [context]; - -// // miss > excep > spr/sync -// uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); -// uint8_t priority1 = 2; // miss - -// // is_valid = can modify local information -// // if context_state_ok : yes -// // if context_state_ko : test the depth, and the priority of envent - -// bool is_valid = ((state == CONTEXT_STATE_OK) or -// (depth1< depth0) or -// ((depth1==depth0) and (priority1>=priority0))); - -// if (is_valid) -// { -// // commit -// Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]); -// reg_STATE [context] = CONTEXT_STATE_KO_MISS; -// reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT -// reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]); -// reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence -// //reg_EVENT_ADDRESS_EEAR [context]; -// reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; -// reg_EVENT_IS_DELAY_SLOT [context] = take; -// reg_EVENT_IS_DS_TAKE [context] = take; -// reg_EVENT_DEPTH [context] = depth; -// } -// } -// } - - // ------------------------------------------------------------------- // -----[ EVENT ]----------------------------------------------------- // ------------------------------------------------------------------- Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters.cpp (revision 106) @@ -22,5 +22,5 @@ uint32_t nb_decod_unit, uint32_t nb_inst_branch_complete, - uint32_t * size_depth, + uint32_t * nb_inst_branch_speculated, uint32_t size_general_data, uint32_t * size_nb_inst_decod, @@ -34,5 +34,5 @@ _nb_decod_unit = nb_decod_unit ; _nb_inst_branch_complete = nb_inst_branch_complete ; - _array_size_depth = size_depth ; + _nb_inst_branch_speculated = nb_inst_branch_speculated ; // _size_general_data = size_general_data ; // _size_nb_inst_decod = size_nb_inst_decod ; @@ -45,5 +45,5 @@ { _size_context_id = log2(_nb_context); - _size_depth = log2(max(size_depth,_nb_context)); + _size_depth = log2(max(nb_inst_branch_speculated,_nb_context)); _size_general_data = size_general_data; _size_instruction_address = size_general_data-2; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp (revision 106) @@ -85,5 +85,5 @@ else { - // Cusume the instruction (to erase) + // Consume the instruction (to erase) internal_DECOD_OUT_ACK [i] = 1; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp (revision 106) @@ -144,5 +144,5 @@ // * BTB hit and the branchement is the PC current and it's the last slot. // -> next pc must be the delay slot - if ((not pc_current_is_ds_take) and // if pc_current is ds_take, alors pc_next is the destination of branchement + if ((not pc_current_is_ds_take) and // if pc_current is ds_take, then pc_next is the destination of branchement (address_src_lsb == (_param->_nb_instruction [context]-1))) { @@ -173,5 +173,6 @@ log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK"); - // use none unit (dir, upt and ras) + // use none unit (dir and ras) + use_upt = true; direction = true; pc_next = address_dest; @@ -324,4 +325,10 @@ ); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * btb_{ val, ack} : %d, %d", btb_val, btb_ack); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * dir_{use, val, ack} : %d, %d, %d",use_dir,dir_val, dir_ack); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * ras_{use, val, ack} : %d, %d, %d",use_ras,ras_val, ras_ack); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * upt_{use, val, ack} : %d, %d, %d",use_upt,upt_val, upt_ack); + + // pc_next - is previously computed // branch_state - is previously computed Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 106) @@ -1424,5 +1424,4 @@ (upt_top [context] != out_DEPTH_MAX [context]->read())) SC_START(1); - } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h (revision 106) @@ -47,6 +47,7 @@ UPDATE_PREDICTION_STATE_KO , // this branch is a miss prediction UPDATE_PREDICTION_STATE_EVENT , // previous branch is a miss prediction - UPDATE_PREDICTION_STATE_END_OK , // branch is updated, update pointer - UPDATE_PREDICTION_STATE_END_KO_WAIT_END , // branch is updated, don't update pointer + UPDATE_PREDICTION_STATE_END , // update pointer +// UPDATE_PREDICTION_STATE_END_OK , // branch is updated, update pointer +// UPDATE_PREDICTION_STATE_END_KO_WAIT_END , // branch is updated, don't update pointer UPDATE_PREDICTION_STATE_END_KO // branch is updated, don't update pointer } upt_state_t; @@ -153,6 +154,7 @@ case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_KO : return "ko" ; break; case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_EVENT : return "event" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_OK : return "end_ok" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_KO_WAIT_END: return "end_ko_wait_end" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END : return "end" ; break; +// case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_OK : return "end_ok" ; break; +// case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_KO_WAIT_END: return "end_ko_wait_end" ; break; case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_KO : return "end_ko" ; break; default : return "" ; break; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 106) @@ -168,4 +168,5 @@ private : uint32_t * reg_UFPT_UPDATE ; //[nb_context] private : uint32_t * reg_UFPT_NB_NEED_UPDATE ; //[nb_context] + private : uint32_t * reg_UFPT_NB_UPDATE ; //[nb_context] private : upt_entry_t ** reg_UPDATE_PREDICTION_TABLE ; //[nb_context][size_upt_queue] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 106) @@ -197,4 +197,5 @@ ALLOC1(reg_UFPT_UPDATE ,uint32_t ,_param->_nb_context); ALLOC1(reg_UFPT_NB_NEED_UPDATE ,uint32_t ,_param->_nb_context); + ALLOC1(reg_UFPT_NB_UPDATE ,uint32_t ,_param->_nb_context); ALLOC2(reg_UPDATE_PREDICTION_TABLE ,upt_entry_t ,_param->_nb_context,_param->_size_upt_queue[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 106) @@ -150,4 +150,5 @@ DELETE1(reg_UFPT_UPDATE ,_param->_nb_context); DELETE1(reg_UFPT_NB_NEED_UPDATE ,_param->_nb_context); + DELETE1(reg_UFPT_NB_UPDATE ,_param->_nb_context); DELETE2(reg_UPDATE_PREDICTION_TABLE ,_param->_nb_context,_param->_size_upt_queue[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp (revision 106) @@ -61,5 +61,5 @@ bool retire_ras_from_ufpt [_param->_nb_context]; // event ufpt -> restore RAS, else update upt bool retire_ras_from_upt [_param->_nb_context]; // event upt -> restore RAS, else restore others structure -// bool have_event [_param->_nb_context]; +// bool have_event [_param->_nb_context]; bool ufpt_update [_param->_nb_context]; bool upt_update [_param->_nb_context]; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 106) @@ -39,4 +39,5 @@ reg_UFPT_UPDATE [i] = 0; reg_UFPT_NB_NEED_UPDATE [i] = 0; + reg_UFPT_NB_UPDATE [i] = 0; for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j) @@ -92,17 +93,15 @@ { uint32_t bottom = reg_UPT_BOTTOM [i]; - bool end_ok = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK); - bool end_ko = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO); + bool end = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END); +// bool end_ok = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK); +// bool end_ko = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO); // event_state_t event_state = reg_EVENT_STATE [i]; // Test if state is end -// if ((end_ok or end_ko) and -// ((event_state != EVENT_STATE_UPDATE_CONTEXT) and -// (event_state != EVENT_STATE_WAIT_END_EVENT))) - if (end_ok or end_ko) +// if (end_ok or end_ko) + if (end) { log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom); - // Free slot reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY; @@ -110,5 +109,5 @@ // Update pointer reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i]; - + if (reg_UPT_BOTTOM [i] == reg_UPT_TOP [i]) reg_UPT_EMPTY [i] = true; // free a slot @@ -118,5 +117,4 @@ if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom)) -// if (end_ko) // free { log_printf(TRACE,Update_Prediction_Table,FUNCTION," * END EVENT"); @@ -129,7 +127,9 @@ reg_UPT_EMPTY [i] = false; } + } } } + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (END)"); @@ -450,5 +450,6 @@ // if free a slot, also all queue is updated // Last slot ? - if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) +// if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) + if ((--reg_UFPT_NB_UPDATE [context])==0) switch (reg_EVENT_STATE [context]) { @@ -472,6 +473,5 @@ reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END; - - + // Update pointer log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]); @@ -531,8 +531,9 @@ else { - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_OK (update)",context,depth); - - reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK; - +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_OK (update)",context,depth); +// reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth); + reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END; #ifdef STATISTICS @@ -650,18 +651,25 @@ reg_EVENT_STATE [i] = EVENT_STATE_OK; reg_IS_ACCURATE [i] = true; - -// Tdepth_t depth = reg_UPT_TOP [i]; - -#ifdef DEBUG_TEST -// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO_WAIT_END) -// throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); + + Tdepth_t depth = reg_EVENT_UPT_PTR [i]; + + if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_END_KO) + { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (event)",i,depth); + + reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END; + } + +#ifdef DEBUG_TEST +// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO_WAIT_END) +// throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO) // throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); #endif - -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",i,depth); - -// reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END_KO; - + +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",i,depth); + +// reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END_KO; + break; } @@ -685,19 +693,19 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); - -#ifdef DEBUG_TEST - if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) - throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); -#endif - - // flush all slot after the event - for (uint32_t j=depth; - j!=top; - j=(j+1)%_param->_size_upt_queue[i]) - reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; - - // test full : - if (full) - reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; + // Test empty + if (not reg_UPT_EMPTY [i]) + { +#ifdef DEBUG_TEST + if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) + throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); +#endif + reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; + + // flush all slot after the event + for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; + j!=top; + j=(j+1)%_param->_size_upt_queue[i]) + reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; + } // reg_UPT_BOTTOM [i]; @@ -802,12 +810,15 @@ { for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) - reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; - + { + reg_UFPT_NB_UPDATE [i] ++; + reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; + } + // TOP is next write slot : last slot is TOP-1 uint32_t top = reg_UFPT_TOP [i]; - reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1; - -// reg_UFPT_BOTTOM [i]; -// reg_UFPT_TOP [i]; + reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1; + +// reg_UFPT_BOTTOM [i]; +// reg_UFPT_TOP [i]; } @@ -853,4 +864,5 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE : %d",reg_UFPT_UPDATE [i]); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]); for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++) log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d, %.8d %.8x %.4d - %s", Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h (revision 106) @@ -80,6 +80,6 @@ //public : uint32_t _size_context_id ; //public : uint32_t _size_address ; + public : uint32_t * _array_size_depth ;//[nb_context] public : uint32_t * _array_size_nb_inst_decod ;//[nb_decod_unit] - public : uint32_t * _array_size_depth ;//[nb_context] //public : uint32_t _max_size_depth ; //public : uint32_t * _size_ifetch_queue_ptr ;//[nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp (revision 106) @@ -100,9 +100,9 @@ // _size_context_id = log2(_nb_context); uint32_t size_instruction_address = size_general_data - 2; - + _array_size_depth = new uint32_t [_nb_context]; for (uint32_t i=0; i<_nb_context; i++) _array_size_depth [i] = log2(_upt_size_queue[i]); - + _array_size_nb_inst_decod = new uint32_t [_nb_decod_unit]; for (uint32_t i=0; i<_nb_decod_unit; i++) @@ -221,5 +221,5 @@ _nb_decod_unit, _nb_inst_branch_complete, - _array_size_depth, + _upt_size_queue, size_instruction_address, _array_size_nb_inst_decod, Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 106) @@ -364,4 +364,7 @@ reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence; reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1); + +// if (entry->address_next != reg_PC_NEXT [front_end_id][context_id]) +// throw ERRORMORPHEO(FUNCTION,toString(_("Retire : Instruction's address_next (%.8x) is different of commit_unit's address_next (%.8x)"),entry->address_next,reg_PC_NEXT [front_end_id][context_id])); } @@ -606,6 +609,6 @@ log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_all : %d",reg_NB_INST_COMMIT_ALL[i][j]); log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_mem : %d",reg_NB_INST_COMMIT_MEM[i][j]); - log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x - %d %d",reg_PC_CURRENT [i][j], reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); - log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x",reg_PC_NEXT [i][j]); + log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); + log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp (revision 106) @@ -79,30 +79,92 @@ #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Free_List_unit == true) - log_printf(TRACE,Free_List_unit,FUNCTION," * Dump Free List"); + { + uint32_t limit = 4; + + log_printf(TRACE,Free_List_unit,FUNCTION," * Dump Free List"); + + for (uint32_t i=0; i<_param->_nb_bank; ++i) + { + uint32_t j=0; + for (std::list::iterator it=_gpr_list->begin(); + it!=_gpr_list->end(); + ) + { + std::string str = ""; + + for (uint32_t x=0; xend()) + break; + else + str+=toString("GPR[%.4d][%.4d] : %.5d | ",i,j,*it); + ++it; + ++j; + } + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); + } + } - for (uint32_t i=0; i<_param->_nb_bank; ++i) + for (uint32_t i=0; i<_param->_nb_bank; ++i) + { + uint32_t j=0; + for (std::list::iterator it=_spr_list->begin(); + it!=_spr_list->end(); + ) + { + std::string str = ""; + + for (uint32_t x=0; xend()) + break; + else + str+=toString("SPR[%.4d][%.4d] : %.5d | ",i,j,*it); + ++it; + ++j; + } + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); + } + } + } +#endif + +#ifdef DEBUG_TEST + if (1) { - uint32_t j=0; - for (std::list::iterator it=_gpr_list->begin(); - it!=_gpr_list->end(); - ++it) + for (std::list::iterator it1=_gpr_list->begin(); + it1!=_gpr_list->end(); + ++it1 + ) { - log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_LIST[%.5d][%.5d] : %.5d",i,j,*it); - ++j; + std::list::iterator it2 = it1; + + it2 ++; + while (it2 != _gpr_list->end()) + { + if (*it1 == *it2) + throw ERRORMORPHEO (FUNCTION,toString(_("In free list, Same GPR (%d)"),*it1)); + it2 ++; + } + } + + for (std::list::iterator it1=_spr_list->begin(); + it1!=_spr_list->end(); + ++it1 + ) + { + std::list::iterator it2 = it1; + + it2 ++; + while (it2 != _spr_list->end()) + { + if (*it1 == *it2) + throw ERRORMORPHEO (FUNCTION,toString(_("In free list, Same SPR (%d)"),*it1)); + it2 ++; + } } } - for (uint32_t i=0; i<_param->_nb_bank; ++i) - { - uint32_t j=0; - for (std::list::iterator it=_spr_list->begin(); - it!=_spr_list->end(); - ++it) - { - log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_LIST[%.5d][%.5d] : %.5d",i,j,*it); - ++j; - } - } +#endif -#endif } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp (revision 106) @@ -245,7 +245,7 @@ in_INSERT_WRITE_RE [i]->write(rand() % 2); in_INSERT_NUM_REG_RD_LOG [i]->write((rand() % (_param->_nb_general_register_logic-1))+1); - in_INSERT_NUM_REG_RE_LOG [i]->write( rand() % _param->_nb_special_register_logic); - in_INSERT_NUM_REG_RD_PHY [i]->write(rand() % _param->_nb_general_register); - in_INSERT_NUM_REG_RE_PHY [i]->write(rand() % _param->_nb_special_register); + in_INSERT_NUM_REG_RE_LOG [i]->write( rand() % _param->_nb_special_register_logic ); + in_INSERT_NUM_REG_RD_PHY [i]->write((rand() % (_param->_nb_general_register -1))+1); + in_INSERT_NUM_REG_RE_PHY [i]->write( rand() % _param->_nb_special_register ); } @@ -285,4 +285,5 @@ if (in_INSERT_VAL [i]->read() and out_INSERT_ACK [i]->read()) { + // ERROR BECAUSE write same register if (in_INSERT_WRITE_RD [i]->read() == 1) rat_gpr[front_end_id][context_id][in_INSERT_NUM_REG_RD_LOG[i]->read()] = in_INSERT_NUM_REG_RD_PHY[i]->read(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp (revision 106) @@ -154,5 +154,6 @@ for (uint32_t i=0; i<_param->_nb_front_end; ++i) for (uint32_t j=0; j<_param->_nb_context[i]; ++j) - sensitive << (*(in_RETIRE_EVENT_STATE [i][j])); + sensitive << (*(in_RETIRE_EVENT_VAL [i][j])) + << (*(in_RETIRE_EVENT_STATE [i][j])); # ifdef SYSTEMCASS_SPECIFIC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp (revision 106) @@ -30,8 +30,10 @@ for (uint32_t j=0; j<_param->_nb_context[i]; j++) { + // An event occure + bool no_event = not (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) and (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)); for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k) - internal_rat_gpr_update_table [i][j][k] = rat_gpr_update_table [i][j][k]; + internal_rat_gpr_update_table [i][j][k] = rat_gpr_update_table [i][j][k] and no_event; for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k) - internal_rat_spr_update_table [i][j][k] = rat_spr_update_table [i][j][k]; + internal_rat_spr_update_table [i][j][k] = rat_spr_update_table [i][j][k] and no_event; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp (revision 106) @@ -64,10 +64,22 @@ Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; + + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id); // Test if write + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",PORT_READ(in_INSERT_WRITE_RD [i])); if (PORT_READ(in_INSERT_WRITE_RD [i]) == 1) - rat_gpr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RD_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]); + { + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",PORT_READ(in_INSERT_NUM_REG_RD_PHY [i])); + rat_gpr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RD_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]); + } + + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",PORT_READ(in_INSERT_WRITE_RE [i])); if (PORT_READ(in_INSERT_WRITE_RE [i]) == 1) - rat_spr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RE_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]); + { + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",PORT_READ(in_INSERT_NUM_REG_RE_PHY [i])); + rat_spr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RE_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]); + } } @@ -109,10 +121,10 @@ Tevent_state_t event_state = PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * event_state : %d",event_state); + if (event_state != EVENT_STATE_NO_EVENT) { - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id); - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * event_state : %d",event_state); - // Test if write and have not a previous update if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1) @@ -150,16 +162,62 @@ #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true) - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)"); - for (uint32_t i=0; i<_param->_nb_front_end; ++i) - for (uint32_t j=0; j<_param->_nb_context[i]; ++j) - { - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j); - - for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k) - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR[%.4d] - %.5d %.1d",k,rat_gpr[i][j][k],rat_gpr_update_table[i][j][k]); - - for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k) - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR[%.4d] - %.5d %.1d",k,rat_spr[i][j][k],rat_spr_update_table[i][j][k]); - } + { + uint32_t limit = 4; + + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)"); + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + { + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j); + + for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit) + { + std::string str = ""; + for (uint32_t x=0; x= _param->_nb_general_register_logic) + break; + else + str+=toString("GPR[%.4d] - %.5d %.1d | ",index,rat_gpr[i][j][index],rat_gpr_update_table[i][j][index]); + } + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); + } + + for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) + { + std::string str = ""; + + for (uint32_t x=0; x= _param->_nb_special_register_logic) + break; + else + str+=toString("SPR[%.4d] - %.5d %.1d | ",index,rat_spr[i][j][index],rat_spr_update_table[i][j][index]); + } + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); + } + } + } +#endif + +#ifdef DEBUG_TEST + if (1) + { + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + { + for (uint32_t x=0; x<_param->_nb_general_register_logic; ++x) + for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y) + if (rat_gpr[i][j][x] == rat_gpr[i][j][y]) + throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr[%d][%d][%d] == rat_gpr[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr[i][j][x])); + for (uint32_t x=0; x<_param->_nb_special_register_logic; ++x) + for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y) + if (rat_spr[i][j][x] == rat_spr[i][j][y]) + throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr[%d][%d][%d] == rat_spr[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr[i][j][x])); + } + + } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp (revision 106) @@ -49,7 +49,12 @@ if (PORT_READ(in_INSERT_VAL[i]) and internal_INSERT_ACK[i]) { + log_printf(TRACE,Stat_List_unit,FUNCTION," * INSERT [%d]",i); + if (PORT_READ(in_INSERT_READ_RA [i])) { Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); + uint32_t bank = num_reg >> _param->_shift_gpr; uint32_t reg = num_reg & _param->_mask_gpr ; @@ -60,4 +65,7 @@ { Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg); + uint32_t bank = num_reg >> _param->_shift_gpr; uint32_t reg = num_reg & _param->_mask_gpr ; @@ -68,4 +76,7 @@ { Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); + uint32_t bank = num_reg >> _param->_shift_spr; uint32_t reg = num_reg & _param->_mask_spr ; @@ -76,4 +87,7 @@ { Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg : %d",num_reg); + uint32_t bank = num_reg >> _param->_shift_gpr; uint32_t reg = num_reg & _param->_mask_gpr ; @@ -84,4 +98,7 @@ { Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg : %d",num_reg); + uint32_t bank = num_reg >> _param->_shift_spr; uint32_t reg = num_reg & _param->_mask_spr ; @@ -96,7 +113,12 @@ if (PORT_READ(in_RETIRE_VAL[i]) and internal_RETIRE_ACK[i]) { + log_printf(TRACE,Stat_List_unit,FUNCTION," * RETIRE [%d]",i); + if (PORT_READ(in_RETIRE_READ_RA [i])) { Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RA_PHY [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); + uint32_t bank = num_reg >> _param->_shift_gpr; uint32_t reg = num_reg & _param->_mask_gpr ; @@ -107,4 +129,7 @@ { Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RB_PHY [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RD - num_reg : %d",num_reg); + uint32_t bank = num_reg >> _param->_shift_gpr; uint32_t reg = num_reg & _param->_mask_gpr ; @@ -115,4 +140,7 @@ { Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RC_PHY [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); + uint32_t bank = num_reg >> _param->_shift_spr; uint32_t reg = num_reg & _param->_mask_spr ; @@ -123,6 +151,12 @@ { Tcontrol_t restore_old = PORT_READ(in_RETIRE_RESTORE_RD_PHY_OLD [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - restore_old : %d",restore_old); + { Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg_old : %d",num_reg); + uint32_t bank = num_reg >> _param->_shift_gpr; uint32_t reg = num_reg & _param->_mask_gpr ; @@ -131,4 +165,7 @@ { Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg_new : %d",num_reg); + uint32_t bank = num_reg >> _param->_shift_gpr; uint32_t reg = num_reg & _param->_mask_gpr ; @@ -140,6 +177,12 @@ { Tcontrol_t restore_old = PORT_READ(in_RETIRE_RESTORE_RE_PHY_OLD [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - restore_old : %d",restore_old); + { Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg_new : %d",num_reg); + uint32_t bank = num_reg >> _param->_shift_spr; uint32_t reg = num_reg & _param->_mask_spr ; @@ -148,4 +191,7 @@ { Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); + + log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg_new : %d",num_reg); + uint32_t bank = num_reg >> _param->_shift_spr; uint32_t reg = num_reg & _param->_mask_spr ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_genMealy_read.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_genMealy_read.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_genMealy_read.cpp (revision 106) @@ -15,7 +15,10 @@ namespace registerfile_monolithic { +#undef FUNCTION +#define FUNCTION "RegisterFile_Monolithic::genMealy_read" void RegisterFile_Monolithic::genMealy_read (void) { - log_printf(FUNC,RegisterFile,"genMealy_read","Begin"); + log_begin(RegisterFile_Monolithic,FUNCTION); + log_function(RegisterFile_Monolithic,FUNCTION,_name.c_str()); for (uint32_t i=0; i<_param->_nb_port_read; i++) @@ -31,5 +34,5 @@ Tdata_t data = reg_DATA[address]; - log_printf(TRACE,RegisterFile,"genMealy_read","[%d] -> %.8x",static_cast(address),static_cast(data)); + log_printf(TRACE,RegisterFile,FUNCTION," * [%d] -> %.8x",static_cast(address),static_cast(data)); // Write in registerFile @@ -38,5 +41,5 @@ else { - //log_printf(TRACE,RegisterFile,"genMealy_read","Read  [%d] : No transaction",i); + //log_printf(TRACE,RegisterFile,FUNCTION,"Read  [%d] : No transaction",i); PORT_WRITE(out_READ_DATA[i],0); } @@ -60,9 +63,9 @@ data = reg_DATA[address]; - log_printf(TRACE,RegisterFile,"genMealy_read","[%d] -> %.8x",static_cast(address),static_cast(data)); + log_printf(TRACE,RegisterFile,FUNCTION," * [%d] -> %.8x",static_cast(address),static_cast(data)); } else { - //log_printf(TRACE,RegisterFile,"genMealy_read","Read  [%d] : No transaction",i); + //log_printf(TRACE,RegisterFile,FUNCTION,"Read  [%d] : No transaction",i); data = 0; } @@ -71,6 +74,5 @@ } - log_printf(FUNC,RegisterFile,"genMealy_read","End"); - + log_end(RegisterFile_Monolithic,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp (revision 106) @@ -14,7 +14,11 @@ namespace registerfile { namespace registerfile_monolithic { + +#undef FUNCTION +#define FUNCTION "RegisterFile_Monolithic::transition" void RegisterFile_Monolithic::transition (void) { - log_printf(FUNC,RegisterFile,"transition","Begin"); + log_begin(RegisterFile_Monolithic,FUNCTION); + log_function(RegisterFile_Monolithic,FUNCTION,_name.c_str()); if (_param->_have_init_value and (PORT_READ(in_NRESET) == 0)) @@ -38,5 +42,5 @@ Tdata_t data = PORT_READ(in_WRITE_DATA [i]); - log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast(address),static_cast(data)); + log_printf(TRACE,RegisterFile,FUNCTION," * [%d] <- %.8x",static_cast(address),static_cast(data)); // Write in registerFile @@ -59,5 +63,5 @@ Tdata_t data = PORT_READ(in_READ_WRITE_WDATA [i]); - log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast(address),static_cast(data)); + log_printf(TRACE,RegisterFile,FUNCTION," * [%d] <- %.8x",static_cast(address),static_cast(data)); // Write in registerFile @@ -82,8 +86,33 @@ #endif +#if defined(DEBUG_RegisterFile_Monolithic) and DEBUG_RegisterFile_Monolithic and (DEBUG >= DEBUG_TRACE) + { + log_printf(TRACE,RegisterFile,FUNCTION," * Dump RegisterFile"); + + uint32_t limit = 4; + + for (uint32_t i=0; i<_param->_nb_word; i+=limit) + { + std::string str = ""; + + for (uint32_t j=0; j= _param->_nb_word) + break; + else + str+=toString("[%.4d] %.8x ",index,reg_DATA[index]); + } + + log_printf(TRACE,RegisterFile,FUNCTION," %s",str.c_str()); + } + } +#endif + #if defined(STATISTICS) or defined(VHDL_TESTBENCH) end_cycle(); #endif - log_printf(FUNC,RegisterFile,"transition","End"); + + log_end(RegisterFile_Monolithic,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_read.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_read.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_read.cpp (revision 106) @@ -17,7 +17,10 @@ +#undef FUNCTION +#define FUNCTION "RegisterFile_Multi_Banked::full_crossbar_genMealy_read" void RegisterFile_Multi_Banked::full_crossbar_genMealy_read (void) { - log_printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read","Begin"); + log_begin(RegisterFile_Multi_Banked,FUNCTION); + log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); bool read_port_use [_param->_nb_bank][_param->_nb_port_read_by_bank]; @@ -32,5 +35,5 @@ bool ack = false; - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read","read[%d] : %d",i,val); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * read [%d] : %d",i,val); if (val == true) @@ -43,7 +46,7 @@ address = 0; - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read"," * address : %d",address); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * address : %d",address); Taddress_t bank = address_bank (address); - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read"," * bank : %d",bank ); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank : %d",bank ); // Search loop @@ -59,10 +62,10 @@ Taddress_t num_reg = address_num_reg (address); - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read"," * num_reg : %d",num_reg); - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read"," * bank_port : %d",j); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * num_reg : %d",num_reg); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank_port : %d",j); Tdata_t data = reg_DATA[bank][num_reg]; - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read"," * data : %d",data); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * data : %d",data); PORT_WRITE(out_READ_DATA [i], data); @@ -77,5 +80,5 @@ } - log_printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read","End"); + log_end(RegisterFile_Multi_Banked,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_write.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_write.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_write.cpp (revision 106) @@ -17,7 +17,10 @@ +#undef FUNCTION +#define FUNCTION "RegisterFile_Multi_Banked::full_crossbar_genMealy_write" void RegisterFile_Multi_Banked::full_crossbar_genMealy_write (void) { - log_printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_genMealy_write","Begin"); + log_begin(RegisterFile_Multi_Banked,FUNCTION); + log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); bool write_port_use [_param->_nb_bank][_param->_nb_port_write_by_bank]; @@ -32,5 +35,5 @@ bool ack = false; - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_write","write[%d] : %d",i,val); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * write [%d] : %d",i,val); if (val == true) @@ -43,7 +46,7 @@ else address = 0; - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_write"," * address : %d",address); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * address : %d",address); Taddress_t bank = address_bank (address); - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_write"," * bank : %d",bank ); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank : %d",bank ); // Search loop @@ -60,6 +63,6 @@ Taddress_t num_reg = address_num_reg (address); - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_write"," * num_reg : %d",num_reg); - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_write"," * bank_port : %d",j ); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * num_reg : %d",num_reg); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank_port : %d",j ); internal_WRITE_NUM_REG [i] = num_reg; @@ -77,5 +80,5 @@ } - log_printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_genMealy_write","End"); + log_end(RegisterFile_Multi_Banked,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_transition.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_transition.cpp (revision 106) @@ -17,9 +17,12 @@ +#undef FUNCTION +#define FUNCTION "RegisterFile_Multi_Banked::full_crossbar_genMealy_transition" void RegisterFile_Multi_Banked::full_crossbar_transition (void) { - log_printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_transition","Begin"); + log_begin(RegisterFile_Multi_Banked,FUNCTION); + log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); - log_printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_transition","End"); + log_end(RegisterFile_Multi_Banked,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_genMealy_read.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_genMealy_read.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_genMealy_read.cpp (revision 106) @@ -17,13 +17,15 @@ +#undef FUNCTION +#define FUNCTION "RegisterFile_Multi_Banked::genMealy_read" void RegisterFile_Multi_Banked::genMealy_read (void) { - log_printf(FUNC,RegisterFile_Multi_Banked,"genMealy_read","Begin"); + log_begin(RegisterFile_Multi_Banked,FUNCTION); + log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); // call function pointer (this->*function_genMealy_read) (); - - log_printf(FUNC,RegisterFile_Multi_Banked,"genMealy_read","End"); + log_end(RegisterFile_Multi_Banked,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_genMealy_write.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_genMealy_write.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_genMealy_write.cpp (revision 106) @@ -17,12 +17,15 @@ +#undef FUNCTION +#define FUNCTION "RegisterFile_Multi_Banked::genMealy_write" void RegisterFile_Multi_Banked::genMealy_write (void) { - log_printf(FUNC,RegisterFile_Multi_Banked,"genMealy_write","Begin"); + log_begin(RegisterFile_Multi_Banked,FUNCTION); + log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); // call function pointer (this->*function_genMealy_write) (); - log_printf(FUNC,RegisterFile_Multi_Banked,"genMealy_write","End"); + log_end(RegisterFile_Multi_Banked,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_read.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_read.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_read.cpp (revision 106) @@ -17,7 +17,10 @@ +#undef FUNCTION +#define FUNCTION "RegisterFile_Multi_Banked::partial_crossbar_genMealy_read" void RegisterFile_Multi_Banked::partial_crossbar_genMealy_read (void) { - log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_read","Begin"); + log_begin(RegisterFile_Multi_Banked,FUNCTION); + log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); bool read_port_use [_param->_nb_bank][_param->_nb_port_read_by_bank]; @@ -32,5 +35,5 @@ bool ack = false; - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read","read[%d] : %d",i,val); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * read [%d] : %d",i,val); if (val == true) @@ -42,7 +45,7 @@ else address = 0; - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read"," * address : %d",address); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * address : %d",address); Taddress_t bank = address_bank (address); - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read"," * bank : %d",bank ); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank : %d",bank ); // // Search loop @@ -61,10 +64,10 @@ Taddress_t num_reg = address_num_reg (address); - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read"," * num_reg : %d",num_reg); - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read"," * bank_port : %d",j); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * num_reg : %d",num_reg); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank_port : %d",j); Tdata_t data = reg_DATA[bank][num_reg]; - log_printf(TRACE,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read"," * data : %d",data); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * data : %d",data); PORT_WRITE(out_READ_DATA [i], data); @@ -79,5 +82,5 @@ } - log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_read","End"); + log_end(RegisterFile_Multi_Banked,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.cpp (revision 106) @@ -17,7 +17,10 @@ +#undef FUNCTION +#define FUNCTION "RegisterFile_Multi_Banked::partial_crossbar_genMealy_write" void RegisterFile_Multi_Banked::partial_crossbar_genMealy_write (void) { - log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_write","Begin"); + log_begin(RegisterFile_Multi_Banked,FUNCTION); + log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); bool write_port_use [_param->_nb_bank][_param->_nb_port_write_by_bank]; @@ -31,5 +34,5 @@ bool ack = false; - log_printf(TRACE,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_write","write[%d] : %d",i,val); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * write [%d] : %d",i,val); if (val == true) @@ -42,7 +45,7 @@ else address = 0; - log_printf(TRACE,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_write"," * address : %d",address); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * address : %d",address); Taddress_t bank = address_bank (address); - log_printf(TRACE,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_write"," * bank : %d",bank ); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank : %d",bank ); // // Search loop @@ -61,6 +64,6 @@ Taddress_t num_reg = address_num_reg (address); - log_printf(TRACE,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_write"," * num_reg : %d",num_reg); - log_printf(TRACE,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_write"," * bank_port : %d",j ); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * num_reg : %d",num_reg); + log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank_port : %d",j ); internal_WRITE_NUM_REG [i] = num_reg; @@ -79,5 +82,5 @@ } - log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_write","End"); + log_end(RegisterFile_Multi_Banked,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_transition.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_transition.cpp (revision 106) @@ -17,9 +17,12 @@ +#undef FUNCTION +#define FUNCTION "RegisterFile_Multi_Banked::partial_crossbar_transition" void RegisterFile_Multi_Banked::partial_crossbar_transition (void) { - log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_transition","Begin"); + log_begin(RegisterFile_Multi_Banked,FUNCTION); + log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); - log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_transition","End"); + log_end(RegisterFile_Multi_Banked,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_transition.cpp (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_transition.cpp (revision 106) @@ -16,8 +16,10 @@ namespace registerfile_multi_banked { - +#undef FUNCTION +#define FUNCTION "RegisterFile_Multi_Banked::transition" void RegisterFile_Multi_Banked::transition (void) { - log_printf(FUNC,RegisterFile_Multi_Banked,"transition","Begin"); + log_begin(RegisterFile_Multi_Banked,FUNCTION); + log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); // call function pointer @@ -35,9 +37,39 @@ } +#if defined(DEBUG_RegisterFile_Multi_Banked) and DEBUG_RegisterFile_Multi_Banked and (DEBUG >= DEBUG_TRACE) + { + log_printf(TRACE,RegisterFile,FUNCTION," * Dump RegisterFile"); + + uint32_t limit = 4; + + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + + log_printf(TRACE,RegisterFile,FUNCTION," Bank %d",i); + + for (uint32_t j=0; j<_param->_nb_word_by_bank; j+=limit) + { + std::string str = ""; + + for (uint32_t k=0; k= _param->_nb_word) + break; + else + str+=toString("[%.4d] %.8x ",index,reg_DATA[i][index]); + } + + log_printf(TRACE,RegisterFile,FUNCTION," %s",str.c_str()); + } + } + } +#endif + #if defined(STATISTICS) or defined(VHDL_TESTBENCH) end_cycle(); #endif - log_printf(FUNC,RegisterFile_Multi_Banked,"transition","End"); + log_end(RegisterFile_Multi_Banked,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 106) @@ -10,8 +10,8 @@ #define MORPHEO_MAJOR_VERSION 0 #define MORPHEO_MINOR_VERSION 2 -#define MORPHEO_REVISION "105" +#define MORPHEO_REVISION "106" #define MORPHEO_CODENAME "Castor" -#define MORPHEO_DATE_DAY "05" +#define MORPHEO_DATE_DAY "09" #define MORPHEO_DATE_MONTH "02" #define MORPHEO_DATE_YEAR "2009" Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg (revision 106) @@ -76,9 +76,9 @@ - + - - + + Index: trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 105) +++ trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 106) @@ -15,5 +15,5 @@ - + @@ -24,6 +24,6 @@ - - + +