Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h	(revision 108)
@@ -33,4 +33,6 @@
       CONTEXT_STATE_KO_MISS_LOAD_ADDR     , // update address manager
       CONTEXT_STATE_KO_MISS_LOAD_WAITEND  , // wait end of event (miss load))
+      CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR   , // update address manager
+      CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND, // wait end of event (miss branch)
 //    CONTEXT_STATE_KO_MSYNC              , // wait completion of all memory operation
 //    CONTEXT_STATE_KO_MSYNC_ISSUE        , // issue msync operation
@@ -64,4 +66,6 @@
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_ADDR    : return "context_state_ko_miss_branch_addr"   ; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : return "context_state_ko_miss_branch_waitend"; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR    : return "context_state_ko_miss_branch_and_load_addr"   ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND : return "context_state_ko_miss_branch_and_load_waitend"; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_ADDR      : return "context_state_ko_miss_load_addr"     ; break;
       case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_WAITEND   : return "context_state_ko_miss_load_waitend"  ; break;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp	(revision 108)
@@ -33,4 +33,5 @@
         Tcontrol_t val              = ((state == CONTEXT_STATE_KO_EXCEP_ADDR      ) or
                                        (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR) or
                                        (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR  ) or
                                        (state == CONTEXT_STATE_KO_PSYNC_ADDR      ) or 
@@ -53,4 +54,5 @@
           {
           case CONTEXT_STATE_KO_EXCEP_ADDR      : (type = EVENT_TYPE_EXCEPTION              ); break;
+          case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR: 
           case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: (type = EVENT_TYPE_BRANCH_MISS_SPECULATION); break;
           case CONTEXT_STATE_KO_MISS_LOAD_ADDR  : (type = EVENT_TYPE_LOAD_MISS_SPECULATION  ); break;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp	(revision 108)
@@ -82,4 +82,13 @@
                   break;
                 }
+              case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND :
+                {
+                  // Wait end of all instruction
+                  if (inst_all == 0)
+                    
+//                  state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
+                    state = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR;
+                  break;
+                }
               case CONTEXT_STATE_KO_EXCEP_SPR    :
                 {
@@ -93,4 +102,9 @@
                 }
               case CONTEXT_STATE_KO_MISS_LOAD_ADDR    :
+                {
+                  // nothing, wait the update of internal register (pc)
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR    :
                 {
                   // nothing, wait the update of internal register (pc)
@@ -209,8 +223,10 @@
 
               // priority : miss > excep > spr/sync
-              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR   ) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR     ) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND  ))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
+              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR            ) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR              ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR   ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND         ) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND           ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
               uint8_t    priority1  = 2; // miss
 
@@ -272,8 +288,10 @@
               
               // miss > excep > spr/sync
-              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR   ) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR     ) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND  ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR            ) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR              ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR   ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND         ) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND           ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
               uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?1:0;
 
@@ -405,8 +423,10 @@
             
             // miss > excep > spr/sync
-            uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR   ) or
-                                     (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR     ) or
-                                     (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or
-                                     (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND  ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR            ) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR              ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR   ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND         ) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND           ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
             uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION)
 
@@ -437,5 +457,16 @@
                   {
                   case EVENT_TYPE_EXCEPTION               : {state_next = CONTEXT_STATE_KO_EXCEP;             break;}
-                  case EVENT_TYPE_LOAD_MISS_SPECULATION   : {state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; break;}
+                  case EVENT_TYPE_LOAD_MISS_SPECULATION   : 
+                    {
+                      // Test if previous branch occure
+                      if ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR            ) or
+                          (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND         ) or
+                          (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR   ) or
+                          (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))
+                        state_next = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND;
+                      else
+                        state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND;
+                      break;
+                    }
                   case EVENT_TYPE_BRANCH_MISS_SPECULATION :
                   case EVENT_TYPE_SPR_ACCESS              :
@@ -480,4 +511,5 @@
                   }
                 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR:
+
 //                   {
 //                     reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
@@ -489,4 +521,9 @@
                   {
                     reg_STATE [i] = CONTEXT_STATE_OK;
+                    break;
+                  }
+                case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR:
+                  {
+                    reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
                     break;
                   }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp	(revision 108)
@@ -71,4 +71,7 @@
   ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE                   ,"out_DECOD_NO_EXECUTE                   ",Tcontrol_t         ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT                ,"out_DECOD_IS_DELAY_SLOT                ",Tcontrol_t         ,_param->_nb_inst_decod);
+#ifdef DEBUG
+  ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS                      ,"out_DECOD_ADDRESS                      ",Tgeneral_data_t    ,_param->_nb_inst_decod);
+#endif
   ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT                 ,"out_DECOD_ADDRESS_NEXT                 ",Tgeneral_data_t    ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT                 ,"out_DECOD_HAS_IMMEDIAT                 ",Tcontrol_t         ,_param->_nb_inst_decod);
@@ -148,4 +151,7 @@
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE                   ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT                ,_param->_nb_inst_decod);
+#ifdef DEBUG
+  INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS                      ,_param->_nb_inst_decod);
+#endif
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS_NEXT                 ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_HAS_IMMEDIAT                 ,_param->_nb_inst_decod);
@@ -450,4 +456,7 @@
   delete [] out_DECOD_NO_EXECUTE                   ;
   delete [] out_DECOD_IS_DELAY_SLOT                ;
+#ifdef DEBUG
+  delete [] out_DECOD_ADDRESS                      ;
+#endif
   delete [] out_DECOD_ADDRESS_NEXT                 ;
   delete [] out_DECOD_HAS_IMMEDIAT                 ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h	(revision 108)
@@ -88,4 +88,7 @@
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_NO_EXECUTE                   ;//[nb_inst_decod]
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_IS_DELAY_SLOT                ;//[nb_inst_decod]
+#ifdef DEBUG
+  public    : SC_OUT(Tgeneral_data_t    )  ** out_DECOD_ADDRESS                      ;//[nb_inst_decod]
+#endif
   public    : SC_OUT(Tgeneral_data_t    )  ** out_DECOD_ADDRESS_NEXT                 ;//[nb_inst_decod]
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_HAS_IMMEDIAT                 ;//[nb_inst_decod]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp	(revision 108)
@@ -89,4 +89,7 @@
       ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE   ,"no_execute"   ,Tcontrol_t        ,1                                   );
       ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t        ,1                                   );
+#ifdef DEBUG
+      ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS      ,"address"      ,Tgeneral_data_t   ,_param->_size_instruction_address   );
+#endif
       ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t   ,_param->_size_instruction_address   );
       ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t        ,1                                   );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp	(revision 108)
@@ -49,4 +49,7 @@
         DELETE1_SIGNAL(out_DECOD_NO_EXECUTE   ,_param->_nb_inst_decod,1                                   );
         DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT,_param->_nb_inst_decod,1                                   );
+#ifdef DEBUG
+        DELETE1_SIGNAL(out_DECOD_ADDRESS      ,_param->_nb_inst_decod,_param->_size_instruction_address   );
+#endif
         DELETE1_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod,_param->_size_instruction_address   );
         DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod,1                                   );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp	(revision 108)
@@ -43,5 +43,6 @@
 
     Tcontrol_t can_continue      [_param->_nb_context];
-    Tcontrol_t can_continue_next [_param->_nb_context];    
+//     Tcontrol_t can_continue_next [_param->_nb_context];
+//     Tcontrol_t have_decod_branch [_param->_nb_context];
 
     for (uint32_t i=0; i<_param->_nb_context; i++)
@@ -52,5 +53,6 @@
 	
 	can_continue                      [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]);
-	can_continue_next                 [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]);
+//  	can_continue_next                 [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]);
+//         have_decod_branch                 [i] = false;
       }
     
@@ -79,5 +81,5 @@
                 log_printf(TRACE,Decod,FUNCTION,"    * decod_ack [%d] : %d",i,PORT_READ(in_DECOD_ACK [i]));
 
-		can_continue [x] = can_continue_next [x];
+//  		can_continue [x] = can_continue_next [x];
 
 		decod_val  [i]    = true;                        // fetch_val and decod_enable 
@@ -139,5 +141,7 @@
  		PORT_WRITE(out_DECOD_NO_EXECUTE    [i], _decod_instruction->_no_execute    );
 		PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot );
-// 		PORT_WRITE(out_DECOD_ADDRESS       [i], addr);
+#ifdef DEBUG
+ 		PORT_WRITE(out_DECOD_ADDRESS       [i], addr);
+#endif
 //                 if ((type == TYPE_BRANCH) and
 //                     ((_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_SET) or
@@ -193,5 +197,7 @@
 		
 		    //can_continue_next [x] = PORT_READ(in_PREDICT_CAN_CONTINUE [i]); // can continue is set if direction is "not take" (also, continue is sequential order)
-		    can_continue_next [x] = false; // one branch per context, the DS don't execute
+ 		    can_continue [x] = false; // one branch per context, the DS don't execute
+//  		    can_continue_next [x] = false; // one branch per context, the DS don't execute
+//                     have_decod_branch [x] = true;
 		  }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp	(revision 108)
@@ -60,4 +60,7 @@
   ALLOC1_SC_SIGNAL( in_DECOD_IN_NO_EXECUTE     ," in_DECOD_IN_NO_EXECUTE    ",Tcontrol_t         ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT  ," in_DECOD_IN_IS_DELAY_SLOT ",Tcontrol_t         ,_param->_nb_inst_decod);
+#ifdef DEBUG
+  ALLOC1_SC_SIGNAL( in_DECOD_IN_ADDRESS        ," in_DECOD_IN_ADDRESS       ",Tgeneral_data_t    ,_param->_nb_inst_decod);
+#endif
   ALLOC1_SC_SIGNAL( in_DECOD_IN_ADDRESS_NEXT   ," in_DECOD_IN_ADDRESS_NEXT  ",Tgeneral_data_t    ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL( in_DECOD_IN_HAS_IMMEDIAT   ," in_DECOD_IN_HAS_IMMEDIAT  ",Tcontrol_t         ,_param->_nb_inst_decod);
@@ -84,4 +87,7 @@
   ALLOC1_SC_SIGNAL(out_DECOD_OUT_NO_EXECUTE    ,"out_DECOD_OUT_NO_EXECUTE   ",Tcontrol_t         ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,"out_DECOD_OUT_IS_DELAY_SLOT",Tcontrol_t         ,_param->_nb_inst_decod);
+#ifdef DEBUG
+  ALLOC1_SC_SIGNAL(out_DECOD_OUT_ADDRESS       ,"out_DECOD_OUT_ADDRESS      ",Tgeneral_data_t    ,_param->_nb_inst_decod);
+#endif
   ALLOC1_SC_SIGNAL(out_DECOD_OUT_ADDRESS_NEXT  ,"out_DECOD_OUT_ADDRESS_NEXT ",Tgeneral_data_t    ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_OUT_HAS_IMMEDIAT  ,"out_DECOD_OUT_HAS_IMMEDIAT ",Tcontrol_t         ,_param->_nb_inst_decod);
@@ -125,4 +131,7 @@
   INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_NO_EXECUTE     ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_IS_DELAY_SLOT  ,_param->_nb_inst_decod);
+#ifdef DEBUG
+  INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_ADDRESS        ,_param->_nb_inst_decod);
+#endif
   INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_ADDRESS_NEXT   ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_HAS_IMMEDIAT   ,_param->_nb_inst_decod);
@@ -151,4 +160,7 @@
   INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_NO_EXECUTE    ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod);
+#ifdef DEBUG
+  INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_ADDRESS       ,_param->_nb_inst_decod);
+#endif
   INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_ADDRESS_NEXT  ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_HAS_IMMEDIAT  ,_param->_nb_inst_decod);
@@ -304,4 +316,7 @@
   DELETE1_SC_SIGNAL( in_DECOD_IN_NO_EXECUTE     ,_param->_nb_inst_decod);
   DELETE1_SC_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT  ,_param->_nb_inst_decod);
+#ifdef DEBUG
+  DELETE1_SC_SIGNAL( in_DECOD_IN_ADDRESS        ,_param->_nb_inst_decod);
+#endif
   DELETE1_SC_SIGNAL( in_DECOD_IN_ADDRESS_NEXT   ,_param->_nb_inst_decod);
   DELETE1_SC_SIGNAL( in_DECOD_IN_HAS_IMMEDIAT   ,_param->_nb_inst_decod);
@@ -328,4 +343,7 @@
   DELETE1_SC_SIGNAL(out_DECOD_OUT_NO_EXECUTE    ,_param->_nb_inst_decod);
   DELETE1_SC_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod);
+#ifdef DEBUG
+  DELETE1_SC_SIGNAL(out_DECOD_OUT_ADDRESS       ,_param->_nb_inst_decod);
+#endif
   DELETE1_SC_SIGNAL(out_DECOD_OUT_ADDRESS_NEXT  ,_param->_nb_inst_decod);
   DELETE1_SC_SIGNAL(out_DECOD_OUT_HAS_IMMEDIAT  ,_param->_nb_inst_decod);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h	(revision 108)
@@ -75,4 +75,7 @@
   public    : SC_IN (Tcontrol_t         )  **  in_DECOD_IN_NO_EXECUTE     ;//[nb_inst_decod]
   public    : SC_IN (Tcontrol_t         )  **  in_DECOD_IN_IS_DELAY_SLOT  ;//[nb_inst_decod]
+#ifdef DEBUG
+  public    : SC_IN (Tgeneral_data_t    )  **  in_DECOD_IN_ADDRESS        ;//[nb_inst_decod]
+#endif
   public    : SC_IN (Tgeneral_data_t    )  **  in_DECOD_IN_ADDRESS_NEXT   ;//[nb_inst_decod]
   public    : SC_IN (Tcontrol_t         )  **  in_DECOD_IN_HAS_IMMEDIAT   ;//[nb_inst_decod]
@@ -100,4 +103,7 @@
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_OUT_NO_EXECUTE    ;//[nb_inst_decod]
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_OUT_IS_DELAY_SLOT ;//[nb_inst_decod]
+#ifdef DEBUG
+  public    : SC_OUT(Tgeneral_data_t    )  ** out_DECOD_OUT_ADDRESS       ;//[nb_inst_decod]
+#endif
   public    : SC_OUT(Tgeneral_data_t    )  ** out_DECOD_OUT_ADDRESS_NEXT  ;//[nb_inst_decod]
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_OUT_HAS_IMMEDIAT  ;//[nb_inst_decod]
@@ -129,5 +135,6 @@
   private   : std::list<decod_queue_entry_t*>* reg_QUEUE                  ;
   private   : uint32_t                       * reg_NB_INST                ;//[nb_context]
-    
+  private   : uint32_t                         reg_LAST_SLOT              ;
+
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   private   : Tcontrol_t                     * internal_DECOD_IN_ACK      ;//[nb_inst_decod]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h	(revision 108)
@@ -30,4 +30,7 @@
   public : Tcontrol_t         * _no_execute     ;
   public : Tcontrol_t         * _is_delay_slot  ;
+#ifdef DEBUG
+  public : Tgeneral_data_t    * _address        ;
+#endif
   public : Tgeneral_data_t    * _address_next   ;
   public : Tcontrol_t         * _has_immediat   ;
@@ -56,4 +59,7 @@
       _no_execute     = new Tcontrol_t         [_nb_inst];
       _is_delay_slot  = new Tcontrol_t         [_nb_inst];
+#ifdef DEBUG
+      _address        = new Tgeneral_data_t    [_nb_inst];
+#endif
       _address_next   = new Tgeneral_data_t    [_nb_inst];
       _has_immediat   = new Tcontrol_t         [_nb_inst];
@@ -85,4 +91,7 @@
       delete [] _no_execute     ;
       delete [] _is_delay_slot  ;
+#ifdef DEBUG
+      delete [] _address        ;
+#endif
       delete [] _address_next   ;
       delete [] _has_immediat   ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp	(revision 108)
@@ -67,4 +67,7 @@
       ALLOC1_SIGNAL_IN ( in_DECOD_IN_NO_EXECUTE     ,"no_execute"   ,Tcontrol_t         ,1                                   );
       ALLOC1_SIGNAL_IN ( in_DECOD_IN_IS_DELAY_SLOT  ,"is_delay_slot",Tcontrol_t         ,1                                   );
+#ifdef DEBUG
+      ALLOC1_SIGNAL_IN ( in_DECOD_IN_ADDRESS        ,"address"      ,Tgeneral_data_t    ,_param->_size_instruction_address   );
+#endif
       ALLOC1_SIGNAL_IN ( in_DECOD_IN_ADDRESS_NEXT   ,"address_next" ,Tgeneral_data_t    ,_param->_size_instruction_address   );
       ALLOC1_SIGNAL_IN ( in_DECOD_IN_HAS_IMMEDIAT   ,"has_immediat" ,Tcontrol_t         ,1                                   );
@@ -96,4 +99,7 @@
       ALLOC1_SIGNAL_OUT(out_DECOD_OUT_NO_EXECUTE     ,"no_execute"   ,Tcontrol_t         ,1                                   );
       ALLOC1_SIGNAL_OUT(out_DECOD_OUT_IS_DELAY_SLOT  ,"is_delay_slot",Tcontrol_t         ,1                                   );
+#ifdef DEBUG
+      ALLOC1_SIGNAL_OUT(out_DECOD_OUT_ADDRESS        ,"address"      ,Tgeneral_data_t    ,_param->_size_instruction_address   );
+#endif
       ALLOC1_SIGNAL_OUT(out_DECOD_OUT_ADDRESS_NEXT   ,"address_next" ,Tgeneral_data_t    ,_param->_size_instruction_address   );
       ALLOC1_SIGNAL_OUT(out_DECOD_OUT_HAS_IMMEDIAT   ,"has_immediat" ,Tcontrol_t         ,1                                   );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp	(revision 108)
@@ -37,4 +37,7 @@
 	DELETE1_SIGNAL( in_DECOD_IN_NO_EXECUTE     ,_param->_nb_inst_decod,1                                   );
 	DELETE1_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT  ,_param->_nb_inst_decod,1                                   );
+#ifdef DEBUG
+	DELETE1_SIGNAL( in_DECOD_IN_ADDRESS        ,_param->_nb_inst_decod,_param->_size_instruction_address   );
+#endif
 	DELETE1_SIGNAL( in_DECOD_IN_ADDRESS_NEXT   ,_param->_nb_inst_decod,_param->_size_instruction_address   );
 	DELETE1_SIGNAL( in_DECOD_IN_HAS_IMMEDIAT   ,_param->_nb_inst_decod,1                                   );
@@ -61,4 +64,7 @@
 	DELETE1_SIGNAL(out_DECOD_OUT_NO_EXECUTE    ,_param->_nb_inst_decod,1                                   );
 	DELETE1_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod,1                                   );
+#ifdef DEBUG
+	DELETE1_SIGNAL(out_DECOD_OUT_ADDRESS       ,_param->_nb_inst_decod,_param->_size_instruction_address   );
+#endif
 	DELETE1_SIGNAL(out_DECOD_OUT_ADDRESS_NEXT  ,_param->_nb_inst_decod,_param->_size_instruction_address   );
 	DELETE1_SIGNAL(out_DECOD_OUT_HAS_IMMEDIAT  ,_param->_nb_inst_decod,1                                   );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp	(revision 108)
@@ -35,64 +35,75 @@
     if (not reg_QUEUE->empty())
       for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
-	if (reg_QUEUE->front()->_val [i])
-	  {
-	    log_printf(TRACE,Decod_queue,FUNCTION,_("  * Queue is not empty, slot [%d] is valid."),i);
+        {
+          uint32_t index = reg_LAST_SLOT + i;
 
-	    Tcontext_t context         = reg_QUEUE->front()->_context_id    [i];
-	    Tdepth_t   depth           = reg_QUEUE->front()->_depth         [i];
-	    Tdepth_t   depth_min       = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context]):0;
-	    Tdepth_t   depth_max       = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX [context]):0;
-	    Tcontrol_t depth_full      = PORT_READ(in_DEPTH_FULL[context]);
+          // Stop
+          if (index >= _param->_nb_inst_decod)
+            break;
 
-	    // is a valid instruction ?
-            // If DEPTH_CURRENT :
-            // equal at     DEPTH_MIN            -> not speculative
-            // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
-            //     include ]DEPTH_MIN:DEPTH_MAX] -> speculative
+          if (reg_QUEUE->front()->_val [index])
+            {
+              log_printf(TRACE,Decod_queue,FUNCTION,_("  * Queue is not empty, slot [%d] is valid."),i);
+              
+              Tcontext_t context         = reg_QUEUE->front()->_context_id    [index];
+              Tdepth_t   depth           = reg_QUEUE->front()->_depth         [index];
+              Tdepth_t   depth_min       = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context]):0;
+              Tdepth_t   depth_max       = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX [context]):0;
+              Tcontrol_t depth_full      = PORT_READ(in_DEPTH_FULL[context]);
 
-            // All case
-            // ....... min ...X... max ....... OK
-            // ....... min ....... max ...X... KO
-            // ...X... min ....... max ....... KO
-            // ....... max ....... min ...X... OK
-            // ...X... max ....... min ....... OK
-            // ....... max ...X... min ....... KO
+              // is a valid instruction ?
+              // If DEPTH_CURRENT :
+              // equal at     DEPTH_MIN            -> not speculative
+              // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
+              //     include ]DEPTH_MIN:DEPTH_MAX] -> speculative
+              
+              // All case
+              // ....... min ...X... max ....... OK
+              // ....... min ....... max ...X... KO
+              // ...X... min ....... max ....... KO
+              // ....... max ....... min ...X... OK
+              // ...X... max ....... min ....... OK
+              // ....... max ...X... min ....... KO
+              
+              Tcontrol_t   is_valid      = ((depth == depth_min) or
+                                            depth_full or
+                                            ((depth_min <= depth_max)?
+                                             ((depth >= depth_min) and (depth <=depth_max)):
+                                             ((depth >= depth_min) or  (depth <=depth_max))));
+              //Tcontrol_t is_valid        = ((depth == depth_min) or 
+              //                              ((depth_min < depth_max)?
+              //                               (depth<=depth_max):
+              //                               ((depth > depth_min) or (depth <= depth_max))));
+              //Tcontrol_t is_valid        = depth <= depth_max;
 
-            Tcontrol_t   is_valid      = ((depth == depth_min) or
-                                          depth_full or
-                                          ((depth_min <= depth_max)?
-                                           ((depth >= depth_min) and (depth <=depth_max)):
-                                           ((depth >= depth_min) or  (depth <=depth_max))));
-//    	    Tcontrol_t is_valid        = ((depth == depth_min) or 
-//                                           ((depth_min < depth_max)?
-//                                            (depth<=depth_max):
-//                                            ((depth > depth_min) or (depth <= depth_max))));
-//          Tcontrol_t is_valid        = depth <= depth_max;
-
-	    log_printf(TRACE,Decod_queue,FUNCTION,"    * is_valid : %d",is_valid);
-	    log_printf(TRACE,Decod_queue,FUNCTION,"      * context      : %d",context);
-            log_printf(TRACE,Decod_queue,FUNCTION,"      * depth        : %d",depth);
-            log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_min    : %d",depth_min);
-            log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_max    : %d",depth_max);
-            log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_full   : %d",depth_full);
-            log_printf(TRACE,Decod_queue,FUNCTION,"      * address_next : 0x%x (0x%x)",reg_QUEUE->front()->_address_next[i],reg_QUEUE->front()->_address_next[i]<<2);
-	    internal_DECOD_OUT_VAL [i] = 1; // in all case, val is set (entry is not empty, and instruction is valid)
-	    if (is_valid)
-	      {
-		val                    [i] = 1;
-		internal_DECOD_OUT_ACK [i] = PORT_READ(in_DECOD_OUT_ACK [i]);
-	      }
-	    else
-	      {
-		// Consume the instruction (to erase)
-		internal_DECOD_OUT_ACK [i] = 1;
-	      }
-	  }
+              log_printf(TRACE,Decod_queue,FUNCTION,"    * is_valid : %d",is_valid);
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * context      : %d",context);
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * depth        : %d",depth);
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_min    : %d",depth_min);
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_max    : %d",depth_max);
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * depth_full   : %d",depth_full);
+#ifdef DEBUG
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * address      : 0x%x (0x%x)",reg_QUEUE->front()->_address     [index],reg_QUEUE->front()->_address     [index]<<2);
+#endif
+              log_printf(TRACE,Decod_queue,FUNCTION,"      * address_next : 0x%x (0x%x)",reg_QUEUE->front()->_address_next[index],reg_QUEUE->front()->_address_next[index]<<2);
+              internal_DECOD_OUT_VAL [index] = 1; // in all case, val is set (entry is not empty, and instruction is valid)
+              if (is_valid)
+                {
+                  val                    [i]     = 1;
+                  internal_DECOD_OUT_ACK [index] = PORT_READ(in_DECOD_OUT_ACK [i]);
+                }
+              else
+                {
+                  // Consume the instruction (to erase)
+                  internal_DECOD_OUT_ACK [index] = 1;
+                }
+            }
+      }
 
     for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
       {
         log_printf(TRACE,Decod_queue,FUNCTION,"  * DECOD_OUT_VAL : %d",val [i]);
-
-	PORT_WRITE(out_DECOD_OUT_VAL [i],val [i]);
+        
+        PORT_WRITE(out_DECOD_OUT_VAL [i],val [i]);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp	(revision 108)
@@ -44,27 +44,36 @@
       for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
 	{
+          uint32_t index = reg_LAST_SLOT + i;
+
+          // Stop
+          if (index >= _param->_nb_inst_decod)
+            break;
+
 	  if (_param->_have_port_context_id)
-	  PORT_WRITE(out_DECOD_OUT_CONTEXT_ID    [i],reg_QUEUE->front()->_context_id    [i]);
+	  PORT_WRITE(out_DECOD_OUT_CONTEXT_ID    [i],reg_QUEUE->front()->_context_id    [index]);
 	  if (_param->_have_port_depth)
-	  PORT_WRITE(out_DECOD_OUT_DEPTH         [i],reg_QUEUE->front()->_depth         [i]);
-	  PORT_WRITE(out_DECOD_OUT_TYPE          [i],reg_QUEUE->front()->_type          [i]);
-	  PORT_WRITE(out_DECOD_OUT_OPERATION     [i],reg_QUEUE->front()->_operation     [i]);
-	  PORT_WRITE(out_DECOD_OUT_NO_EXECUTE    [i],reg_QUEUE->front()->_no_execute    [i]);
-	  PORT_WRITE(out_DECOD_OUT_IS_DELAY_SLOT [i],reg_QUEUE->front()->_is_delay_slot [i]);
-	  PORT_WRITE(out_DECOD_OUT_ADDRESS_NEXT  [i],reg_QUEUE->front()->_address_next  [i]);
-	  PORT_WRITE(out_DECOD_OUT_HAS_IMMEDIAT  [i],reg_QUEUE->front()->_has_immediat  [i]);
-	  PORT_WRITE(out_DECOD_OUT_IMMEDIAT      [i],reg_QUEUE->front()->_immediat      [i]);
-	  PORT_WRITE(out_DECOD_OUT_READ_RA       [i],reg_QUEUE->front()->_read_ra       [i]);
-	  PORT_WRITE(out_DECOD_OUT_NUM_REG_RA    [i],reg_QUEUE->front()->_num_reg_ra    [i]);
-	  PORT_WRITE(out_DECOD_OUT_READ_RB       [i],reg_QUEUE->front()->_read_rb       [i]);
-	  PORT_WRITE(out_DECOD_OUT_NUM_REG_RB    [i],reg_QUEUE->front()->_num_reg_rb    [i]);
-	  PORT_WRITE(out_DECOD_OUT_READ_RC       [i],reg_QUEUE->front()->_read_rc       [i]);
-	  PORT_WRITE(out_DECOD_OUT_NUM_REG_RC    [i],reg_QUEUE->front()->_num_reg_rc    [i]);
-	  PORT_WRITE(out_DECOD_OUT_WRITE_RD      [i],reg_QUEUE->front()->_write_rd      [i]);
-	  PORT_WRITE(out_DECOD_OUT_NUM_REG_RD    [i],reg_QUEUE->front()->_num_reg_rd    [i]);
-	  PORT_WRITE(out_DECOD_OUT_WRITE_RE      [i],reg_QUEUE->front()->_write_re      [i]);
-	  PORT_WRITE(out_DECOD_OUT_NUM_REG_RE    [i],reg_QUEUE->front()->_num_reg_re    [i]);
-	  PORT_WRITE(out_DECOD_OUT_EXCEPTION_USE [i],reg_QUEUE->front()->_exception_use [i]);
-	  PORT_WRITE(out_DECOD_OUT_EXCEPTION     [i],reg_QUEUE->front()->_exception     [i]);
+	  PORT_WRITE(out_DECOD_OUT_DEPTH         [i],reg_QUEUE->front()->_depth         [index]);
+	  PORT_WRITE(out_DECOD_OUT_TYPE          [i],reg_QUEUE->front()->_type          [index]);
+	  PORT_WRITE(out_DECOD_OUT_OPERATION     [i],reg_QUEUE->front()->_operation     [index]);
+	  PORT_WRITE(out_DECOD_OUT_NO_EXECUTE    [i],reg_QUEUE->front()->_no_execute    [index]);
+	  PORT_WRITE(out_DECOD_OUT_IS_DELAY_SLOT [i],reg_QUEUE->front()->_is_delay_slot [index]);
+#ifdef DEBUG
+	  PORT_WRITE(out_DECOD_OUT_ADDRESS       [i],reg_QUEUE->front()->_address       [index]);
+#endif
+	  PORT_WRITE(out_DECOD_OUT_ADDRESS_NEXT  [i],reg_QUEUE->front()->_address_next  [index]);
+	  PORT_WRITE(out_DECOD_OUT_HAS_IMMEDIAT  [i],reg_QUEUE->front()->_has_immediat  [index]);
+	  PORT_WRITE(out_DECOD_OUT_IMMEDIAT      [i],reg_QUEUE->front()->_immediat      [index]);
+	  PORT_WRITE(out_DECOD_OUT_READ_RA       [i],reg_QUEUE->front()->_read_ra       [index]);
+	  PORT_WRITE(out_DECOD_OUT_NUM_REG_RA    [i],reg_QUEUE->front()->_num_reg_ra    [index]);
+	  PORT_WRITE(out_DECOD_OUT_READ_RB       [i],reg_QUEUE->front()->_read_rb       [index]);
+	  PORT_WRITE(out_DECOD_OUT_NUM_REG_RB    [i],reg_QUEUE->front()->_num_reg_rb    [index]);
+	  PORT_WRITE(out_DECOD_OUT_READ_RC       [i],reg_QUEUE->front()->_read_rc       [index]);
+	  PORT_WRITE(out_DECOD_OUT_NUM_REG_RC    [i],reg_QUEUE->front()->_num_reg_rc    [index]);
+	  PORT_WRITE(out_DECOD_OUT_WRITE_RD      [i],reg_QUEUE->front()->_write_rd      [index]);
+	  PORT_WRITE(out_DECOD_OUT_NUM_REG_RD    [i],reg_QUEUE->front()->_num_reg_rd    [index]);
+	  PORT_WRITE(out_DECOD_OUT_WRITE_RE      [i],reg_QUEUE->front()->_write_re      [index]);
+	  PORT_WRITE(out_DECOD_OUT_NUM_REG_RE    [i],reg_QUEUE->front()->_num_reg_re    [index]);
+	  PORT_WRITE(out_DECOD_OUT_EXCEPTION_USE [i],reg_QUEUE->front()->_exception_use [index]);
+	  PORT_WRITE(out_DECOD_OUT_EXCEPTION     [i],reg_QUEUE->front()->_exception     [index]);
 	}
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp	(revision 108)
@@ -31,4 +31,6 @@
 	for (uint32_t i=0; i<_param->_nb_context; i++)
 	  reg_NB_INST [i]=0;
+
+        reg_LAST_SLOT = 0;
       }
     else
@@ -62,4 +64,7 @@
 		entry->_no_execute    [i] = PORT_READ(in_DECOD_IN_NO_EXECUTE    [i]);
 		entry->_is_delay_slot [i] = PORT_READ(in_DECOD_IN_IS_DELAY_SLOT [i]);
+#ifdef DEBUG
+		entry->_address       [i] = PORT_READ(in_DECOD_IN_ADDRESS       [i]);
+#endif
 		entry->_address_next  [i] = PORT_READ(in_DECOD_IN_ADDRESS_NEXT  [i]);
 		entry->_has_immediat  [i] = PORT_READ(in_DECOD_IN_HAS_IMMEDIAT  [i]);
@@ -90,13 +95,20 @@
 	if (not reg_QUEUE->empty())
 	  {
-	    bool find = false;
+ 	    bool find = false;
 	    
 	    for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
 	      {
 		// Test transaction : if ok then invalid slot
+                // In order by rename logic
 		if (internal_DECOD_OUT_VAL [i] and internal_DECOD_OUT_ACK[i])
 		  {
 		    log_printf(TRACE,Decod_queue,FUNCTION,_("  * DECOD_OUT [%d]"),i);
 		
+#ifdef DEBUG_TEST
+                    if (reg_LAST_SLOT != i)
+                      throw ERRORMORPHEO(FUNCTION,toString(_("reg_LAST_SLOT (%d) is different at decod_out port (%d)."),reg_LAST_SLOT,i));
+#endif
+                    reg_LAST_SLOT ++;
+
 		    reg_QUEUE->front()->_val [i] = 0;
 
@@ -108,9 +120,9 @@
 		  }
 		// Test if slot is (again) valid, if yes, then have less one instruction in the entry
-		find |= reg_QUEUE->front()->_val [i];
+ 		find |= reg_QUEUE->front()->_val [i];
 	      }
 	    
-	    // test if can free the entry
-	    if (not find) // no valid instruction in current slot
+	    // test if can free the entry : test if have consume all entry
+            if (not find) // no valid instruction in current slot
 	      {
 		log_printf(TRACE,Decod_queue,FUNCTION,_("    * POP  queue"));
@@ -119,4 +131,6 @@
 		delete reg_QUEUE->front();
 		reg_QUEUE->pop_front();
+
+                reg_LAST_SLOT = 0;
 	      }
 	  }
@@ -125,4 +139,5 @@
 #if defined(DEBUG) and defined(DEBUG_Decod_queue) and (DEBUG >= DEBUG_TRACE)
     log_printf(TRACE,Decod_queue,FUNCTION,"  * Dump decod_queue");
+    log_printf(TRACE,Decod_queue,FUNCTION,"    * reg_LAST_SLOT : %d",reg_LAST_SLOT);
     uint32_t x=0;
     for (std::list<decod_queue_entry_t*>::iterator it=reg_QUEUE->begin();
@@ -144,6 +159,6 @@
 			 ,(*it)->_no_execute    [i]
 			 ,(*it)->_is_delay_slot [i]
-			 ,(*it)->_address_next  [i]
-			 ,(*it)->_address_next  [i]<<2
+			 ,(*it)->_address       [i]
+			 ,(*it)->_address       [i]<<2
 			 ,(*it)->_has_immediat  [i]
 			 ,(*it)->_immediat      [i]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp	(revision 108)
@@ -73,4 +73,7 @@
   ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE                   ,"out_DECOD_NO_EXECUTE                   ",Tcontrol_t         ,_param->_nb_inst_decod); 
   ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT                ,"out_DECOD_IS_DELAY_SLOT                ",Tcontrol_t         ,_param->_nb_inst_decod);
+#ifdef DEBUG
+  ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS                      ,"out_DECOD_ADDRESS                      ",Tgeneral_data_t    ,_param->_nb_inst_decod);
+#endif
   ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT                 ,"out_DECOD_ADDRESS_NEXT                 ",Tgeneral_data_t    ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT                 ,"out_DECOD_HAS_IMMEDIAT                 ",Tcontrol_t         ,_param->_nb_inst_decod);
@@ -159,4 +162,7 @@
   INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NO_EXECUTE                   ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_IS_DELAY_SLOT                ,_param->_nb_inst_decod);
+#ifdef DEBUG
+  INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_ADDRESS                      ,_param->_nb_inst_decod);
+#endif
   INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_ADDRESS_NEXT                 ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_HAS_IMMEDIAT                 ,_param->_nb_inst_decod);
@@ -490,4 +496,7 @@
   DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE                   ,_param->_nb_inst_decod);
   DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT                ,_param->_nb_inst_decod);
+#ifdef DEBUG
+  DELETE1_SC_SIGNAL(out_DECOD_ADDRESS                      ,_param->_nb_inst_decod);
+#endif
   DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT                 ,_param->_nb_inst_decod);
   DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT                 ,_param->_nb_inst_decod);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h	(revision 108)
@@ -87,4 +87,7 @@
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_NO_EXECUTE                   ;//[nb_inst_decod]
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_IS_DELAY_SLOT                ;//[nb_inst_decod]
+#ifdef DEBUG
+  public    : SC_OUT(Tgeneral_data_t    )  ** out_DECOD_ADDRESS                      ;//[nb_inst_decod]
+#endif
   public    : SC_OUT(Tgeneral_data_t    )  ** out_DECOD_ADDRESS_NEXT                 ;//[nb_inst_decod]
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_HAS_IMMEDIAT                 ;//[nb_inst_decod]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp	(revision 108)
@@ -89,4 +89,7 @@
       ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE   ,"no_execute"   ,Tcontrol_t        ,1                                   );
       ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t        ,1                                   );
+#ifdef DEBUG
+      ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS      ,"address"      ,Tgeneral_data_t   ,_param->_size_instruction_address   );
+#endif
       ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t   ,_param->_size_instruction_address   );
       ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t        ,1                                   );
@@ -293,4 +296,8 @@
 	  COMPONENT_MAP(_component,src ,"out_DECOD_"   +toString(i)+"_IS_DELAY_SLOT",
 			           dest, "in_DECOD_IN_"+toString(i)+"_IS_DELAY_SLOT");
+#ifdef DEBUG
+	  COMPONENT_MAP(_component,src ,"out_DECOD_"   +toString(i)+"_ADDRESS"      ,
+			           dest, "in_DECOD_IN_"+toString(i)+"_ADDRESS"      );
+#endif
 	  COMPONENT_MAP(_component,src ,"out_DECOD_"   +toString(i)+"_ADDRESS_NEXT" ,
 			           dest, "in_DECOD_IN_"+toString(i)+"_ADDRESS_NEXT" );
@@ -435,4 +442,5 @@
       // in_DECOD_IN_NO_EXECUTE     - component decod
       // in_DECOD_IN_IS_DELAY_SLOT  - component decod
+      // in_DECOD_IN_ADDRESS        - component decod
       // in_DECOD_IN_ADDRESS_NEXT   - component decod
       // in_DECOD_IN_HAS_IMMEDIAT   - component decod
@@ -478,4 +486,8 @@
 	  PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_IS_DELAY_SLOT",
 		              dest,"out_DECOD_"    +toString(i)+"_IS_DELAY_SLOT");
+#ifdef DEBUG
+	  PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_ADDRESS"      ,
+		              dest,"out_DECOD_"    +toString(i)+"_ADDRESS"      );
+#endif
 	  PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_ADDRESS_NEXT" ,
 		              dest,"out_DECOD_"    +toString(i)+"_ADDRESS_NEXT" );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp	(revision 108)
@@ -48,4 +48,7 @@
         DELETE1_SIGNAL(out_DECOD_NO_EXECUTE                   ,_param->_nb_inst_decod,1                                   );
         DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT                ,_param->_nb_inst_decod,1                                   );
+#ifdef DEBUG
+        DELETE1_SIGNAL(out_DECOD_ADDRESS                      ,_param->_nb_inst_decod,_param->_size_instruction_address   );
+#endif
         DELETE1_SIGNAL(out_DECOD_ADDRESS_NEXT                 ,_param->_nb_inst_decod,_param->_size_instruction_address   );
         DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT                 ,_param->_nb_inst_decod,1                                   );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_1-decod_unit_1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_1-decod_unit_1.cfg	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_1-decod_unit_1.cfg	(revision 108)
@@ -8,2 +8,3 @@
 2	2	+1	# size_depth                 [0] [nb_context]
 4	4	+1	# nb_branch_speculated       [0] [nb_context]
+4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_1.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_1.cfg	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_1.cfg	(revision 108)
@@ -17,2 +17,3 @@
 2	2	+1	# nb_branch_speculated       [2] [nb_context]
 8	8	+1	# nb_branch_speculated       [3] [nb_context]
+4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-a.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-a.cfg	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-a.cfg	(revision 108)
@@ -18,2 +18,3 @@
 2	2	+1	# nb_branch_speculated       [2] [nb_context]
 8	8	+1	# nb_branch_speculated       [3] [nb_context]
+4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-b.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-b.cfg	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-b.cfg	(revision 108)
@@ -18,2 +18,3 @@
 2	2	+1	# nb_branch_speculated       [2] [nb_context]
 8	8	+1	# nb_branch_speculated       [3] [nb_context]
+4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_4.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_4.cfg	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_4.cfg	(revision 108)
@@ -20,2 +20,3 @@
 2	2	+1	# nb_branch_speculated       [2] [nb_context]
 8	8	+1	# nb_branch_speculated       [3] [nb_context]
+4       4       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-min.cfg	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-min.cfg	(revision 108)
@@ -8,2 +8,3 @@
 0	0	+1	# size_depth                 [0] [nb_context]
 1	1	+1	# nb_branch_speculated       [0] [nb_context]
+1       1       +1      # size_nb_inst_decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/main.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/main.cpp	(revision 108)
@@ -8,5 +8,5 @@
 #include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/include/test.h"
 
-#define NB_PARAMS 4
+#define NB_PARAMS 5
 
 void usage (int argc, char * argv[])
@@ -22,4 +22,5 @@
   err (_(" * size_depth                 [nb_context]    (uint32_t)\n"));
   err (_(" * nb_branch_speculated       [nb_context]    (uint32_t)\n"));
+  err (_(" * size_nb_inst_decod                         (uint32_t)\n"));
 
   exit (1);
@@ -69,4 +70,6 @@
     _nb_branch_speculated [i] = fromString<uint32_t>(argv[x++]);
 
+  uint32_t   _size_nb_inst_decod         = fromString<uint32_t>(argv[x++]);
+
   std::vector<uint32_t> * _translate_context_id_from_decod_unit = new std::vector<uint32_t> [_nb_decod_unit];
 
@@ -87,4 +90,5 @@
          _size_depth                           ,
          _nb_branch_speculated                 ,
+         _size_nb_inst_decod                   ,
          true // is_toplevel
         );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp	(revision 108)
@@ -104,4 +104,8 @@
   ALLOC2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH_VAL                   ,"out_CONTEXT_DECOD_UNIT_DEPTH_VAL                   ",Tcontrol_t,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]);
   ALLOC2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH                       ,"out_CONTEXT_DECOD_UNIT_DEPTH                       ",Tdepth_t  ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]);
+
+  ALLOC1_SC_SIGNAL(out_NB_INST_DECOD_ALL                              ,"out_NB_INST_DECOD_ALL                              ",Tcounter_t,_param->_nb_context);
+  ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_UNIT_DECOD_ALL                   ," in_NB_INST_DECOD_UNIT_DECOD_ALL                   ",Tcounter_t,_param->_nb_context);
+  ALLOC1_SC_SIGNAL(out_NB_INST_CONTEXT_STATE_DECOD_ALL                ,"out_NB_INST_CONTEXT_STATE_DECOD_ALL                ",Tcounter_t,_param->_nb_context);
   
   /********************************************************
@@ -182,4 +186,8 @@
         }
 
+  INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_NB_INST_DECOD_ALL                                ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_NB_INST_DECOD_UNIT_DECOD_ALL                     ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_NB_INST_CONTEXT_STATE_DECOD_ALL                  ,_param->_nb_context);
+
   msg(_("<%s> : Start Simulation ............\n"),name.c_str());
     
@@ -282,4 +290,8 @@
   DELETE2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH_VAL                     ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]);
   DELETE2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH                         ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]);
+
+  DELETE1_SC_SIGNAL(out_NB_INST_DECOD_ALL                                ,_param->_nb_context);
+  DELETE1_SC_SIGNAL( in_NB_INST_DECOD_UNIT_DECOD_ALL                     ,_param->_nb_context);
+  DELETE1_SC_SIGNAL(out_NB_INST_CONTEXT_STATE_DECOD_ALL                  ,_param->_nb_context);
     }
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h	(revision 108)
@@ -133,4 +133,12 @@
   public    : SC_OUT(Tcontrol_t           ) *** out_CONTEXT_DECOD_UNIT_DEPTH_VAL                      ;//[nb_decod_unit][nb_decod_unit_context]
   public    : SC_OUT(Tdepth_t             ) *** out_CONTEXT_DECOD_UNIT_DEPTH                          ;//[nb_decod_unit][nb_decod_unit_context]
+
+    // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_OUT(Tcounter_t           ) ** out_NB_INST_DECOD_ALL                                  ;//[nb_context]
+
+  public    : SC_IN (Tcounter_t           ) **  in_NB_INST_DECOD_UNIT_DECOD_ALL                       ;//[nb_context]
+
+  public    : SC_OUT(Tcounter_t           ) ** out_NB_INST_CONTEXT_STATE_DECOD_ALL                    ;//[nb_context]
+
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
@@ -177,4 +185,5 @@
   public  : void        genMealy_event            (void);
   public  : void        genMealy_depth            (void);
+  public  : void        genMealy_nb_inst          (void);
 #endif					       
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h	(revision 108)
@@ -54,4 +54,5 @@
                         uint32_t              * size_depth                           ,
                         uint32_t              * nb_branch_speculated                 ,
+                        uint32_t                size_nb_inst_decod                   ,
                         uint32_t                is_toplevel=false);
 //   public : Parameters  (Parameters & param) ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp	(revision 108)
@@ -176,4 +176,15 @@
 # endif     
       
+	log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Method - genMealy_nb_inst"),_name.c_str());
+
+	SC_METHOD (genMealy_nb_inst);
+	dont_initialize ();
+// 	sensitive << (*(in_CLOCK)).neg(); // don't need internal register
+        for (uint32_t i=0; i<_param->_nb_context; ++i)
+            sensitive << (*( in_NB_INST_DECOD_UNIT_DECOD_ALL [i]));
+
+# ifdef SYSTEMCASS_SPECIFIC
+	// List dependency information
+# endif    
 	
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp	(revision 108)
@@ -155,5 +155,14 @@
       _ALLOC2_SIGNAL_OUT(out_CONTEXT_DECOD_UNIT_DEPTH                          ,"DECOD_UNIT_DEPTH"              ,Tdepth_t             ,_param->_size_depth  ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]);
     }
-    
+
+    // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      ALLOC1_INTERFACE("nb_inst",OUT,EAST,_("nb inst"),_param->_nb_context);
+
+      ALLOC1_SIGNAL_OUT(out_NB_INST_DECOD_ALL                                  ,"DECOD_ALL"                     ,Tcounter_t           ,_param->_size_nb_inst_decod);
+      ALLOC1_SIGNAL_IN ( in_NB_INST_DECOD_UNIT_DECOD_ALL                       ,"DECOD_UNIT_DECOD_ALL"          ,Tcounter_t           ,_param->_size_nb_inst_decod);
+      ALLOC1_SIGNAL_OUT(out_NB_INST_CONTEXT_STATE_DECOD_ALL                    ,"CONTEXT_STATE_DECOD_ALL"       ,Tcounter_t           ,_param->_size_nb_inst_decod);
+    }
+
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp	(revision 108)
@@ -87,4 +87,8 @@
         DELETE2_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH_VAL                     ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],1);
         DELETE2_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH                         ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth);
+
+        DELETE1_SIGNAL(out_NB_INST_DECOD_ALL                                ,_param->_nb_context,_param->_size_nb_inst_decod);
+        DELETE1_SIGNAL( in_NB_INST_DECOD_UNIT_DECOD_ALL                     ,_param->_nb_context,_param->_size_nb_inst_decod);
+        DELETE1_SIGNAL(out_NB_INST_CONTEXT_STATE_DECOD_ALL                  ,_param->_nb_context,_param->_size_nb_inst_decod);
       }
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_nb_inst.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_nb_inst.cpp	(revision 108)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_nb_inst.cpp	(revision 108)
@@ -0,0 +1,42 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_front_end {
+namespace front_end {
+namespace front_end_glue {
+
+#undef  FUNCTION
+#define FUNCTION "Front_end_Glue::genMealy_nb_inst"
+  void Front_end_Glue::genMealy_nb_inst (void)
+  {
+    log_begin(Front_end_Glue,FUNCTION);
+
+    for (uint32_t i=0; i<_param->_nb_context; ++i)
+      {
+        Tcounter_t nb_inst = PORT_READ(in_NB_INST_DECOD_UNIT_DECOD_ALL [i]);
+
+        PORT_WRITE(out_NB_INST_DECOD_ALL               [i], nb_inst);
+        PORT_WRITE(out_NB_INST_CONTEXT_STATE_DECOD_ALL [i], nb_inst);
+      }
+
+    log_end(Front_end_Glue,FUNCTION);
+  };
+
+}; // end namespace front_end_glue
+}; // end namespace front_end
+}; // end namespace multi_front_end
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters.cpp	(revision 108)
@@ -28,4 +28,5 @@
                           uint32_t              * size_depth                           ,
                           uint32_t              * nb_branch_speculated                 ,
+                          uint32_t                size_nb_inst_decod                   ,
                           uint32_t                is_toplevel):
     morpheo::behavioural::Parameters()
@@ -55,5 +56,6 @@
         _size_instruction_address = size_address;
         _size_depth               = max<uint32_t>(size_depth,_nb_context);
-        
+        _size_nb_inst_decod       = size_nb_inst_decod;
+
         _have_port_context_id     = _size_context_id > 0;
         _have_port_depth          = _size_depth > 0;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp	(revision 108)
@@ -28,6 +28,18 @@
       {
         log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"  * PREDICT [%d]",i);
+
+	Tcontrol_t val          = PORT_READ(in_PREDICT_VAL          [i]);
+	Tcontrol_t register_ack = PORT_READ(in_PREDICT_REGISTER_ACK [i]);
+	Tcontrol_t sort_val     = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_VAL   [i]):true;
+	Tcontrol_t victim_ack   = (_param->_have_port_victim)?PORT_READ(in_PREDICT_VICTIM_ACK [i]):true;
+
+        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * val          : %d",val         );
+        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * register_ack : %d",register_ack);
+        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * sort_val     : %d",sort_val    );
+        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * victim_ack   : %d",victim_ack  );
+	
 	Tptr_t          index       = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_INDEX [i]):0;
-	Tcontrol_t      hit         = PORT_READ(in_PREDICT_REGISTER_HIT         [i][index]);
+        Tcontrol_t      hit         = // (_param->_have_port_victim)?sort_val:
+                                      PORT_READ(in_PREDICT_REGISTER_HIT [i][index]);
 	Tgeneral_data_t address_src = PORT_READ(in_PREDICT_REGISTER_ADDRESS_SRC [i][index]);
 
@@ -44,18 +56,8 @@
 	PORT_WRITE(out_PREDICT_IS_ACCURATE  [i],PORT_READ(in_PREDICT_REGISTER_IS_ACCURATE   [i][index]));
 
-	Tcontrol_t val          = PORT_READ(in_PREDICT_VAL          [i]);
-	Tcontrol_t register_ack = PORT_READ(in_PREDICT_REGISTER_ACK [i]);
-	Tcontrol_t sort_val     = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_VAL   [i]):true;
-	Tcontrol_t victim_ack   = (_param->_have_port_victim)?PORT_READ(in_PREDICT_VICTIM_ACK [i]):true;
-
-        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * val          : %d",val         );
-        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * register_ack : %d",register_ack);
-        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * sort_val     : %d",sort_val    );
-        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * victim_ack   : %d",victim_ack  );
-	
 	PORT_WRITE(out_PREDICT_ACK            [i], (
 //                                                  val          and 
                                                     register_ack and
-                                                    sort_val     and
+//                                                  sort_val     and
                                                     victim_ack
                                                     ));
@@ -63,5 +65,5 @@
                                                     val          and 
 //                                                  register_ack and
-                                                    sort_val     and
+//                                                  sort_val     and
                                                     victim_ack
                                                     ));
@@ -71,6 +73,6 @@
 	PORT_WRITE(out_PREDICT_VICTIM_VAL     [i], (
                                                     val          and 
-                                                    register_ack and
-                                                    sort_val     // and
+                                                    register_ack // and
+//                                                  sort_val     and
 //                                                  victim_ack
                                                     ));
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp	(revision 108)
@@ -54,4 +54,5 @@
 	    //  * context is the same
 	    //  * address_src must be higher that the address, because the address lower is previous the current pc.
+            //  * prediction is no accurate is address_dest is not valid.
 	    PORT_WRITE(out_PREDICT_HIT          [i][j],hit);
 	    PORT_WRITE(out_PREDICT_ADDRESS_SRC  [i][j],reg_BTB[num_bank][j]._address_src );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp	(revision 108)
@@ -224,9 +224,11 @@
 		                       dest,"out_PREDICT_"+toString(i)+"_"+toString(j)+"_ADDRESS_SRC");
 
-	      // out_OUTPUT_VAL     -> glue
-	      // out_OUTPUT_INDEX   -> glue
-	      // out_OUTPUT_ADDRESS -> no exist
 	    }
-	}
+
+          // 1 output
+          // out_OUTPUT_VAL     -> glue
+          // out_OUTPUT_INDEX   -> glue
+          // out_OUTPUT_ADDRESS -> no exist
+        }
 
 	//================================================================
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp	(revision 108)
@@ -126,4 +126,9 @@
                       if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i])
                         reg_UPT_EMPTY [i] = false;
+
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_TOP             : %d",reg_UPT_TOP            [i]);
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_TOP_EVENT       : %d",reg_UPT_TOP_EVENT      [i]);
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_UPDATE          : %d",reg_UPT_UPDATE         [i]);
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_EMPTY           : %d",reg_UPT_EMPTY          [i]);
                     }
 
@@ -210,5 +215,5 @@
 	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * miss_decod    : %d",miss_decod);
 	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * upt_ptr_write : %d",upt_ptr_write);
-	      
+
               if (miss_ifetch or miss_decod)
 		{
@@ -218,5 +223,4 @@
                     throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state."));
 #endif
-                  
                   if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
                     {
@@ -312,124 +316,8 @@
               reg_UPT_EMPTY   [context] = false;
 //            reg_UPT_UPDATE  [context] = reg_UPT_TOP [context];
+
+//               if (miss_ifetch or miss_decod)
+//                 reg_UPT_TOP_EVENT [context] = reg_UPT_TOP [context];
 	    }
-
-	// ===================================================================
-	// =====[ BRANCH_COMPLETE ]===========================================
-	// ===================================================================
-        
-        // The branch is complete
-        //   * Hit  prediction : 
-        //     * update status
-        //   * Miss prediction :
-	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
-	  if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])
-	    {
-	      Tcontext_t context   = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
-	      Tdepth_t   depth     = (_param->_have_port_depth     )?PORT_READ(in_BRANCH_COMPLETE_DEPTH      [i]):0;
-              Tcontrol_t miss      = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];
-              Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE            [i];
-              Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST    [i];
-
-	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * BRANCH_COMPLETE[%d] - Accepted",i);
-	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * context    : %d",context);
-	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * depth      : %d",depth);
-	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * miss       : %d",miss);
-	      
-              if (miss)
-		{
-                  // Have a miss !!!
-                  // Flush UPFT
-                  flush_UFPT [context] = true;
-                  
-                  // Flush UPT
-                  uint32_t top        = reg_UPT_TOP [context];
-                  uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; 
-
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * top        : %d",top);
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * new_update : %d",new_update);
-
-                  for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];
-                                j!=top; 
-                                j=(j+1)%_param->_size_upt_queue[context])
-                    reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;
-                  
-                  
-//                reg_UPT_BOTTOM    [context];
-                  reg_UPT_TOP       [context] = depth;
-                  reg_UPT_TOP_EVENT [context] = top;
-
-                  if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context])
-                    reg_UPT_EMPTY [context] = true;
-
-#ifdef DEBUG_TEST
-                  if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
-                    throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
-#endif
-                  
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);
-                  reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;
-                  
-                  Taddress_t    address_src         = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
-                  event_state_t event_state         = reg_EVENT_STATE [context];
-                  bool          previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
-                                                       (event_state == EVENT_STATE_MISS_FLUSH_UPT          ) or
-                                                       (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
-                                                       (event_state == EVENT_STATE_EVENT_FLUSH_UPT));
-//                   bool          update_ras          = (new_update != depth);
-
-//                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * update_ras : %d",update_ras);
-
-                  if (reg_UFPT_NB_NEED_UPDATE [context] > 0)
-                    {
-                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);
-                      reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT;
-                    }
-                  else
-                    {
-//                       if (not previous_update_ras)
-                        {
-                          // have ras prediction ?
-                          log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context);
-
-                          reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT;
-             
-                        }
-                    }
-
-                  if (not previous_update_ras)
-                    {
-                      reg_UPT_UPDATE [context]  = new_update;
-                    }
-                  // else no update
-
-                  reg_EVENT_DEPTH           [context] = depth;
-                  reg_EVENT_ADDRESS_SRC     [context] = address_src; // delay_slot is compute in Context_State
-                  reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
-                  reg_EVENT_ADDRESS_DEST    [context] = good_addr;
-		}
-	      else
-		{
-                  // Hit case
-
-#ifdef DEBUG_TEST
-                  if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
-                    throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
-#endif
-                    
-                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);
-                  reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;
-		}
-
-	      // In all case : update good_take
-	      reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take    = good_take;
-
-              // Write address_dest if need read register
-              Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
-              
-              if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or
-                  (condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK   ) or
-                  (condition == BRANCH_CONDITION_READ_STACK                       ) )
-                reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr;
-            }
 
 	// ===================================================================
@@ -599,4 +487,128 @@
         }
 
+
+	// ===================================================================
+	// =====[ BRANCH_COMPLETE ]===========================================
+	// ===================================================================
+        
+        // The branch is complete
+        //   * Hit  prediction : 
+        //     * update status
+        //   * Miss prediction :
+	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
+	  if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])
+	    {
+	      Tcontext_t context   = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
+	      Tdepth_t   depth     = (_param->_have_port_depth     )?PORT_READ(in_BRANCH_COMPLETE_DEPTH      [i]):0;
+              Tcontrol_t miss      = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];
+              Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE            [i];
+              Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST    [i];
+
+	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * BRANCH_COMPLETE[%d] - Accepted",i);
+	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * context    : %d",context);
+	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * depth      : %d",depth);
+	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * miss       : %d",miss);
+	      
+              if (miss)
+		{
+                  // Have a miss !!!
+                  // Flush UPFT
+                  flush_UFPT [context] = true;
+                  
+                  // Flush UPT
+                  uint32_t top        = reg_UPT_TOP [context];
+                  uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; 
+
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * top        : %d",top);
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * new_update : %d",new_update);
+
+                  for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];
+                                j!=top; 
+                                j=(j+1)%_param->_size_upt_queue[context])
+                    reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;
+                  
+                  
+//                reg_UPT_BOTTOM    [context];
+                  reg_UPT_TOP       [context] = depth;
+                  reg_UPT_TOP_EVENT [context] = top;
+
+                  if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context])
+                    reg_UPT_EMPTY [context] = true;
+
+#ifdef DEBUG_TEST
+                  if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
+                    throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
+#endif
+                  
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);
+                  reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;
+                  
+                  Taddress_t    address_src         = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
+                  event_state_t event_state         = reg_EVENT_STATE [context];
+                  bool          previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
+                                                       (event_state == EVENT_STATE_MISS_FLUSH_UPT          ) or
+                                                       (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
+                                                       (event_state == EVENT_STATE_EVENT_FLUSH_UPT));
+//                   bool          update_ras          = (new_update != depth);
+
+//                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * update_ras : %d",update_ras);
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * previous_update_ras : %d",previous_update_ras);
+
+                  if (reg_UFPT_NB_NEED_UPDATE [context] > 0)
+                    {
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);
+                      reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT;
+                    }
+                  else
+                    {
+//                       if (not previous_update_ras)
+                        {
+                          // have ras prediction ?
+                          log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context);
+
+                          reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT;
+             
+                        }
+                    }
+
+                  if (not previous_update_ras)
+                    {
+                      reg_UPT_UPDATE [context]  = new_update;
+                    }
+                  // else no update
+
+                  reg_EVENT_DEPTH           [context] = depth;
+                  reg_EVENT_ADDRESS_SRC     [context] = address_src; // delay_slot is compute in Context_State
+                  reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
+                  reg_EVENT_ADDRESS_DEST    [context] = good_addr;
+		}
+	      else
+		{
+                  // Hit case
+
+// #ifdef DEBUG_TEST
+//                   if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
+//                     throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
+// #endif
+
+                  if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
+                    {
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);
+                      reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;
+                    }
+		}
+
+	      // In all case : update good_take
+	      reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take    = good_take;
+
+              // Write address_dest if need read register
+              Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
+              
+              if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or
+                  (condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK   ) or
+                  (condition == BRANCH_CONDITION_READ_STACK                       ) )
+                reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr;
+            }
+
  	// ===================================================================
 	// =====[ BRANCH_EVENT ]==============================================
@@ -695,18 +707,42 @@
                     uint32_t bottom     = reg_UPT_BOTTOM [i];
                     uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; 
-                    uint32_t full       = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]);
+                    bool     full       = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]);
+//                     bool     empty      = reg_UPT_EMPTY [i];
+
                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * top        : %d",top);
                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * depth      : %d",depth);
                     log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * new_update : %d",new_update);
 
-                    // Test empty
-                    if (not reg_UPT_EMPTY [i])
+                    event_state_t event_state         = reg_EVENT_STATE [i];
+                    bool          previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
+                                                         (event_state == EVENT_STATE_MISS_FLUSH_UPT          ) or
+                                                         (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
+                                                         (event_state == EVENT_STATE_EVENT_FLUSH_UPT));
+
+                    bool find = false; // have slot to update ???
+
+                    // flush all slot after the event
+                    for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];
+                         j!=top; 
+                         j=(j+1)%_param->_size_upt_queue[i])
+                      if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and
+                          (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY))
+                        {
+                          find = true;
+                          reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;
+                        }
+                    
+                    if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and
+                        (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY))
                       {
-#ifdef DEBUG_TEST
-                        if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
-                          throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
-#endif
+                        find = true;
                         reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;
-
+                      }
+
+                    log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * find       : %d",find);
+                    
+                    // Test if have update slot
+                    if (find)
+                      {
                         // flush all slot after the event
                         for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];
@@ -714,25 +750,23 @@
                              j=(j+1)%_param->_size_upt_queue[i])
                           reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;
+
+                        reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;
+                        
+                        // reg_UPT_BOTTOM    [i];
+                        // TODO : special case : event is an exception on branch, also depth is not valid
+                        reg_UPT_TOP       [i] = depth; // depth is again valid
+                        reg_UPT_TOP_EVENT [i] = top;
+                        
+                        if (bottom == reg_UPT_TOP [i])
+                          reg_UPT_EMPTY [i] = true;
                       }
+
+                    bool          update_ras = find and ((top != depth) or full);
+                    
+                    log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * update_ras : %d",update_ras);
+                    
+                    if (not previous_update_ras and update_ras)
+                      reg_UPT_UPDATE [i]  = new_update;
               
-//                  reg_UPT_BOTTOM    [i];
-                    // TODO : special case : event is an exception on branch, also depth is not valid
-                    reg_UPT_TOP       [i] = depth; // depth is again valid
-                    reg_UPT_TOP_EVENT [i] = top;
-
-                    if (bottom == reg_UPT_TOP [i])
-                      reg_UPT_EMPTY [i] = true;
-
-                    reg_EVENT_VAL     [i] = true;
-                    reg_EVENT_UPT_PTR [i] = depth;
-                    event_state_t event_state         = reg_EVENT_STATE [i];
-                    bool          previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
-                                                         (event_state == EVENT_STATE_MISS_FLUSH_UPT          ) or
-                                                         (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
-                                                         (event_state == EVENT_STATE_EVENT_FLUSH_UPT));
-                    bool          update_ras          = (top != depth) or full;
-
-                    log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * update_ras : %d",update_ras);
-                    
                     // new state :
                     //   * test if ufpt is empty
@@ -741,4 +775,7 @@
                     //            * ok : nothing
                     //            * ko : flush upt
+                    reg_EVENT_VAL     [i] = true;
+                    reg_EVENT_UPT_PTR [i] = depth;
+
                     if (reg_UFPT_NB_NEED_UPDATE [i] > 0)
                       {
@@ -766,12 +803,11 @@
                         else
                           {
+                            // special case : nothing
+                            reg_EVENT_VAL     [i] = false;
+
                             reg_EVENT_STATE [i] = EVENT_STATE_OK;
                           }
                       }
-                    
-                    if (not previous_update_ras and update_ras)
-                      {
-                        reg_UPT_UPDATE [i]  = new_update;
-                      }
+
                     // else no update
                     
@@ -817,8 +853,12 @@
                 {
                   for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
-                    {
-                      reg_UFPT_NB_UPDATE [i] ++;
-                      reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT;
-                    }
+                    // EMPTY : no event
+                    // END   : already update
+                    // EVENT : previous event
+                    if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state == UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
+                      {
+                        reg_UFPT_NB_UPDATE [i] ++;
+                        reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT;
+                      }
 
                   // TOP is next write slot : last slot is TOP-1
@@ -862,7 +902,7 @@
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_STATE           : %s"  ,toString(reg_EVENT_STATE [i]).c_str());
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_DEPTH           : %d"  ,reg_EVENT_DEPTH           [i]);
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_ADDRESS_SRC     : %.8x",reg_EVENT_ADDRESS_SRC     [i]);
+        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_ADDRESS_SRC     : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC     [i],reg_EVENT_ADDRESS_SRC     [i]<<2);
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_ADDRESS_DEST_VAL: %d"  ,reg_EVENT_ADDRESS_DEST_VAL[i]);
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_ADDRESS_DEST    : %.8x",reg_EVENT_ADDRESS_DEST    [i]);
+        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_ADDRESS_DEST    : %.8x (%.8x)",reg_EVENT_ADDRESS_DEST    [i],reg_EVENT_ADDRESS_DEST    [i]<<2);
 
 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * Update_Fetch_Prediction_Table   [%d]",i);
@@ -914,4 +954,15 @@
       }
 #endif
+
+#ifdef DEBUG_TEST
+    for (uint32_t i=0; i<_param->_nb_context; i++)
+      {
+        if (reg_UFPT_NB_NEED_UPDATE [i] > _param->_size_ufpt_queue[i])
+          throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_NEED_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_NEED_UPDATE [i],_param->_size_ufpt_queue[i]));
+        if (reg_UFPT_NB_UPDATE [i] > _param->_size_ufpt_queue[i])
+          throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_UPDATE [i],_param->_size_ufpt_queue[i]));
+      }
+#endif
+
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp	(revision 108)
@@ -68,4 +68,7 @@
   ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE               ,"out_DECOD_NO_EXECUTE               ",Tcontrol_t           ,_param->_sum_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT            ,"out_DECOD_IS_DELAY_SLOT            ",Tcontrol_t           ,_param->_sum_inst_decod);
+#ifdef DEBUG
+  ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS                  ,"out_DECOD_ADDRESS                  ",Tgeneral_data_t      ,_param->_sum_inst_decod);
+#endif
   ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT             ,"out_DECOD_ADDRESS_NEXT             ",Tgeneral_data_t      ,_param->_sum_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT             ,"out_DECOD_HAS_IMMEDIAT             ",Tcontrol_t           ,_param->_sum_inst_decod);
@@ -116,4 +119,5 @@
   ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL             ," in_NB_INST_COMMIT_ALL             ",Tcounter_t           ,_param->_nb_context);
   ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM             ," in_NB_INST_COMMIT_MEM             ",Tcounter_t           ,_param->_nb_context);
+  ALLOC1_SC_SIGNAL(out_NB_INST_DECOD_ALL              ,"out_NB_INST_DECOD_ALL              ",Tcounter_t           ,_param->_nb_context);
   ALLOC1_SC_SIGNAL(out_DEPTH_MIN                      ,"out_DEPTH_MIN                      ",Tdepth_t             ,_param->_nb_context);
   ALLOC1_SC_SIGNAL(out_DEPTH_MAX                      ,"out_DEPTH_MAX                      ",Tdepth_t             ,_param->_nb_context);
@@ -156,4 +160,7 @@
   INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NO_EXECUTE               ,_param->_sum_inst_decod);
   INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IS_DELAY_SLOT            ,_param->_sum_inst_decod);
+#ifdef DEBUG
+  INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS                  ,_param->_sum_inst_decod);
+#endif
   INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS_NEXT             ,_param->_sum_inst_decod);
   INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_HAS_IMMEDIAT             ,_param->_sum_inst_decod);
@@ -208,4 +215,5 @@
   INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_ALL             ,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_MEM             ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Front_end,out_NB_INST_DECOD_ALL              ,_param->_nb_context);
   if (_param->_have_port_depth)
     {
@@ -317,4 +325,7 @@
   DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE               ,_param->_sum_inst_decod);
   DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT            ,_param->_sum_inst_decod);
+#ifdef DEBUG
+  DELETE1_SC_SIGNAL(out_DECOD_ADDRESS                  ,_param->_sum_inst_decod);
+#endif
   DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT             ,_param->_sum_inst_decod);
   DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT             ,_param->_sum_inst_decod);
@@ -365,4 +376,5 @@
   DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL             ,_param->_nb_context);
   DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM             ,_param->_nb_context);
+  DELETE1_SC_SIGNAL(out_NB_INST_DECOD_ALL              ,_param->_nb_context);
   DELETE1_SC_SIGNAL(out_DEPTH_MIN                      ,_param->_nb_context);
   DELETE1_SC_SIGNAL(out_DEPTH_MAX                      ,_param->_nb_context);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h	(revision 108)
@@ -94,4 +94,7 @@
   public    : SC_OUT(Tcontrol_t           ) ** out_DECOD_NO_EXECUTE                ;//[sum_inst_decod]
   public    : SC_OUT(Tcontrol_t           ) ** out_DECOD_IS_DELAY_SLOT             ;//[sum_inst_decod]
+#ifdef DEBUG
+  public    : SC_OUT(Tgeneral_data_t      ) ** out_DECOD_ADDRESS                   ;//[sum_inst_decod]
+#endif
   public    : SC_OUT(Tgeneral_data_t      ) ** out_DECOD_ADDRESS_NEXT              ;//[sum_inst_decod]
   public    : SC_OUT(Tcontrol_t           ) ** out_DECOD_HAS_IMMEDIAT              ;//[sum_inst_decod]
@@ -152,4 +155,5 @@
   public    : SC_IN (Tcounter_t           ) **  in_NB_INST_COMMIT_ALL               ;//[nb_context]
   public    : SC_IN (Tcounter_t           ) **  in_NB_INST_COMMIT_MEM               ;//[nb_context]
+  public    : SC_OUT(Tcounter_t           ) ** out_NB_INST_DECOD_ALL                ;//[nb_context]
                                                                                    
     // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~         
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp	(revision 108)
@@ -97,4 +97,7 @@
       ALLOC1_SIGNAL_OUT (out_DECOD_NO_EXECUTE                 ,"NO_EXECUTE"       ,Tcontrol_t           ,1                                   );
       ALLOC1_SIGNAL_OUT (out_DECOD_IS_DELAY_SLOT              ,"IS_DELAY_SLOT"    ,Tcontrol_t           ,1                                   );
+#ifdef DEBUG
+      ALLOC1_SIGNAL_OUT (out_DECOD_ADDRESS                    ,"ADDRESS"          ,Tgeneral_data_t      ,_param->_size_instruction_address   );
+#endif
       ALLOC1_SIGNAL_OUT (out_DECOD_ADDRESS_NEXT               ,"ADDRESS_NEXT"     ,Tgeneral_data_t      ,_param->_size_instruction_address   );
       ALLOC1_SIGNAL_OUT (out_DECOD_HAS_IMMEDIAT               ,"HAS_IMMEDIAT"     ,Tcontrol_t           ,1                                   );
@@ -175,4 +178,5 @@
       ALLOC1_SIGNAL_IN  ( in_NB_INST_COMMIT_ALL               ,"COMMIT_ALL"       ,Tcounter_t           ,_param->_size_nb_inst_commit);
       ALLOC1_SIGNAL_IN  ( in_NB_INST_COMMIT_MEM               ,"COMMIT_MEM"       ,Tcounter_t           ,_param->_size_nb_inst_commit);
+      ALLOC1_SIGNAL_OUT (out_NB_INST_DECOD_ALL                ,"DECOD_ALL"        ,Tcounter_t           ,_param->_size_nb_inst_decod );
     }
 
@@ -699,4 +703,8 @@
           PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_IS_DELAY_SLOT",
                               dest,"out_DECOD_"+toString(x)+"_IS_DELAY_SLOT");
+#ifdef DEBUG
+          PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_ADDRESS"      ,
+                              dest,"out_DECOD_"+toString(x)+"_ADDRESS"      );
+#endif
           PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_ADDRESS_NEXT" ,
                               dest,"out_DECOD_"+toString(x)+"_ADDRESS_NEXT" );
@@ -809,5 +817,5 @@
           uint32_t y=(_param->_translate_context_id_from_decod_unit[i])[j];
 
-          dest = _name+"_context_state";
+          dest = _name+"_glue";
 #ifdef POSITION
           _component->interface_map (src ,"nb_inst_"+toString(j),
@@ -815,6 +823,6 @@
 #endif
 
-          COMPONENT_MAP(_component,src ,"out_NB_INST_"+toString(j)+"_DECOD_ALL",
-                                   dest, "in_NB_INST_"+toString(y)+"_DECOD_ALL");
+          COMPONENT_MAP(_component,src ,"out_NB_INST_"+toString(j)+           "_DECOD_ALL",
+                                   dest, "in_NB_INST_"+toString(y)+"_DECOD_UNIT_DECOD_ALL");
         }
 
@@ -965,12 +973,10 @@
 
       // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-      //   in_NB_INST_DECOD_ALL                  - component_decod_unit
-
       for (uint32_t i=0; i<_param->_nb_context; ++i)
         {
           dest = _name;
 #ifdef POSITION
-          _component->interface_map (src ,"nb_inst",
-                                     dest,"nb_inst");
+          _component->interface_map (src ,"nb_inst_"+toString(i),
+                                     dest,"nb_inst_"+toString(i));
 #endif
           
@@ -979,4 +985,13 @@
           PORT_MAP(_component,src , "in_NB_INST_"+toString(i)+"_COMMIT_MEM",
                               dest, "in_NB_INST_"+toString(i)+"_COMMIT_MEM");
+
+          dest = _name+"_glue";
+#ifdef POSITION
+          _component->interface_map (src ,"nb_inst_"+toString(i),
+                                     dest,"nb_inst_"+toString(i));
+#endif
+          
+          COMPONENT_MAP(_component,src , "in_NB_INST_"+toString(i)+              "_DECOD_ALL",
+                                   dest,"out_NB_INST_"+toString(i)+"_CONTEXT_STATE_DECOD_ALL");
       }
 
@@ -1218,4 +1233,20 @@
       //  out_CONTEXT_DECOD_UNIT_DEPTH_VAL                      - component_decod_unit
       //  out_CONTEXT_DECOD_UNIT_DEPTH                          - component_decod_unit
+
+      // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+      for (uint32_t i=0; i<_param->_nb_context; ++i)
+        {
+          dest = _name;
+#ifdef POSITION
+          _component->interface_map (src ,"nb_inst_"+toString(i),
+                                     dest,"nb_inst_"+toString(i));
+#endif
+          
+          PORT_MAP(_component,src ,"out_NB_INST_"+toString(i)+"_DECOD_ALL",
+                              dest,"out_NB_INST_"+toString(i)+"_DECOD_ALL");
+
+      //   in_NB_INST_DECOD_UNIT_DECOD_ALL                      - component_decod_unit
+      //  out_NB_INST_CONTEXT_STATE_DECOD_ALL                   - component_context_state
+        }
     }
     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp	(revision 108)
@@ -49,4 +49,7 @@
         DELETE1_SIGNAL(out_DECOD_NO_EXECUTE                 ,_param->_sum_inst_decod,1                                   );
         DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT              ,_param->_sum_inst_decod,1                                   );
+#ifdef DEBUG
+        DELETE1_SIGNAL(out_DECOD_ADDRESS                    ,_param->_sum_inst_decod,_param->_size_instruction_address   );
+#endif
         DELETE1_SIGNAL(out_DECOD_ADDRESS_NEXT               ,_param->_sum_inst_decod,_param->_size_instruction_address   );
         DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT               ,_param->_sum_inst_decod,1                                   );
@@ -102,4 +105,5 @@
         DELETE1_SIGNAL( in_NB_INST_COMMIT_ALL               ,_param->_nb_context,_param->_size_nb_inst_commit);
         DELETE1_SIGNAL( in_NB_INST_COMMIT_MEM               ,_param->_nb_context,_param->_size_nb_inst_commit);
+        DELETE1_SIGNAL(out_NB_INST_DECOD_ALL                ,_param->_nb_context,_param->_size_nb_inst_decod);
 
         DELETE1_SIGNAL(out_DEPTH_MIN                        ,_param->_nb_context,_param->_size_depth  );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp	(revision 107)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp	(revision 108)
@@ -109,4 +109,6 @@
       _array_size_nb_inst_decod [i] = log2(_size_decod_queue[i]+1);
 
+    uint32_t size_nb_inst_decod         = max<uint32_t>(_array_size_nb_inst_decod,_nb_decod_unit);
+
     _param_ifetch_unit = new behavioural::core::multi_front_end::front_end::ifetch_unit::Parameters * [_nb_context];
     for (uint32_t i=0; i<_nb_context; ++i)
@@ -236,5 +238,6 @@
        size_instruction_address              ,
        _array_size_depth                     ,
-       _upt_size_queue                        //_nb_branch_speculated
+       _upt_size_queue                       ,//_nb_branch_speculated
+       size_nb_inst_decod
        );
 
@@ -244,5 +247,5 @@
         _size_instruction_address   = size_instruction_address;
         _size_general_data          = size_general_data;
-        _size_nb_inst_decod         = max<uint32_t>(_array_size_nb_inst_decod,_nb_decod_unit);
+        _size_nb_inst_decod         = size_nb_inst_decod;
         _size_nb_inst_commit        = size_nb_inst_commit;
         _size_depth                 = max<uint32_t>(_array_size_depth,_nb_context);
